KR20100122700A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20100122700A KR20100122700A KR1020090041725A KR20090041725A KR20100122700A KR 20100122700 A KR20100122700 A KR 20100122700A KR 1020090041725 A KR1020090041725 A KR 1020090041725A KR 20090041725 A KR20090041725 A KR 20090041725A KR 20100122700 A KR20100122700 A KR 20100122700A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- dummy metal
- insulating film
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 143
- 239000002184 metal Substances 0.000 claims abstract description 143
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 27
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 20
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 10
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid group Chemical group S(O)(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 5
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 5
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims description 5
- 229910017604 nitric acid Inorganic materials 0.000 claims description 5
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- 230000008878 coupling Effects 0.000 abstract description 6
- 238000010168 coupling process Methods 0.000 abstract description 6
- 238000005859 coupling reaction Methods 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 3
- 230000007261 regionalization Effects 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 2
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that can improve the operating speed of the device by adjusting the size of the air-gap.
In accordance with the demand for high integration and high speed of semiconductor devices, the gap and minimum line width between metal wirings of semiconductor devices are rapidly decreasing, so the RC delay, which is expressed as the product of the resistance of the metal wirings and the charge capacity of the insulating film, increases rapidly. It is becoming.
In addition, the width of the metal wiring is reduced, and the coupling capacitance induced in the insulating film is increased due to the resistance of the metal wiring and the narrow gap between the metal wirings, thereby reducing the operation speed of the device.
Accordingly, various process technologies for reducing the resistance of the metallization and reducing the coupling capacitance have been studied. As a part thereof, in order to increase the operation speed of the semiconductor device, a metal wiring is used as a low resistance wiring such as copper instead of the conventional aluminum wiring, and an SiO 2 film having a conventional dielectric constant of 4.0 as an insulating film formed between the metal wiring or Attempts have been made to use low-k dielectrics having dielectric constants of 3.0 or less in place of a fluorinated silicate glass (FSG) film of 3.5.
However, even a low dielectric film has a problem that it is difficult to obtain a dielectric constant of 2.5 or less, for example, 2.3 to 2.5. Thus, a method of forming an air layer having a dielectric constant of 1 in an insulating film formed between the metal wiring and the metal wiring has been proposed. Here, the air layer artificially formed in the insulating film is called an air-gap.
On the other hand, the air gap is formed by using a void formed in the insulating film according to the process conditions when forming the insulating film, or is formed by removing the insulating film formed between the metal wiring and the metal wiring by injecting an etchant.
However, the above-mentioned method cannot control the size of the air gap, and there is a risk that the etchant for removing the insulating film penetrates into the metal wiring and is lost.
The present invention provides a method of manufacturing a semiconductor device capable of adjusting the size of an air gap formed in the insulating film between the metal wiring and the metal wiring.
In addition, the present invention provides a method of manufacturing a semiconductor device that can reduce the coupling capacitance by adjusting the size of the air-gap.
In addition, the present invention provides a method of manufacturing a semiconductor device that can improve the operation speed of the device by improving the RC signal delay.
In an aspect, a method of manufacturing a semiconductor device according to an embodiment of the present invention may include forming an insulating film on a semiconductor substrate including a wiring forming region and an air-gap forming region, and selectively etching the insulating film to form the wiring. Exposing a formation region and an air-gap formation region, forming metal wirings and dummy metal patterns in the exposed wiring formation region and the air-gap formation region, respectively, and forming the metal wirings and the dummy metal patterns. Forming a first interlayer insulating film on the field and the insulating film, forming holes to expose a portion of the dummy metal pattern by etching the first interlayer insulating film, and injecting an etchant through the holes to form the dummy metal pattern. Removing them.
The insulating film may be formed of any one of an oxide film, a nitride film, a DC (Diamond like carbon) film, an SOG film, a SiC film, a SiOC film, and a SiCN film, or a laminated film thereof.
The metal wiring and the dummy metal pattern are formed to be alternately arranged.
The metal wiring and the dummy metal pattern include a copper film.
The first interlayer insulating film is formed of any one of an oxide film, a nitride film, a DC film, an SOG film, a SiC film, a SiOC film, and a SiCN film.
In the method of manufacturing a semiconductor device according to the embodiment of the present invention, after the forming of the metal wirings and the dummy metal patterns, and before the forming of the first interlayer insulating film, the metal wirings and the dummy metal patterns And forming a diffusion barrier on the insulating film.
The etchant is sulfuric acid (H 2 SO 4 ), nitric acid (HNO 3 ), phosphoric acid (H 3 PO 4 ), hydrofluoric acid (HF), ammonium fluoride (NH 4 F), hydrochloric acid (HCl), hydrogen peroxide (H 2 O 2 ) , Sodium hydroxide (NaOH) and potassium hydroxide (KOH).
In the method of manufacturing a semiconductor device according to an embodiment of the present invention, after removing the dummy metal patterns, a second interlayer insulating layer is formed on the resultant of the semiconductor substrate from which the dummy metal patterns have been removed so as not to fill the holes. And forming an air-gap between the adjacent metal wires.
The second interlayer insulating film is formed of any one of an oxide film, a nitride film, a DC film, an SOG film, a SiC film, a SiOC film, and a SiCN film.
In another aspect, a method of manufacturing a semiconductor device according to an embodiment of the present invention, forming a conductive film on the semiconductor substrate including a wiring formation region and an air-gap formation region, and selectively etching the conductive film to the wiring Forming metal wirings and dummy metal patterns in the formation region and the air-gap formation region, respectively, and insulating an insulating layer between the metal wiring and the dummy metal baton on a semiconductor substrate including the metal wiring and the dummy metal baton. Forming a first interlayer insulating film on the metal wires, the dummy metal patterns, and the insulating film; and forming holes to expose a portion of the dummy metal pattern by etching the first interlayer insulating film. And removing the dummy metal patterns by injecting an etchant through the holes.
Here, the conductive film includes a copper film.
The metal wiring and the dummy metal pattern are formed to be alternately arranged.
The insulating film is formed of any one of an oxide film, a nitride film, a DC (Diamond like carbon) film, an SOG film, an SiC film, an SiOC film, and a SiCN film, or a laminated film thereof.
The first interlayer insulating film is formed of any one of an oxide film, a nitride film, a DC film, an SOG film, a SiC film, a SiOC film, and a SiCN film.
In the method of manufacturing a semiconductor device according to the embodiment of the present invention, after forming the insulating film and before forming the first interlayer insulating film, the diffusion barrier layer is formed on the metal wires, the dummy metal patterns and the insulating film. It further comprises the step of forming.
The etchant is sulfuric acid (H 2 SO 4 ), nitric acid (HNO 3 ), phosphoric acid (H 3 PO 4 ), hydrofluoric acid (HF), ammonium fluoride (NH 4 F), hydrochloric acid (HCl), hydrogen peroxide (H 2 O 2 ) , Sodium hydroxide (NaOH) and potassium hydroxide (KOH).
In the method of manufacturing a semiconductor device according to an embodiment of the present invention, after removing the dummy metal patterns, a second interlayer insulating layer is formed on the resultant of the semiconductor substrate from which the dummy metal patterns have been removed so as not to fill the holes. And forming an air-gap between the adjacent metal wires.
The second interlayer insulating film is formed of any one of an oxide film, a nitride film, a DC film, an SOG film, a SiC film, a SiOC film, and a SiCN film.
After the insulating film is formed on the semiconductor substrate, the insulating film portion corresponding to the metal wiring and the dummy metal pattern forming region is selectively etched to provide the metal wiring and the dummy metal pattern forming region. The dummy metal pattern formation region is a region where an air gap is to be formed. Then, the metal wiring and the dummy metal pattern are formed in the metal wiring and the dummy metal pattern forming regions, respectively, and a first interlayer insulating film covering the metal wiring and the dummy metal pattern is formed. A portion of the first interlayer insulating layer corresponding to the dummy metal pattern is etched to form holes exposing portions of the dummy metal pattern, and an etchant is injected through the holes to remove the dummy metal pattern. A second interlayer insulating film is formed on the resultant of the semiconductor substrate from which the dummy metal patterns are removed to form an air gap between the adjacent metal wires.
As such, the present invention can provide a space in which an air gap is to be formed depending on the etching performed to prepare the metal wiring and the dummy metal pattern forming region, that is, the degree of etching the insulating film. The size of the air gap can be adjusted. Therefore, the present invention can improve the RC delay due to the coupling capacitance, and thus the operating speed of the device can be improved.
In addition, the present invention can remove only the dummy metal pattern by injecting the etchant through the hole exposing only the dummy metal pattern, it is possible to prevent the etching solution from penetrating into the metal wiring when the etching solution is injected. .
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1A to 1D are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.
Referring to FIG. 1A, an insulating layer may be formed to cover the
Next, the
Here, the present invention is an etching performed to provide first and second trenches T1 and T2 exposing the metal wiring forming region and the dummy wiring forming region (air-gap forming region), respectively, that is, the insulating film ( Depending on the degree of etching 107), the size of the subsequent air-gap can be adjusted.
Referring to FIG. 1B, a conductive film, for example, a copper film is formed to fill the first and second trenches T1 and T2 on the
Although not shown, the metal wiring M and the dummy metal pattern DM may be formed by a patterning process other than the damascene process. Specifically, after the conductive film is formed on the semiconductor substrate, a photosensitive film pattern may be formed on the conductive film, and then the conductive film may be patterned using the photosensitive film pattern to form metal wiring and a dummy metal pattern.
Subsequently, a first
In addition, although not shown, a diffusion barrier layer (not shown) is further formed on the metal lines M, the dummy metal patterns DM, and the insulating
Referring to FIG. 1C, the first
Referring to FIG. 1D, an etchant is injected through the holes H to remove the dummy metal patterns. The etchant injected to remove the dummy metal pattern includes sulfuric acid (H 2 SO 4), nitric acid (HNO 3), phosphoric acid (H 3 PO 4), hydrofluoric acid (HF), ammonium fluoride (NH 4 F), hydrochloric acid (HCl), hydrogen peroxide (H 2 O 2), and hydroxide. It may be a solution of either sodium (NaOH) and potassium hydroxide (KOH).
Here, since the hole H exposes only the dummy metal pattern, the etchant does not penetrate the metal wiring when the dummy metal pattern is removed. Therefore, in the process of removing the dummy metal pattern, it is possible to prevent the metal wiring from being lost by the etchant.
Subsequently, a second
Thereafter, a series of well-known subsequent steps are sequentially performed to complete the manufacture of the semiconductor device according to the embodiment of the present invention.
As described above, the present invention provides an etching performed to prepare the first and second trenches T1 and T2 exposing the metal wiring forming region and the dummy wiring forming region, that is, the insulating
In addition, since the present invention can form an air gap having a dielectric constant of 1 in the insulating film to a desired size, it is possible to improve the RC signal delay due to the coupling capacitance. As a result, the operation speed of the device can be improved.
In addition, since the dummy metal pattern may be removed when the etching solution is injected through the hole exposing only the dummy metal pattern, the present invention may prevent the etching solution from penetrating into the metal wiring.
As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
1A to 1D are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.
Explanation of symbols on the main parts of the drawings
100
107: insulating film T: trench
M: Metal wiring DM: Lower metal wiring
108: first interlayer insulating film H: hole
110: second interlayer insulating film A: air-gap
Claims (18)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090041725A KR20100122700A (en) | 2009-05-13 | 2009-05-13 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090041725A KR20100122700A (en) | 2009-05-13 | 2009-05-13 | Method of manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20100122700A true KR20100122700A (en) | 2010-11-23 |
Family
ID=43407550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020090041725A KR20100122700A (en) | 2009-05-13 | 2009-05-13 | Method of manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20100122700A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140011679A (en) * | 2012-07-18 | 2014-01-29 | 삼성전자주식회사 | Non volatile memory devices and methods of manufacturing the same |
| US9337150B2 (en) | 2012-09-05 | 2016-05-10 | Samsung Electronics Co., Ltd. | Semiconductor devices including supporting patterns in gap regions between conductive patterns |
| US9406553B2 (en) | 2014-04-07 | 2016-08-02 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
| US9520348B2 (en) | 2012-05-03 | 2016-12-13 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
-
2009
- 2009-05-13 KR KR1020090041725A patent/KR20100122700A/en not_active Application Discontinuation
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9520348B2 (en) | 2012-05-03 | 2016-12-13 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| US10490444B2 (en) | 2012-05-03 | 2019-11-26 | Samsung Electronics Co., Ltd. | Semiconductor devices having an air gap |
| US10910261B2 (en) | 2012-05-03 | 2021-02-02 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| US11764107B2 (en) | 2012-05-03 | 2023-09-19 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices |
| KR20140011679A (en) * | 2012-07-18 | 2014-01-29 | 삼성전자주식회사 | Non volatile memory devices and methods of manufacturing the same |
| US8975684B2 (en) | 2012-07-18 | 2015-03-10 | Samsung Electronics Co., Ltd. | Methods of forming non-volatile memory devices having air gaps |
| US9041088B2 (en) | 2012-07-18 | 2015-05-26 | Samsung Electronics Co., Ltd. | Non-volatile memory devices having air gaps and methods of manufacturing the same |
| US9773795B2 (en) | 2012-07-18 | 2017-09-26 | Samsung Electronics Co., Ltd. | Semiconductor devices having airgaps and methods of manufacturing the same |
| US9337150B2 (en) | 2012-09-05 | 2016-05-10 | Samsung Electronics Co., Ltd. | Semiconductor devices including supporting patterns in gap regions between conductive patterns |
| US9741608B2 (en) | 2012-09-05 | 2017-08-22 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices including supporting patterns in gap regions between conductive patterns |
| US9406553B2 (en) | 2014-04-07 | 2016-08-02 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
| US9558994B2 (en) | 2014-04-07 | 2017-01-31 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
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| WITN | Withdrawal due to no request for examination |