KR20100098896A - Lead frame used fabricating for semiconductor package and stack package using the same - Google Patents

Lead frame used fabricating for semiconductor package and stack package using the same Download PDF

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KR20100098896A
KR20100098896A KR20090017595A KR20090017595A KR20100098896A KR 20100098896 A KR20100098896 A KR 20100098896A KR 20090017595 A KR20090017595 A KR 20090017595A KR 20090017595 A KR20090017595 A KR 20090017595A KR 20100098896 A KR20100098896 A KR 20100098896A
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paddle
inner lead
lead
semiconductor chip
semiconductor
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KR20090017595A
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Korean (ko)
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김승지
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주식회사 하이닉스반도체
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Publication of KR20100098896A publication Critical patent/KR20100098896A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

PURPOSE: A lead frame for a semiconductor package and a stacked package using the same are provided to overcome a restriction with respect to the length of an inner lead in a highly stacked package forming process using a paddle with a plurality of conductive patterns. CONSTITUTION: A paddle(102) is composed of a plurality of conductive patterns(102a). An inner lead(104) is arranged to surround the paddle. The inner lead includes first inner leads(104a) and second inner leads(104b). The first inner leads are arranged on one side and on the other side of the paddle. The second inner leads are arranged on the upper side and on the lower side of the paddle. An outer lead(106) is expanded to the outside of the first inner leads.

Description

반도체 패키지 제조용 리드프레임 및 이를 이용한 스택 패키지{LEAD FRAME USED FABRICATING FOR SEMICONDUCTOR PACKAGE AND STACK PACKAGE USING THE SAME}LEAD FRAME USED FABRICATING FOR SEMICONDUCTOR PACKAGE AND STACK PACKAGE USING THE SAME

본 발명은 반도체 패키지 제조용 리드프레임 및 이를 이용한 스택 패키지에 관한 것으로, 보다 상세하게는, 다수의 도전 패턴으로 이루어진 패들을 이용한 반도체 패키지 제조용 리드프레임 및 이를 이용한 스택 패키지에 관한 것이다.The present invention relates to a lead frame for manufacturing a semiconductor package and a stack package using the same, and more particularly, to a lead package for manufacturing a semiconductor package using a paddle made of a plurality of conductive patterns and a stack package using the same.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전 되고 있다. 예컨대, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장 작업의 효율성 및 실장 후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다. In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technologies for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

또한, 전기·전자 제품의 소형화와 더불어 고 성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. In addition, as miniaturization of electric and electronic products and high performance are required, various technologies for providing a high capacity semiconductor module have been researched and developed.

고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. As a method for providing a high capacity semiconductor module, there is a high integration of a memory chip, which can be realized by integrating a larger number of cells in a limited space of the semiconductor chip.

그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선 폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 스택(Stack) 기술이 제안되었다. However, such high integration of the memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width. Therefore, a stack technology has been proposed as another method for providing a high capacity semiconductor module.

상기와 같은 스택 기술은 스택 된 2개의 칩을 하나의 패키지 내에 내장시키는 방법과 패키징 된 2개의 단품의 패키지를 스택하는 방법이 있다. 그러나, 상기와 같이 2개의 단품의 패키지를 스택하는 방법은 전기·전자 제품의 소형화되는 추세와 더불어 그에 따른 반도체 패키지의 높이의 한계가 있다.The stack technology described above includes a method of embedding two stacked chips in one package and stacking two packaged packages. However, the method of stacking two single packages as described above has a limit of height of the semiconductor package with the trend of miniaturization of electrical and electronic products.

따라서, 하나의 패키지의 2∼3개의 반도체 칩들을 탑재시키는 스택 패키지(Stack Package) 및 멀티 칩 패키지(Multi Chip Package)에 대한 연구가 최근 들어 활발하게 진행되고 있다. Therefore, research on a stack package and a multi chip package in which two or three semiconductor chips of one package are mounted has been actively conducted in recent years.

그러나, 자세하게 도시하고 설명하지는 않았지만, 전술한 종래 기술의 경우에는, 최소 2개 이상의 반도체 칩 간을 스택하여 구현하는 하이(High) 스택 패키지 형성시, 스택된 각 반도체 칩들과 인너리드 간을 전기적으로 연결하기 위한 와이어를 본딩하기 위해 스택되는 상기 각 반도체 칩의 갯수에 비례하여 인너리드의 길이가 요구되지만, 규격화된 전체 패키지의 크기로 인해, 상기 인너리드의 길이에 제약이 발생하게 된다.However, although not shown and described in detail, in the above-described prior art, when forming a high stack package that is implemented by stacking at least two or more semiconductor chips, the stacked semiconductor chips and the inner lead are electrically connected to each other. Although the length of the inner lead is required in proportion to the number of the respective semiconductor chips stacked to bond the wires for connection, the size of the standardized overall package causes a limitation in the length of the inner lead.

따라서, 상기와 같은 인너리드 길이의 제약으로 인해, 스택되는 반도체 칩의 갯수에 한계를 발생시키게 되어, 결국, 하이 스택 패키지를 구현하기 어렵게 된다.Therefore, the limitation of the inner lead length causes a limit on the number of stacked semiconductor chips, which makes it difficult to implement a high stack package.

본 발명은 인너리드 길이의 제약에 따른 스택되는 반도체 칩 갯수의 한계를 극복한 반도체 패키지 제조용 리드프레임 및 이를 이용한 스택 패키지를 제공한다.The present invention provides a lead frame for manufacturing a semiconductor package that overcomes the limitation of the number of stacked semiconductor chips due to the limitation of inner lead length, and a stack package using the same.

또한, 본 발명은 상기와 같이 스택되는 반도체 칩 갯수의 한계를 극복하여 하이 스택 패키지를 용이하게 구현한 반도체 패키지 제조용 리드프레임 및 이를 이용한 스택 패키지를 제공한다.In addition, the present invention provides a lead package for manufacturing a semiconductor package and a stack package using the same, which easily implements a high stack package by overcoming the limitation of the number of stacked semiconductor chips as described above.

본 발명의 실시예에 따른 반도체 패키지 제조용 리드프레임은, 다수의 도전 패턴으로 이루어진 패들; 상기 패들의 일측 및 타측에 이격해서 각각 배치된 제1인너리드; 상기 제1인너리드와 수직하고 상기 패들의 상측 및 하측에 이격해서 각각 배치된 제2인너리드; 및 상기 제1인너리드 외측으로 연장 배치된 아우터리드;를 포함한다.A lead frame for manufacturing a semiconductor package according to an embodiment of the present invention includes a paddle made of a plurality of conductive patterns; First inner leads spaced apart from one side and the other side of the paddle; A second inner lead perpendicular to the first inner lead and spaced apart from an upper side and a lower side of the paddle; And an outer lead extending outwardly from the first inner lead.

상기 도전 패턴은 등 간격으로 배치된 직사각형 형상인 것을 특징으로 한다.The conductive pattern is characterized in that the rectangular shape arranged at equal intervals.

상기 제1인너리드와 도전 패턴 간은 서로 일대일 대응되도록 배치된 것을 특징으로 한다.The first inner lead and the conductive pattern may be disposed to correspond one to one with each other.

상기 제2인너리드와 도전 패턴 간은 서로 일대일 대응되도록 배치된 것을 특징으로 한다.The second inner lead and the conductive pattern may be disposed to correspond one to one with each other.

또한, 본 발명의 실시예에 따른 반도체 패키지 제조용 리드프레임을 이용한 스택 패키지는, 청구항 1의 기재를 갖는 리드프레임; 상기 리드프레임의 패들 상에 동일한 본딩패드 배열 방향으로 스택된 적어도 둘 이상의 제1반도체 칩; 상기 제1반도체 칩과 제1인너리드 간을 전기적으로 연결하는 제1연결 부재; 상기 제1반도체 칩 상에 상기 제1반도체 칩의 본딩패드 배열 방향과 수직하는 방향으로 본딩패드들이 배열되게 스택된 적어도 둘 이상의 제2반도체 칩; 상기 제2반도체 칩과 제2인너리드 간을 전기적으로 연결하는 제2연결 부재; 및 상기 패들 후면의 각 도전 패턴과 상기 제1 및 제2인너리드 간을 각각 전기적으로 연결하는 제3연결 부재;를 포함한다.In addition, a stack package using a lead frame for manufacturing a semiconductor package according to an embodiment of the present invention, a lead frame having a substrate of claim 1; At least two first semiconductor chips stacked on a paddle of the lead frame in the same bonding pad arrangement direction; A first connection member electrically connecting the first semiconductor chip and a first inner lead; At least two second semiconductor chips stacked on the first semiconductor chip such that bonding pads are arranged in a direction perpendicular to a bonding pad arrangement direction of the first semiconductor chip; A second connecting member electrically connecting the second semiconductor chip and a second inner lead; And a third connection member electrically connecting each conductive pattern on the back surface of the paddle and the first and second inner leads, respectively.

상기 도전 패턴은 등 간격으로 배치된 직사각형 형상인 것을 특징으로 한다.The conductive pattern is characterized in that the rectangular shape arranged at equal intervals.

상기 제1 및 제2반도체 칩과 제1, 제2 및 제3연결 부재를 포함하는 공간적 영역을 밀봉하며, 상기 리드프레임의 아우터리드는 외부로 인출되도록 하는 봉지제를 더 포함한다.The encapsulant further encapsulates the spatial region including the first and second semiconductor chips and the first, second and third connection members, and the outer lead of the lead frame is drawn out to the outside.

본 발명은 스택 패키지 형성시, 다수 개의 도전 패턴을 포함하는 패들을 이용함으로써, 이를 통해 적어도 2개 이상의 반도체 칩을 스택하는 하이 스택 패키지 형성시에도 인너리드 길이의 제약을 극복할 수 있다.According to the present invention, by using a paddle including a plurality of conductive patterns when forming a stack package, it is possible to overcome the limitation of the inner lead length even when forming a high stack package stacking at least two semiconductor chips.

따라서, 본 발명은 스택되는 반도체 칩 갯수의 한계를 극복할 수 있으므로, 하이 스택 패키지를 용이하게 구현할 수 있다.Therefore, the present invention can overcome the limitation of the number of stacked semiconductor chips, it is possible to easily implement a high stack package.

이하에서는 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 1은 본 발명의 실시예에 따른 반도체 패키지 제조용 리드프레임을 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.1 is a cross-sectional view illustrating a lead frame for manufacturing a semiconductor package according to an embodiment of the present invention.

본 발명의 실시예에 따른 반도체 패키지 제조용 리드프레임(100)은 패들(102), 인너리드(104) 및 아우터리드(106)로 이루어진다.The leadframe 100 for manufacturing a semiconductor package according to an exemplary embodiment of the present invention includes a paddle 102, an inner lead 104, and an outer lead 106.

패들(102)은 중앙 부분에 각 반도체 칩(110, 118)이 부착되는 반도체 칩 부착 영역(도시안됨)을 갖는다.The paddle 102 has a semiconductor chip attachment region (not shown) to which the semiconductor chips 110 and 118 are attached at the center portion.

이때, 이러한 패들(102)의 반도체 칩 부착 영역은 다수의 도전 패턴(102a)으로 이루어지며, 이러한 다수의 도전 패턴(102a)은 예를 들면 등 간격으로 배치된 직사각형 형상을 포함한다.At this time, the semiconductor chip attachment region of the paddle 102 is composed of a plurality of conductive patterns 102a, and the plurality of conductive patterns 102a include rectangular shapes arranged at equal intervals, for example.

인너리드(104)는 이러한 반도체 칩 부착 영역을 포함하는 패들(102)의 사면을 둘러싸도록 배치된다.The inner lead 104 is disposed to surround the slope of the paddle 102 including this semiconductor chip attachment region.

이때, 이러한 인너리드(104)는 예를 들면 제1인너리드(104a) 및 제2인너리드(104b)로 나눌 수 있다.In this case, the inner lead 104 may be divided into, for example, a first inner lead 104a and a second inner lead 104b.

제1인너리드(104a)는 패들(102)과 수평하는 방향으로 연장 배치되며, 제2인너리드(104b)는 패들(102)과 수직하는 방향으로 연장 배치된다.The first inner lead 104a extends in a direction parallel to the paddle 102, and the second inner lead 104b extends in a direction perpendicular to the paddle 102.

즉, 제1인너리드(104a)는 패들(102)의 일측 및 타측에 이격해서 각각 배치되며, 제2인너리드(104b)는 제1인너리드(104a)와 수직하고 패들(102)의 상측 및 하측에 이격해서 각각 배치된다.That is, the first inner lead 104a is disposed on one side and the other side of the paddle 102, respectively, and the second inner lead 104b is perpendicular to the first inner lead 104a, and the upper side of the paddle 102 and It is arrange | positioned separately and spaced apart below.

이때, 이러한 제1 및 제2인너리드(104a, 104b)와 도전 패턴(102a)은 서로 각각 일대일 대응되도록 형성된다.In this case, the first and second inner leads 104a and 104b and the conductive pattern 102a are formed to correspond to each other one by one.

아우터리드(106)는 제1인너리드(104a)와 연결됨과 아울러, 제1인너리드(104a)로부터 외측으로 연장 배치되머, 외부 접속 수단으로 사용된다.The outer lead 106 is connected to the first inner lead 104a and extends outward from the first inner lead 104a to be used as an external connection means.

도 2는 본 발명의 실시예에 따른 반도체 패키지 제조용 리드프레임을 이용한 스택 패키지를 설명하기 위해 도시한 단면도이고, 도 3 및 도 4는 본 발명의 실시예에 따른 반도체 패키지 제조용 리드프레임을 이용한 스택 패키지를 설명하기 위해 도시한 평면도로서, 이를 설명하면 다음과 같다.2 is a cross-sectional view illustrating a stack package using a lead frame for manufacturing a semiconductor package according to an embodiment of the present invention, and FIGS. 3 and 4 are stack packages using a lead frame for manufacturing a semiconductor package according to an embodiment of the present invention. As a plan view shown to explain, it will be described as follows.

도 2 내지 도 4에 도시된 바와 같이 본 발명의 실시예에 따른 스택 패키지(200)는, 리드프레임(100), 제1반도체 칩(110), 제1연결 부재(114), 제2반도체 칩(118), 제2연결 부재(124), 제3연결 부재(126) 및 봉지제(122)를 포함한다.As shown in FIGS. 2 to 4, the stack package 200 according to an exemplary embodiment of the present invention may include a lead frame 100, a first semiconductor chip 110, a first connection member 114, and a second semiconductor chip. 118, a second connecting member 124, a third connecting member 126, and an encapsulant 122.

리드프레임(100)은 패들(102), 인너리드(104) 및 아우터리드(106)로 이루어진다.The leadframe 100 consists of a paddle 102, an inner lead 104, and an outer lead 106.

패들(102)은 중앙 부분에 각 반도체 칩(110, 118)이 부착되는 반도체 칩 부착 영역(도시안됨)을 갖는다.The paddle 102 has a semiconductor chip attachment region (not shown) to which the semiconductor chips 110 and 118 are attached at the center portion.

이때, 이러한 패들(102)의 반도체 칩 부착 영역은 다수의 도전 패턴(102a)으로 이루어지며, 이러한 다수의 도전 패턴(102a)은 예를 들면 등 간격으로 배치된 직사각형 형상을 포함한다.At this time, the semiconductor chip attachment region of the paddle 102 is composed of a plurality of conductive patterns 102a, and the plurality of conductive patterns 102a include rectangular shapes arranged at equal intervals, for example.

인너리드(104)는 이러한 반도체 칩 부착 영역을 포함하는 패들(102)의 사면을 둘러싸도록 배치된다.The inner lead 104 is disposed to surround the slope of the paddle 102 including this semiconductor chip attachment region.

이때, 이러한 인너리드(104)는 예를 들면 제1인너리드(104a) 및 제2인너리드(104b)로 나눌 수 있다.In this case, the inner lead 104 may be divided into, for example, a first inner lead 104a and a second inner lead 104b.

제1인너리드(104a)는 패들(102)과 수평하는 방향으로 연장 배치되며, 제2인너리드(104b)는 패들(102)과 수직하는 방향으로 연장 배치된다.The first inner lead 104a extends in a direction parallel to the paddle 102, and the second inner lead 104b extends in a direction perpendicular to the paddle 102.

즉, 제1인너리드(104a)는 패들(102)의 일측 및 타측에 이격해서 각각 배치되며, 제2인너리드(104b)는 제1인너리드(104a)와 수직하고 패들(102)의 상측 및 하측에 이격해서 각각 배치된다.That is, the first inner lead 104a is disposed on one side and the other side of the paddle 102, respectively, and the second inner lead 104b is perpendicular to the first inner lead 104a, and the upper side of the paddle 102 and It is arrange | positioned separately and spaced apart below.

이때, 이러한 제1 및 제2인너리드(104a, 104b)와 도전 패턴(102a)은 서로 각각 일대일 대응되도록 형성된다.In this case, the first and second inner leads 104a and 104b and the conductive pattern 102a are formed to correspond to each other one by one.

아우터리드(106)는 제1인너리드(104a)와 연결됨과 아울러, 제1인너리드(104a)로부터 외측으로 연장 배치되머, 외부 접속 수단으로 사용된다.The outer lead 106 is connected to the first inner lead 104a and extends outward from the first inner lead 104a to be used as an external connection means.

제1반도체 칩(110)은 상면의 에지(Edge)에 제1본딩패드(112)가 다수 개 배치된 적어도 둘 이상이 한 쌍으로 이루어지며, 이러한 적어도 둘 이상이 한 쌍으로 이루어진 제1반도체 칩(110)은 패들(102) 상면의 반도체 칩 부착 영역, 즉, 다수의 도전 패턴(102a) 상에 스택된다. The first semiconductor chip 110 includes a pair of at least two or more pairs of the plurality of first bonding pads 112 disposed on an edge of an upper surface thereof, and the at least two pairs of the first semiconductor chip 110 110 is stacked on the semiconductor chip attachment region on the paddle 102, that is, on the plurality of conductive patterns 102a.

이때, 이러한 제1반도체 칩(110)은 패들(102), 즉, 다수의 도전 패턴(102a)으로 이루어진 반도체 칩 부착 영역 상에 부착시 제1인너리드(104a) 및 제2인너리드(104b)와 각각 수평 및 수직하는 방향으로 배치된다.In this case, the first semiconductor chip 110 may be attached to the paddle 102, that is, the first inner lead 104a and the second inner lead 104b when attached to a semiconductor chip attachment region formed of a plurality of conductive patterns 102a. And are arranged in horizontal and vertical directions, respectively.

또한, 제1반도체 칩(110)은 패들(102)의 도전 패턴(102a) 상에 동일한 제1본딩패드(112) 배열 방향으로 각각 스택된다.In addition, the first semiconductor chip 110 is stacked on the conductive pattern 102a of the paddle 102 in the same first bonding pad 112 arrangement direction.

제1연결 부재(114)는 이러한 패들(102)의 반도체 칩 부착 영역, 즉, 다수의 도전 패턴(102a) 상면에 스택된 제1반도체 칩(110)과 인너리드(104) 간을 전기적으로 연결하기 위해, 제1반도체 칩(110)의 제1본딩패드(112)와 제1인너리드(104a) 간을 연결한다. 이러한 제1연결 부재(114)는 예를 들면 금속와이어를 포함한다.The first connection member 114 electrically connects the semiconductor chip attachment region of the paddle 102, that is, the first semiconductor chip 110 and the inner lead 104 stacked on the upper surface of the plurality of conductive patterns 102a. In order to do so, the first bonding pad 112 of the first semiconductor chip 110 and the first inner lead 104a are connected to each other. The first connection member 114 includes a metal wire, for example.

제2반도체 칩(118)은 상면의 에지(Edge)에 제2본딩패드(120)가 다수 개 배치된 적어도 둘 이상이 한 쌍으로 이루어지며, 이러한 적어도 둘 이상이 한 쌍으로 이루어진 제2반도체 칩(118)은 제1반도체 칩(110) 상면에 스택된다.The second semiconductor chip 118 is formed of a pair of at least two or more in which a plurality of second bonding pads 120 are disposed at an edge of the upper surface, and the at least two of the second semiconductor chips are formed of a pair. 118 is stacked on the top surface of the first semiconductor chip 110.

또한, 제2반도체 칩(118)은 상면에 다수 개 배치된 제2본딩패드(120)를 포함하며, 이러한 제2본딩패드(120)는 예를 들면 에지 패드 타입을 포함한다.In addition, the second semiconductor chip 118 may include a plurality of second bonding pads 120 disposed on an upper surface thereof, and the second bonding pads 120 may include, for example, an edge pad type.

이때, 이러한 제2반도체 칩(118)은 제1반도체 칩(110) 상에 스택시, 제1반도체 칩(110)과 90°도 회전되어 부착된다. 즉, 제2반도체 칩(118)은 제1반도체 칩(110) 상에 스택시, 제1인너리드(104a) 및 제2인너리드(104b)와 각각 수직 및 수평하는 방향으로 배치된다.In this case, when the second semiconductor chip 118 is stacked on the first semiconductor chip 110, the second semiconductor chip 118 is rotated by 90 ° with the first semiconductor chip 110. That is, when the second semiconductor chip 118 is stacked on the first semiconductor chip 110, the second semiconductor chip 118 is disposed in a direction perpendicular to and horizontal to the first inner lead 104a and the second inner lead 104b, respectively.

예컨대, 제2반도체 칩(118)은 제1반도체 칩(110)의 제1본딩패드(112) 배열 방향과 수직하는 방향으로 제2본딩패드(120)가 배열되게 스택된다.For example, the second semiconductor chip 118 is stacked such that the second bonding pads 120 are arranged in a direction perpendicular to the direction in which the first bonding pads 112 of the first semiconductor chip 110 are arranged.

제2연결 부재(124)는 제2반도체 칩(118)과 인너리드(104) 간을 전기적으로 연결하기 위해, 제2반도체 칩(124)의 제2본딩패드(120)와 제2인너리드(104b) 간을 연결하며, 이러한 제2연결 부재(124)는 예를 들면 금속와이어를 포함한다.The second connecting member 124 may electrically connect the second semiconductor chip 118 and the inner lead 104 to the second bonding pad 120 and the second inner lead of the second semiconductor chip 124. 104b), the second connecting member 124 comprises a metal wire, for example.

한편, 적어도 둘 이상의 제1반도체 칩(110) 간, 제1반도체 칩(110)과 제2반도체 칩(124) 및 적어도 둘 이상의 제2반도체 칩(124) 간 사이에는 스페이서(116)가 개재되어, 제1 및 제2연결 부재(114, 124)가 형성될 공간을 확보한다.Meanwhile, a spacer 116 is interposed between at least two first semiconductor chips 110, between the first semiconductor chip 110 and the second semiconductor chip 124, and at least two or more second semiconductor chips 124. In order to secure the space in which the first and second connection members 114 and 124 are to be formed.

제3연결 부재(126)는 제2인너리드(104b)와 전기적으로 연결된 제2반도체 칩(118)을 제1인너리드(104a)와 연결시키기 위해, 제2반도체 칩(118)이 부착된 패들(102) 후면의 각 도전 패턴(102a)과 제1 및 제2인너리드(104a, 104b) 간을 각각 전기적으로 연결한다.The third connection member 126 is a paddle to which the second semiconductor chip 118 is attached to connect the second semiconductor chip 118 electrically connected to the second inner lead 104b to the first inner lead 104a. (102) The conductive patterns 102a on the rear surface are electrically connected to the first and second inner leads 104a and 104b, respectively.

즉, 이러한 제3연결 부재(126)는 각 제2반도체 칩(118)의 소망하는 연결 신호에 대응하도록, 제2반도체 칩(118)이 연결된 제2인너리드(104b)와 패들(102) 후면의 도전 패턴(102a) 간을 전기적으로 연결하고, 이렇게 각 제2반도체 칩(118)의 소망하는 연결 신호에 전기적으로 연결된 패들(102) 후면의 각 도전 패턴(102a)을 소망하는 각 연결 신호에 대응하도록 제1인너리드(104a)와 전기적으로 연결한다.In other words, the third connecting member 126 may have a rear surface of the second inner lead 104b and the paddle 102 to which the second semiconductor chip 118 is connected to correspond to a desired connection signal of each second semiconductor chip 118. The conductive patterns 102a are electrically connected to each other, and each conductive pattern 102a on the back surface of the paddle 102 is electrically connected to the desired connection signal of each second semiconductor chip 118 to each desired connection signal. The first inner lead 104a is electrically connected to the corresponding inner lead 104a.

봉지제(122)는 제1 및 제2반도체 칩(110, 118)과, 제1, 제2 및 제3연결 부재(114, 124, 126)를 외부의 스트레스로부터 보호하기 위해, 제1 및 제2반도체 칩(118, 118)과, 제1, 제2 및 제3연결 부재(114, 124, 126)를 포함하는 공간적 영역을 밀봉하며, 이때, 리드프레임(100)의 아우터리드(106)는 외부로 인출되도록 밀봉한다.The encapsulant 122 is used to protect the first and second semiconductor chips 110 and 118 and the first, second and third connection members 114, 124, and 126 from external stress. Sealing the spatial region including the two semiconductor chips 118 and 118 and the first, second and third connecting members 114, 124 and 126, wherein the outermost 106 of the leadframe 100 Seal it out to the outside.

이러한 봉지제(122)는 예를 들면 EMC(Epoxy Molding Compound)를 포함한다. The encapsulant 122 includes, for example, an epoxy molding compound (EMC).

전술한 바와 같이 본 발명은, 다수 개의 도전 패턴을 포함하는 패들을 이용하여 스택 패키지를 형성함으로써, 상기 다수 개의 도전 패턴으로 인해 적어도 2개 이상의 반도체 칩을 스택하는 하이 스택 패키지 형성시에도 인너리드 길이의 제약을 극복할 수 있다.As described above, in the present invention, the stack package is formed using a paddle including a plurality of conductive patterns, so that an inner lead length is formed even when a high stack package for stacking at least two semiconductor chips due to the plurality of conductive patterns is formed. Can overcome the constraints of

따라서, 상기와 같이 하이 스택 패키지 형성시에도 인너리드 길이의 제약을 극복할 수 있으므로, 스택되는 반도체 칩 갯수의 한계를 극복할 수 있어, 그에 따른 하이 스택 패키지를 용이하게 구현할 수 있다.Therefore, since the limitation of the inner lead length can be overcome even when the high stack package is formed as described above, the limitation of the number of stacked semiconductor chips can be overcome, and thus the high stack package can be easily implemented.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1은 본 발명의 실시예에 따른 반도체 패키지 제조용 리드프레임을 설명하기 위해 도시한 평면도.1 is a plan view showing a lead frame for manufacturing a semiconductor package according to an embodiment of the present invention.

도 2는 본 발명의 실시예에 따른 반도체 패키지 제조용 리드프레임을 이용한 스택 패키지를 설명하기 위해 도시한 단면도.2 is a cross-sectional view illustrating a stack package using a lead frame for manufacturing a semiconductor package according to an embodiment of the present invention.

도 3 및 도 4는 본 발명의 실시예에 따른 반도체 패키지 제조용 리드프레임을 이용한 스택 패키지를 설명하기 위해 도시한 평면도.3 and 4 are plan views illustrating a stack package using a lead frame for manufacturing a semiconductor package according to an embodiment of the present invention.

Claims (7)

다수의 도전 패턴으로 이루어진 패들;A paddle made of a plurality of conductive patterns; 상기 패들의 일측 및 타측에 이격해서 각각 배치된 제1인너리드;First inner leads spaced apart from one side and the other side of the paddle; 상기 제1인너리드와 수직하고 상기 패들의 상측 및 하측에 이격해서 각각 배치된 제2인너리드; 및 A second inner lead perpendicular to the first inner lead and spaced apart from an upper side and a lower side of the paddle; And 상기 제1인너리드 외측으로 연장 배치된 아우터리드;An outer lead extending outwardly from the first inner lead; 를 포함하는 것을 특징으로 하는 리드프레임.Lead frame comprising a. 제 1 항에 있어서,The method of claim 1, 상기 도전 패턴은 등 간격으로 배치된 직사각형 형상인 것을 특징으로 하는 스택 패키지.The conductive pattern is a stack package, characterized in that the rectangular shape arranged at equal intervals. 제 1 항에 있어서,The method of claim 1, 상기 제1인너리드와 도전 패턴 간은 서로 일대일 대응되도록 배치된 것을 특징으로 하는 리드프레임.The lead frame, characterized in that disposed between the first inner lead and the conductive pattern to correspond one to one. 제 1 항에 있어서,The method of claim 1, 상기 제2인너리드와 도전 패턴 간은 서로 일대일 대응되도록 배치된 것을 특징으로 하는 리드프레임.The lead frame, characterized in that disposed between the second inner lead and the conductive pattern to correspond one to one. 청구항 1의 기재를 갖는 리드프레임;A leadframe having the substrate of claim 1; 상기 리드프레임의 패들 상에 동일한 본딩패드 배열 방향으로 스택된 적어도 둘 이상의 제1반도체 칩;At least two first semiconductor chips stacked on a paddle of the lead frame in the same bonding pad arrangement direction; 상기 제1반도체 칩과 제1인너리드 간을 전기적으로 연결하는 제1연결 부재;A first connection member electrically connecting the first semiconductor chip and a first inner lead; 상기 제1반도체 칩 상에 상기 제1반도체 칩의 본딩패드 배열 방향과 수직하는 방향으로 본딩패드들이 배열되게 스택된 적어도 둘 이상의 제2반도체 칩;At least two second semiconductor chips stacked on the first semiconductor chip such that bonding pads are arranged in a direction perpendicular to a bonding pad arrangement direction of the first semiconductor chip; 상기 제2반도체 칩과 제2인너리드 간을 전기적으로 연결하는 제2연결 부재; 및A second connecting member electrically connecting the second semiconductor chip and a second inner lead; And 상기 패들 후면의 각 도전 패턴과 상기 제1 및 제2인너리드 간을 각각 전기적으로 연결하는 제3연결 부재; A third connection member electrically connecting each conductive pattern on the back surface of the paddle with the first and second inner leads; 를 포함하는 것을 특징으로 하는 스택 패키지.Stack package comprising a. 제 5 항에 있어서,The method of claim 5, 상기 도전 패턴은 등 간격으로 배치된 직사각형 형상인 것을 특징으로 하는 스택 패키지.The conductive pattern is a stack package, characterized in that the rectangular shape arranged at equal intervals. 제 5 항에 있어서,The method of claim 5, 상기 제1 및 제2반도체 칩과 제1, 제2 및 제3연결 부재를 포함하는 공간적 영역을 밀봉하며, 상기 리드프레임의 아우터리드는 외부로 인출되도록 하는 봉지제 를 더 포함하는 것을 특징으로 하는 스택 패키지.And a sealing agent sealing the spatial region including the first and second semiconductor chips and the first, second and third connecting members, and the outer frame of the lead frame is drawn out to the outside. Stack package.
KR20090017595A 2009-03-02 2009-03-02 Lead frame used fabricating for semiconductor package and stack package using the same KR20100098896A (en)

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