KR20100028019A - 비휘발성 메모리 및 예측 프로그래밍 방법 - Google Patents

비휘발성 메모리 및 예측 프로그래밍 방법 Download PDF

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Publication number
KR20100028019A
KR20100028019A KR1020097021264A KR20097021264A KR20100028019A KR 20100028019 A KR20100028019 A KR 20100028019A KR 1020097021264 A KR1020097021264 A KR 1020097021264A KR 20097021264 A KR20097021264 A KR 20097021264A KR 20100028019 A KR20100028019 A KR 20100028019A
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KR
South Korea
Prior art keywords
programming
memory
threshold voltage
voltage level
checkpoint
Prior art date
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KR1020097021264A
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English (en)
Korean (ko)
Inventor
라울-애드리안 세르네아
Original Assignee
쌘디스크 코포레이션
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Filing date
Publication date
Priority claimed from US11/733,694 external-priority patent/US7643348B2/en
Priority claimed from US11/733,706 external-priority patent/US7551483B2/en
Application filed by 쌘디스크 코포레이션 filed Critical 쌘디스크 코포레이션
Publication of KR20100028019A publication Critical patent/KR20100028019A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
KR1020097021264A 2007-04-10 2008-04-09 비휘발성 메모리 및 예측 프로그래밍 방법 Withdrawn KR20100028019A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/733,694 US7643348B2 (en) 2007-04-10 2007-04-10 Predictive programming in non-volatile memory
US11/733,694 2007-04-10
US11/733,706 2007-04-10
US11/733,706 US7551483B2 (en) 2007-04-10 2007-04-10 Non-volatile memory with predictive programming

Publications (1)

Publication Number Publication Date
KR20100028019A true KR20100028019A (ko) 2010-03-11

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ID=39712596

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020097021264A Withdrawn KR20100028019A (ko) 2007-04-10 2008-04-09 비휘발성 메모리 및 예측 프로그래밍 방법

Country Status (6)

Country Link
EP (1) EP2135252A2 (enrdf_load_stackoverflow)
JP (1) JP2010524147A (enrdf_load_stackoverflow)
KR (1) KR20100028019A (enrdf_load_stackoverflow)
CN (1) CN101711414B (enrdf_load_stackoverflow)
TW (1) TWI371041B (enrdf_load_stackoverflow)
WO (1) WO2008124760A2 (enrdf_load_stackoverflow)

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* Cited by examiner, † Cited by third party
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Also Published As

Publication number Publication date
EP2135252A2 (en) 2009-12-23
TWI371041B (en) 2012-08-21
WO2008124760A2 (en) 2008-10-16
CN101711414B (zh) 2013-06-26
JP2010524147A (ja) 2010-07-15
TW200907975A (en) 2009-02-16
CN101711414A (zh) 2010-05-19
WO2008124760A3 (en) 2008-11-27

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PA0105 International application

Patent event date: 20091012

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid