TW200907975A - Non-volatile memory and method for predictive programming - Google Patents

Abstract

In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. The checkpoint is an actual programming voltage that programs the memory cell in question to a verified designated threshold voltage level.

Description

200907975 IX. Description of the Invention: [Technical Field of the Invention] The present invention generally relates to non-volatile semiconductor memories such as electrically erasable programmable read only memory (EEPR〇M) and flash EEPROM In particular, it relates to memory and stylized operations, where the number of program verification operations is minimized. [Prior Art] A solid-state memory in the form of a EEPR0M and a flash EEpR〇M capable of carrying a charge, in particular, a card that is sealed as a small form factor has recently become a multi-action and palm-type device ( Especially for storage devices selected for information equipment and consumer electronics. Unlike RAM (random access memory), which is also a solid-state memory, flash memory is non-volatile and retains its stored data even after the power is turned off. Despite the higher cost, flash memory is increasingly used in mass storage applications. Conventional mass storage devices based on rotating magnetic media such as hard disk drives and flexible disks are not suitable for mobile and palm-sized environments. This is because the hard disk drive tends to be bulky, prone to mechanical failure and has higher latency and higher power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory in the form of embedded and removable cards is ideally suited for action and palm due to its small size, low power consumption, more obscurity and higher reliability. In a type environment. , EEPR〇M and electro-programmable read-only memory (EPROM) are erasable and can write new data or |, stylized, non-volatile memory of human memory unit I30505.doc 200907975 . Both utilize floating in the field region of the field effect transistor structure that is positioned between the source and drain regions of the semiconductor substrate (the gate is not connected. The gate is then provided on the floating gate. The amount of charge on the pole of the floating gate controls the threshold voltage characteristic of the transistor. That is, for a given amount of charge on the floating gate, there must be a "turn-on" transistor to allow its source and immersion regions The voltage applied to the control before the conduction is turned on. The floating gate can hold a certain range of charge and can therefore be programmed to be any threshold voltage level within the threshold window. And the maximum threshold level and the size limit of the threshold power window] Hai and other threshold levels correspond to the range of charge that can be programmed to the floating gate. The threshold window generally depends on the characteristics of the memory attack. , operating conditions and history. ^ Each unique, resolvable threshold voltage level within the window can (in principle) be used to represent the unit's explicit memory state. When dividing the threshold voltage into two different regions Each suffix will be able to store one meta-data. Similarly, when the voltage window is divided into two or more different regions, each memory cell will be able to store more than one bit of data. In a common two-state EEPR0M unit, at least a current breakpoint level is established to divide a conduction window into two regions. a field straw is read by a predetermined, fixed voltage, and a breakpoint is used. The reference source (or reference current IREF) is compared to resolve its source/drain current to the memory state. If the current reading is higher than the breakpoint level reading, then the decision cell is in the - logic state (eg,, 0,, State). On the other hand, if the current is less than the breakpoint: the quasi-current, the decision unit is in another logic state (for example, 130505.doc 200907975 heart), because the embarrassing state, the embarrassing state is stored; ^ one-dimensional Digital two-information. The externally stylized reference current source can be used as the breakpoint level current of the memory system. In order to increase the memory capacity, α-knife manufacture is becoming more and more high with the advancement of semiconductor technology. It Flash EEPR〇M device. Another way to increase storage capacity is to store more than two states in each memory cell. For multi-state or multi-bit quasi-EEPR0] VU memory cells, More than one breakpoint divides the conduction window into more than two regions so that each cell can store more than one bit of information. The information that can be stored for a given eepr〇m array is therefore increased with the number of states that each cell can store. U.S. Patent No. 5,172,338 describes an EEPROM or flash EEPROM having a multi-shaped (four) multi-bit memory cell.

U usually stylizes the electrical body used as a memory unit into |, stylized, and state by two mechanisms.热"Hot-electron injection,", applied to: a very high voltage accelerates electrons across the substrate channel region. At the same time, a high voltage applied to the control idler pulls the hot electrons through the thinner gate dielectric to the floating gate In "wearing &", a higher voltage is applied to the gate relative to the substrate. In this way, the electronic substrate is pulled to the inserted floating gate. The memory device can be erased by a number of mechanisms For bribe (10), the memory can be erased as a whole by removing the charge from the floating idler by ultraviolet light. For dirt resistance, the voltage of the south of the vehicle can be applied by controlling the closed pole to The substrate electrically insulates the memory cells by inducing electrons in the floating gate to pass through the thinner oxide to the substrate channel region (ie, 'Fowler_Nordheim tunneling'). Typically, the bitwise tuple In the case of a flash EEPROM, the S memory can be erased all at once or one or more blocks at a time, one of which can be 5丨2 or 5 of the memory.丨2 or more of the byte group. Memory device usually One or more memory cells are mounted on a card. Each memory chip includes an array of memory cells supported by peripheral circuits such as decoders and erase, write and read circuits. Complex memory devices are also operated with external memory controllers that perform intelligent and higher-level memory operations and interface connections. Many commercially successful non-volatile solid-state memory devices are being used today. The device may be flash EEPROM or other types of non-volatile memory cells may be used. U.S. Patent Nos. 5, 〇 7 〇, 〇 32, 5, 〇 95, 344, 5, 315, 541, 5, 343, 063 and 5, 661, 053, Examples of flash memory and systems and methods of making the same are given in U.S. Patent Nos. 5,313,421 and 6,222,762. In particular, U.S. Patent No. 5,57,315,

A flash memory device having a NAND string structure is described in U.S. Patent Nos. 5,903,495 and 6,046,935. Also, the non-volatile memory device is also fabricated from a memory cell having a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. These memory devices utilizing dielectric storage elements have been used by Eitan et al., 'NR 〇M: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell·' » IEEE

Electron Device Letters, Vol. 21, No. 11, 200 (^U, pp. 543-545. The ΟΝΟ dielectric layer extends across the channel between the source and drain diffusion regions. It will be used for a data bit. The charge of the element is positioned adjacent to the drain in the dielectric layer and the charge for the other data bit is located adjacent to the source in the electrical layer 130505.doc 200907975. For example, US Patent No. 5 No. 6, 011, 725 discloses a non-volatile memory cell having a dielectric sandwiched between two ruthenium dioxide layers. The memory storage region is separated by reading the space within the dielectric, respectively. Dual state to implement multi-state data storage. To improve read and program performance, read or program multiple charge storage elements or memory transistors in an array in parallel. Therefore, read or program memory together The "page of the component" in the existing memory architecture, - column

Usually contains staggered pages or it can form a stomach. All memory elements of a page will be read or programmed. The conventional stylization technique using a series of alternating stylization/verification loops is used to deal with the uncertainty in the stylization process. The current limit of the unit is initially increased in response to the relatively large changes in VPGM. However, the growth slows down and eventually stops because the stabilizing of the charge core in the floating gate reduces the effective field used to further (4) float (4). This process appears to be highly non-linear and therefore uses a trial-and-error approach. The calibre/verification program is difficult to use in a few days. This problem is exacerbated by the ability to store the yoke of a few of the suffix units. In essence, it is necessary to perform a check on the possible multiple mothers in the state. For a 16-possible memory, this tone is also a half-length with a body shape. The test step will cause at least 16 sensing operations. In the mechanism of the 28th, there may be even less 仏, Du 方方丁-人, therefore, the 芸 芸 位 quasi-memory unit ("MLC") can be increased, the number of shovel " The verification loop of the a-style/verification mechanism becomes more time consuming. 130505.doc 200907975 Applied by Loc Tu et al. on September 12, 2006, Meth〇d f〇r

Non-volatile Memory with Linear Estimation of Initial Programming Voltage, US Patent Application Serial No. 11/53, 227, discloses a method for estimating an initial stylized voltage by linear estimation. For good stylized performance, the initial programmed voltage VpGMQ and the step size must be optimally selected at the factory. This is done by testing each page of the memory cell. Continuously stylized by a series of voltage pulses with a staircase waveform. a word line coupled to the selected page, wherein verification is performed between pulses until the page is verified to be in a specified mode. The stylized voltage at the time of programmatic verification of the page is used to linearly scale down to the page Estimating the initial value of the stylized voltage and estimating the phase-by-step improvement estimate using the one-pass pass in the second pass. Therefore, using conventional alternate stylization and verification to generate a successful stylization - The final stylized voltage of the page. Next, the final stylized voltage is linearly scaled down to achieve the estimated initial programmed voltage for the page. The scaling of the type is on the total scale of the page level, and does not solve the conventional disadvantage of staging on the unit-by-unit basis and verifying the memory of the site. Ten therefore the ## line is high-capacity and high-efficiency non-volatile The memory is generally versatile, and it is known to have a high-capacity non-volatile memory with improved stylized performance, in which the aforementioned disadvantages are minimized. [Invention] According to one aspect of the present invention, In non-volatile memory with an array of memory cells (where the memory cell can be one of a range of voltage levels), predictive needs are provided: =: 130505.doc -10- 200907975 Voltage level To pre-program a given memory unit to a predetermined target threshold voltage level. In this way, no verification operations need to be performed, thereby greatly improving the performance of the stylized operation. In an embodiment, by proportional Generating a linear function of a programmed voltage level for a given target threshold voltage level to approximate a predetermined function having a predetermined number of units suitable for the memory array The slope given by the mean. The linear function is uniquely determined for the given memory unit by a checkpoint on a predetermined linear function for a given memory unit. The checkpoint is based on stylizing the memory unit to a specified threshold voltage. The actual stylized voltage of the level. The checkpoint of the check april preferably corresponds to the lowest stylized sorrow of the memory unit. The memory is initially stored by, for example, conventional stylization/verification stylization techniques. The body unit is stylized to the checkpoint and verified. In this way, the checkpoint value for the actual stylized voltage necessary to program the memory unit to the specified statistic state is determined. Therefore, the predetermined I and number are Used to determine the stylized voltage value used to program the memory cell to the target threshold voltage: the quasi-programmed power plant is calibrated to generate a checkpoint at the checkpoint threshold voltage level 5 . In the:-embodiment, a plurality of checkpoints can be specified in the range of compressible levels supported by the memory unit. Each checkpoint will be used to: a local joy function near the checkpoint. Use a local predetermined function to predict: programmatically level to the programmed voltage level near the associated checkpoint. + ==Γ= is advantageous because stylized to the target state does not need to be tested. Only verify operations are required to set the number in general - 130505.doc 200907975 points. A change in the result of the error, but such a check that the number of possible memory states can be corrected by appropriate error correction will cause the prediction to be stylized to produce a false error that will be a statistically predictable error, code ("ECC") is handled. The description will be understood from the following description of the preferred embodiments of the invention, and the description will be understood in conjunction with the accompanying drawings. [Embodiment] -$ Memory System

DETAILED DESCRIPTION OF THE INVENTION Each of Figures 1 through 5 illustrates an example memory system, aspects of which. The figure illustrates the conventional stylization technique. 7 through 16 illustrate various aspects and embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of functional blocks of a non-volatile memory chip that can be implemented in accordance with the present invention. The memory chip 1 includes a two-dimensional array of memory cells (10), a control circuit 21G, and peripheral circuits such as a decoder, a read writer circuit, and a multiplexer. It can be addressed by the word line via the column decoder 23 (divided into 23〇α, 23〇β) and by the bit line via the row decoder 260 (split into 26〇Α, 26〇Β) Body array 200 (see also Figures 4 and 5). The read write circuit 27 (divided into 270A, 270B) allows pages of memory cells to be read or programmed in parallel. The data I/O bus 231 is coupled to the read write circuit 27 〇 β. In the preferred embodiment, a page consists of a column adjacent to the memory bank 7G sharing one of the same word lines. In another embodiment, a column of memory cells is divided into a plurality of pages, and a block multiplexer 250 is provided (split into 25A and 250B) to read 130505.doc 200907975 to/write circuit 270. To individual pages. For example, two-page multiplexes formed by odd and even row memory cells, respectively, are applied to the read write circuit. Figure 1 illustrates a preferred configuration 'where access to the memory array 200 is performed by various peripheral circuits in a manner symmetrical on opposite sides of the array to halve the density of the access lines and circuitry on the female side . Therefore, the column decoder is split into column decoders 230A and 230B and the row decoder is split into row decoders 260A and 260B. In the case of dividing a column of memory cells into a plurality of pages, the page multi-worker 250 is also divided into page multiplexers 25 〇 A and 25 0B. Similarly, the read write circuit 27 is split into a read write circuit 27〇 connected to the bit line from the bottom of the array 2〇〇 and connected to the top of the array 2〇〇.

: Line read write circuit 27〇B. In this way, the cost of the read/write module and thus the density of the sensing module 38 is substantially halved. Control circuit 110 is an on-wafer controller that cooperates with read write circuit 27 to perform memory operations on memory array 2〇0. Control circuit 110 typically includes state machine 112 and other circuitry such as on-wafer address decoder and power control module Cui Zhanding. The state machine 112 provides a wafer level control of the memory operation. The circuit is communicated to the host via the external memory controller. The memory array 200 is typically organized into a two-dimensional array of memory cells, with the =signs being arranged in multiple columns and rows and by word lines and addresses. The array can be formed according to the job type or the _ type architecture. Fig. 2 schematically illustrates that the non-volatility ^ ^ ^ ^ ^ ° has been hidden as early as 70. The memory cell 10 can be implemented by eight crystals such as a net moving gate. The field effect electrode 30 of the unit memory unit 20 is recorded. Uh10 also includes source H, immersion 16 and control closure 130505.doc -13· 200907975 Many commercially successful non-volatile solid state memory devices are being used today. These memory devices can use different types of memory cells, each type having one or more charge storage elements. Typical non-volatile memory cells include EEPROM and flash EEPROM. An example of an EEPROM cell and a method of making the same are given in U.S. Patent No. 5,595,924. Examples of flash EEPROM cells, their use in memory systems, and methods of making them are given in U.S. Patent Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, 5,661,053, 5,313,421. And in No. 6,222,762. In particular, an example of a memory device having a NAND cell structure is described in U.S. Patent Nos. 5,570,315, 5,903,495, 6,046,935. Further, an example of a memory device using a dielectric storage element has been used by Eitan % "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell"> IEEE Electron

Device Letters, Vol. 21, No. 11, 2000, November, pp. 543-5, 5 pages, and U.S. Patent Nos. 5,768,192 and 6, 〇 11,725. In practice, the memory state of the cell is read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of the cell, a corresponding conduction current for the fixed reference control gate voltage can be detected. Similarly, the range of charge that can be ramped to the floating gate defines the corresponding threshold voltage® or corresponding conduction current window. Alternatively, instead of detecting the conduction current in the split current window, at the gate of control 130505.doc •14.200907975, the threshold voltage may be measured for the given memory state (4) and the measured conduction current is lower than or Above the threshold current. In one implementation, #, checking that the conduction current is discharged through the capacitance of the bit line is completed = the lifetime of the threshold current versus the conduction current. Figure 3 illustrates the relationship between the source-drain current 1 〇 and the control gate voltage να for a floating open-pole, optionally, different charge Q1-Q4. The relationship between the four solid lines Id*Vcg indicates the four possible charge levels that can be converted to the floating gate of the memory bank 7L, which correspond to the four possible memory states, respectively. As an example, a threshold voltage window for a certain number of cells can range from 0.5 V to 3·5 ¥. The seven possible memory states t, "Ρ ' " respectively, can be divided into five erased states and six stylized states by dividing the threshold window into five regions at intervals of 0·5 V. 2", "3", "4", "5", "6". For example, if a reference current IREF of 2 μΑ is used as shown, the unit programmed with ... can be regarded as In the memory state "Γ, because its curve intersects Iref in the region of the threshold window by VCG = 0.5 乂 and ^ v. Similarly, Q4 is in the memory state "5". As can be seen from the above description, the more the memory cells are stored, the more finely divided the privacy limits are. For example, the memory device can have a memory cell with a threshold window that varies from -1.5 V to 5 V. This provides a maximum width of 6.5 V. If the memory unit is to be stored in 16 states, each state can occupy 2 paws from the threshold window to 3 〇〇 mV. This will require a higher degree of precision in the stylization and read operations in order to achieve the desired resolution. 130505.doc -15- 200907975 Figure 4 illustrates an example of an array of memory cells. In the memory array 200, the 'per-column memory cell' is connected by a source 14 and a gateless daisy-chain. This design is sometimes referred to as a virtual grounding design... The control gate 3() of the single (4) column is connected to a word line such as word line 42. The source and drain of the cell in the row are connected to selected bit lines such as bit lines 34 and 36, respectively. Figure 5A schematically illustrates a string memory unit organized as a string of wealth. NAND string 50 includes a series of memory transistors M1, M2 ... Mn (e.g., η 4 8 16 or 16). The memory transistors are daisy chained by their source and drain. A pair of select transistors S1, S2 respectively control the connection of the memory transistor chain via the source terminal 54 of the NAND string and the % of the drain terminal to the outside. In the § memory array, when the source selection transistor s ^ is turned on, the source terminal is coupled to the source line (see FIG. 5B) <> similarly, when the drain select transistor S2 is turned on When the 'NAND string is not extremely pure to the bit line of the memory array. Each memory transistor in the chain acts as a memory unit. It has a charge storage element 2 to store a given amount of charge in order to express an undesired state of the memory. The control gate of each memory transistor allows control of read and write operations. As will be seen in Figure 5B, the control gates 3 相应 of the respective memory transistors of the column NAND strings are all connected to the same-word line. Similarly, control gate 32 of each of select transistors S1, 82 provides controlled access to the NAND string via source terminal 54 and gate terminal 56 of the NAND string, respectively. Similarly, the control gates 3 2 of the respective select transistors of a column of NAND strings are connected to the same select line. When the address symmetry in the NAND string is read or verified during the stylization, an appropriate voltage is supplied to its control gate 30. At the same time, the remaining portion of the unresolved 5 mnoreic transistors in the NAND string 5 完全 is fully turned on by applying sufficient voltage to the control gate of the remaining portion of the unaddressed memory transistor in the NAND string 50. . In this way, from the source of the individual memory transistor to the source terminal 54 of the NAND string and likewise from the drain of the individual memory transistor to the terminal of the cell 56, the conduction path is effectively generated. A memory device having the NAND string structure is described in , No. 5, No. 5, No. 5, No. 5, 495, No. 6, No. 46,935. Figure 5B illustrates an example of a NAND array 200 of memory cells composed of NAND strings 5A such as the 2 NAND strings shown in Figure 5A. Along each row of the NAND string, a bit line such as bit line 36 is coupled to the drain terminal 56 of each NAND string. Along each group of NAND strings, a source line such as source line 34 is coupled to source terminal 54 of each NAND string. The control gates of the column § memory cells in a group of NAND strings are also connected to word lines such as word lines 42. The control gates of the selected transistor along a column of one of the NAND strings are coupled to a select line such as select line 44. An entire column of memory cells in the group of NAND strings can be addressed by the word lines of the set of NAND strings and the appropriate voltage on the select lines. When reading one of the memory transistors in the NAND string, the remaining memory cells in the string are hard-on via their associated word lines such that the current flowing through the string is substantially stored in the The level of charge in the cell being read depends on the level of charge. Figure 6 illustrates a prior art technique for staging memory cells to a target memory state. The programmed voltage vPGM is applied to the control gate of the memory cell via the coupled word line. vPGM is the step from the initial voltage level VpGMQ 130505.doc •17· 200907975 The form of the waveform - series of stylized voltage pulses. The stylized unit is subjected to this series of stylized electric house pulses, each of which attempts to add an incremental charge to the floating pole. Between the program sputum pulses, the unit is read back or verified to determine its source _ drain current relative to the breakpoint level. The readback process can involve one or more sensing operations. Stylize for the unit when it is verified that it has reached the target state. The private burst used, which is used, may have an increasing period or amplitude to cancel the accumulated electrons in the charge storage unit that is programmed into the memory unit. A stylized circuit typically applies a series of stylized pulses to a selected word line. In this way, the page of the memory unit that controls the open-to-word line can be programmed. As long as one of the memory cells of the page is programmed to its target state, the cell will be stabilized and the other cells will continue to be stylized until all cells of the page have been programmatically verified. The conventional stylization technique using the -series alternate stylization/verification loop is used to deal with the uncertainty in the stylization process, where the threshold voltage of the unit initially grows rapidly in response to a relatively large change in VPGMi. However, the increase slows down and eventually stops because the charge is reduced to the charge of the floating gate wiper to reduce the effective electric field used to further tunnel electrons into the floating gate. This process appears to be highly non-linear and therefore uses trial and error. The disadvantage of stylized/verified stylization techniques is that it verifies loop time and affects performance. This problem is exacerbated by the implementation of memory cells capable of storing multiple bits. Basically, verification is required for each of a plurality of possible states of the memory unit. For a memory with 16 possible memory states, this means that each verification step will have at least 16 sensing operations. In some other mechanisms, it may even be several more times. Therefore, with the 130505.doc 18 200907975 multi-level memory unit ("MLC") verification/verification mechanism verification, it is more and more time-consuming. The second best = memory device with improved stylized performance, in "predictive stylization technology according to one aspect of the invention, in - non-volatile memory, _ early p歹, BP „ τ ° The invisible body can be programmed to individual

One of J's scopes provides a predetermined function for predicting the application of a stylized coating level to program a given memory single S to a given target threshold voltage. In this way, there is no need to perform verification operations, thereby improving the performance of Dazhongtian's stylized operations. In one embodiment, the predetermined function is approximated by a linear function that proportionally produces a private voltage level for a given target threshold voltage level. The linear function has a slope given by a predetermined average of a fixed number of single Ss for the memory array. The linear function is uniquely determined for the given memory unit by a checkpoint on a predetermined linear function for a given memory unit. The checkpoint is based on the actual stylized voltage that stylizes the memory cells to the specified threshold voltage level. The checkpoint preferably corresponds to one of the lowest stylized states of the memory unit. Memory cells are initially stylized to checkpoints and verified by, for example, conventional stylization/verification stylization techniques. In this way, a checkpoint value is determined for the actual stylized voltage necessary to program the memory unit to the specified memory state. Therefore, the predetermined function is corrected to be used to determine the programmed voltage value for staging the memory unit to the target threshold voltage level to produce a level of accuracy at the checkpoint threshold of 130505.doc -19-200907975 The checkpoint stylized voltage value at the time of evaluation. f In the example, the range of possible thresholds supported by the memory unit may refer to the checkpoint of Jin Xizhen. Each checkpoint will be used to correct

The slice near each checkpoint has an hA pre-function. A local predetermined function is used to measure the stylized voltage level used to program the target threshold voltage level near the associated checkpoint.

Predictive stylization techniques are advantageous because stylized to target states do not require inspection. Only verification operations are required to determine, in general, checkpoints that are much smaller in number than the number of states that can be used. There will be changes to stagger the wait predictions to produce erroneous results, but such errors will be statistically predictable errors that can be handled by appropriate error correction: ('E C C"). Figure 7 illustrates the observations between the samples of the memory cells of a given memory device $ and the known additions of the stylized electrical waste and the threshold dust level. = The stylized behavior of individual memory singles is observed. Even in the marginal arrogance: the range is also surprisingly linear. Individual cells within the array, either multi or v, act in the same manner, with the change in the programmed threshold voltage being substantially proportional to the change in the voltage level.胄Because the individual units are subjected to deep and erased and other ® f, the W units can differ by the number of stylized pulses to reach the specified checkpoint, but each of the individual units has a substantially similar Slope. Figure 7 shows some examples of slow stylized units, fast redformed units, and medium-speed stylized units (solid lines). It can be observed that the change in slope between different instances is small. 130505.doc -20- 200907975 Figure 8 is not intended to illustrate the slope of the sample of the memory cell in the needle media & σ 疋 己 t 八 八 八 八 ^ ^ ^ . . . . . . 分布Basically, it shows an average slope of about 9.9 and a normal distribution of the “quasi-difference of your ^1. The actual stylization uses two different programs*. The voltage step size has been observed. Two steps have been observed. Similar distribution and average slope. Figure 9 illustrates the pre-complex function of the boxed & required to provide the _ _ , , f ° 隐 隐 兀 兀 至 至 至 至 至 目标 目标 目标Preferred embodiment. The predetermined function is approximated by a linear function, and the vertical φ

, in which the threshold VT is given as a function of the stylized voltage VpGM by the following relationship: vt (Vpgm) = <slope> VPGM + VT(0) Equation (1) (where <slope> ;=avtmvpqm) Conversely, equation (2)

Vpgm(Vt) = 1 / &lt;slope &gt;[ντ_ντ(〇)]; In the preferred real_, the average &lt;slope &gt; can be predetermined by testing the work waste samples from similar production lots. For example, the test yields &lt;slope&gt; is 〇.9. VT(〇) depends on the unit and is predetermined by the checkpoint from each memory unit before the prediction of each unit. Once &lt;slope &gt; and VT(0) are known, the predetermined function of the memory cell is defined, and equation (2) can be used to obtain the programmed voltage level required to program to the target threshold voltage level. Figure 10 is a flow chart illustrating predictive gasification in accordance with a general embodiment of the present invention. Step 300: Providing a predetermined function for the memory unit in the stylization' This function generates a stylized voltage value according to the threshold 130505.doc -21 - 200907975 level to which the memory unit is to be programmed. Step 3 I 〇 ······················································· The (4) word line is applied to the _ _ seedling_, a I. Electric biting U body early control gate. Step 320: In the stylized thunder, the pressure level difference has substantially reached the end of the page of the memory list after the value determined by the target threshold element 1 = the fixed function f = usually 'simultaneously When the memory unit in the memory unit discussion transferred to the same word line has received the value determined by the predetermined function evaluated at the threshold voltage level of the target,

The advancement is performed, and (4) at the word line T 廿, the extra stylized pulses for the memory cells of the page are present in the depth. Κ ...like '' does not need to approximate the predetermined function by a linear function. If the pre-function is used to accurately cover and reproduce a wide range of threshold voltage levels, then I can be modeled by testing the production batch at the factory. j疋 and by a suitable function, in general, it is being stylized. The cryptic saponin is one of the memory cells of the one page of the stylized t. The parent elements of the predetermined letter provided for each memory unit of the page share the same word line, ...: all memory sheets on the page - one of the memories of the stylized page of the predicted stylized voltage The body unit is forbidden for further stylization. The prediction 嵩4 described in Fig. 1 (predictive % mode is preferably implemented in the heartbeat of the memory operation of the volume array 200). Road U. The state machine 112 (see Figure 11 illustrates that the weight of the predetermined 疋 function shown in Figure 9 is followed by the stylized voltage when it is applied in the predicted 130505.doc -22-200907975 stylized mode. In the initial phase The memory cell checkpoint (〇) is specified at a threshold voltage level (private checkpoint threshold voltage level) that is slightly considered to be the voltage level associated with the erased state. The incremental stylized voltage pulse stylizes the memory unit towards the checkpoint threshold voltage level. The stylized style can be used for parental stylization and verification until the stylization verifies the checkpoint threshold. Once the coordinate system [VPGM, VT] is detected for the checkpoint (9), u(9), the predetermined function in the form of equation (2) (see Figure 9) can be solved for VT(〇) and is fully specified. After specifying a predetermined function in the form of equation (2), the memory unit can then be programmed in the prediction mode using a predetermined function to provide an estimated programmed voltage level for the target threshold level or for the target memory state. In the preferred embodiment Adjusting the stylized voltage step size so that each extra pulse will stylize the memory cell to the next memory state. For example, in a memory cell with (four) possible memory states, the pulse size can be 'in this way' ' _ extra pulse will program the memory to state (1), another - extra pulse will be stylized memory to state (7), etc. Therefore, stylized to a given memory state can be simplified to self-state (〇) count state The number and supply of the same number of pulses. For example, the flag can be set once in state (9), and thereafter the memory cell can be programmed with the same number of pulses as the number of states of the target state state (〇). Stylized pulse size is possible. For example, for a memory cell with one possible memory state, the pulse size can be &quot;Ο. In that case, 'will take two pulses from the memory state. 130505.doc -23- 200907975 Modification to the next adjacent memory state. This will provide a stylized resolution, which is used in the case of using the target &amp; In the implementation, FIG. 12 schematically illustrates the distribution of various memory states of the memory-pages during the stylization process shown in Fig. u. The pages of the memory cells are; Starting in the erase state, the memory cells can be self-erased by the memory cell unit during the initial programming phase of the second verification cycle (eg, X stylized pulses plus the total number of verification steps). To the state (〇) ° In general, the 'per-memory cell's collision is independent. Once the 2 memory cell is in the state, the predictive stylization mode begins, and each extra pulse will program the memory cell to The following is a memory state. Fig. 13 is a flow chart showing the step-by-day _ _ ^ _ 〇 月 月 〇 包括 包括 包括 包括 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The checkpoint of the specified function is used as the specified checkpoint threshold voltage level that can be learned by the corresponding checkpoint program pad value. Step 304: Determine the stylized electric power value of the corresponding checkpoint by alternately planting the decimal/testing method until the stylization verifies the checkpoint threshold. Step 306: After the predetermined function is used, the predetermined function is corrected before the program is used to program the memory unit to the target threshold voltage level to generate a power limit at the checkpoint. Dust value. Checkpoints at the time of assessment Figure 14 illustrates an example of an example of using a predictive stylization of wall-walled check 2 In the first instance, each record to be stylized by the predictive mode 130505.doc • 24-200907975 Before the hidden form is in the checkpoint in the figure &quot; in step 302 and step; Memory state in 4. Gradually, the memory unit is programmed into a state (〇), a form of separation = mode ^, if it can be, the even state state (〇), shape ~,), cancer (7) ... point. Stylized/verified stylized, etc. From each check, : (see Figure 6), the test is cut from the previous state - the number can be corrected and used to predict (3), state (7).... The embodiment described in the example - the odd state (1), the shape = allows the prediction mode to be "two: show good linearity at such short intervals. =: the enumeration mode is only stylized every other memory free ^ Know at least half of the verification operations in the stylization (see Figure 6). Figure 15 illustrates the sides of the various associated predetermined functions described in Figure 14;:: = : The number near the checkpoint is linear and has the same predetermined flat: : 丰察到^ ^ ^ ^ ίΐ - Τ 々 slope. Checkpoint (0) is used to set the boundary condition of function 400. Similarly, check the boundary condition of local predetermined function 420 - boundary condition of predetermined function 44G Etc. - Point (4) is set by setting the local predetermined function, which can be used to recall the stylized state of the body, and 隹m is used for the next level to produce U. Therefore, the local job function is used. Stylize the unit to a stylized version: =: ° is used to generate the unit for stylization to the state heart \ and a local predetermined function 440 is used to generate the unit I30505.doc -25 - 200907975 Stylized voltage level to state (5), etc. Figure I6 illustrates the use of a A second example of the embodiment of the predictive stylization of the above checkpoints. In contrast to the first example shown in Figures 14 and 5, the first instance has a checkpoint designated by the parent four memory states. The checkpoint (〇) is specified in state (0), state (4), state (8), etc. The local predetermined function set by checkpoint (0) will be used to respectively target the next three memory states (ie , state (1), state (2), and state (3)) predict the stylized voltage. Similarly, the local predetermined function set by checkpoint (4) will be used to target

The next three memory states (ie, state (5), state (6), and state prediction stylized voltage. The predicted stylized voltage generated by the second instance will not be as accurate as the predicted stylized voltage of the first example, However, it can be sufficient in many applications. It has the potential to further reduce the number of stylized verification operations. It is possible to specify other checkpoints within the threshold of the memory unit's threshold f. In contrast to the accuracy, in some stylized algorithms, the pages of the memory unit are programmed to be close to their respective target states in the first pass, stylized through the completion to the respective target state. The program _ people use methods to alleviate (4) memory unit interference. Because A ^ a 】 "between the process ^ because the Zhuo - times through the stylization does not require the second time accuracy, so zinc, over one : The second pass through the throttling threshold stylized mode to perform the .... In some implementations, it is also expected that the second u-L mode will be better used at the appropriate position ^ 130505.doc -26 - 200907975 check Point. The stylized mode does not exclude the very small possibility of exceeding the ^ ^ ^ ^ ^ ^ ^ ^ α plus ι limit voltage level (estimated to be less than 〇1. / ) 勹jm/ο. Exceeding the target memory state In the case, the error can be corrected by the error correction implemented. When two checkpoints are available, it is possible to independently set the slope of the predetermined function. Once the predetermined function is specified, the bean can be used to generate Stylized voltage level for subsequent memory states.

All patents, specifications, other publications, documents, and matters cited herein are incorporated herein by reference. This document is dominant in terms of inconsistencies or inconsistencies between any of them and the text of this document. The application or use of a patent application, article, book, or article for all purposes, all of which is defined in the disclosure, document, or thing, or the use or definition of any term used, although in relation to certain implementations The examples describe various aspects of the invention, but it should be understood that 'the invention is entitled to the complete material protection of the scope of the patents. force

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of functional blocks of a non-volatile memory chip that can be implemented in accordance with the present invention. Figure 2 schematically illustrates a non-volatile memory unit. Figure 3 illustrates the relationship between the source-drain current Id and the control gate voltage Vcg for four different charges Q1_Q4 that are selectively stored by the floating gate at any one time. Figure 4 illustrates an example of an array of memory cells; 130505.doc -27- 200907975 FIG. 5A schematically illustrates one-string memory unit 0 organized as a NAND string. FIG. 5B illustrates a memory unit composed of a NAND string 5〇 such as the NAND string shown in FIG. 5A. An example of a NAND array 200. Figure 6 illustrates a conventional technique for staging a § memory unit to a target memory bear. Figure 7 illustrates the stylization of individual memory cells in a given memory device

The observed relationship between the sample and the applied stylized voltage and the threshold voltage level. Figure 8 is a schematic illustration of the distribution of the slopes shown in Figure 7 for a sample of memory cells in a given memory device. Figure 9 illustrates (4) a preferred embodiment of a predetermined function for providing a stylized voltage required to program a memory cell to a target threshold voltage level. Figure 10 is a flow chart illustrating predictive programming performed in accordance with a general embodiment of the present invention. Figure 11 illustrates the correction of the shape function as shown in Figure 9 followed by its stylized voltage when applied in predictive stylized mode. Fig. 12 is a view schematically showing the distribution of various memory states of one page of a memory cell during the stylization process of the figure dd _ 圚. Fig. 13 is a flow chart showing the step 疋 γ 〇〇 3 〇〇 5 shown in Fig. 1 为 as including a predetermined function for correcting the memory unit using the checkpoint. Figure 14 illustrates a first example of an embodiment that uses more than one check to predict privateization. Referring to the vicinity of the calibration checkpoint, Fig. 15 illustrates the manner in which the checkpoints illustrated in Fig. 14 are associated with various associated predetermined functions of 130505.doc -28-200907975. Figure 16 illustrates a second example of an embodiment of predictive stylization using more than one checkpoint. [Main component symbol description] 10 Memory unit 14 Source 16 Deuterium 20 Charge storage unit 30 Control gate 32 Control gate 34 Bit line/source line 36 Bit line 42 Word line 44 Select line 50 NAND string 54 Source terminal 56 汲 terminal 100 memory chip 110 control circuit 112 state machine 200 NAND array 歹 230A column decoder 230B column decoder 231 data I / O bus 130505.doc - 29 - 200907975 250A block multiplexer /Page multiplexer 250B Block multiplexer / page multiplexer 260A Row decoder 260B Row decoder 270A Read write circuit 270B Read write circuit 400 Local predetermined function 420 Local predetermined function 440 Local predetermined function Id source Pole-drain current Iref Reference current Ml, M2&quot;. Μη Memory transistor Q1-Q4 Charge SI Source select transistor S2 Dip select transistor VcG Control gate voltage VpGM Stylized voltage VpgMO Initial voltage level VT target The threshold level 130505.doc -30-

Claims (1)

200907975 X. Patent application scope: I. A non-volatile memory of a non-volatile memory that is programmed into a target threshold voltage level in a non-volatile memory. An array of armored cells that can be individually programmed to a threshold voltage level - one of the dry circumferences, the method comprising: providing a memory for one of the stylized deuterations The unit-predetermined function, the 3H function generates a stylized voltage value according to a threshold of a memory that is programmed to the threshold voltage level; the voltage is programmed to achieve the memory unit After the target threshold voltage is set to a value, the memory is stopped to be programmed to the target threshold voltage level with an increasing amplitude; the predetermined function is determined by the predetermined voltage in the programmed voltage. Stylized. 2 · The method of claim 1, is a series of voltage pulses. 3 · As requested in item 1, the number. Wherein the stylized voltage having an increasing amplitude, wherein the predetermined function is substantially a linear function (such as the method, wherein the providing _ function includes: p-fix/function &lt; checkpoint as a usable - corresponding checkpoint stylized voltage value Stylized a specified checkpoint threshold voltage level; the programmed checkpoint voltage value is determined by \#stylization and verification until the checkpoint verifies the checkpoint threshold voltage level; and in the preview The function is used to determine the number of the stylized (four) values used to program the memory unit to the 'gDn limit voltage level' before the correction of the pre-130505.doc 200907975 number is generated at the checkpoint threshold voltage checkpoint Stylized voltage value. The method of determining the liquid at the time of soap evaluation, wherein the target threshold voltage is the predetermined voltage of the checkpoint, and the predetermined voltage is obtained from the method of 6. 'Where in the limit: or multiple checkpoints, the threshold voltage level. 彳之钱围中指7. As in the method of the monthly claim 4, where the estimated slope and - checkpoint are defined. The number is linear, and by The method of f 1=:4, wherein the predetermined function is substantially linear, and is defined by two checkpoints. The method of item 1, wherein the non-volatile memory has individual: more than one bit The memory unit of the data. The method of item 1 wherein the non-volatile memory has a memory unit that individually stores the data as an amount programmed into a charge storage element. U. The method of claim 1 The floating gate of the body. 12. The dielectric layer of the method body of claim 1. 13. The method of claim 1, wherein the non-volatile memory has a memory cell containing a NAND structure. The method of claimant, wherein the non-volatile memory is a flash EEPR 〇m 〇1 5. The method of claim i, wherein the non-volatile memory is implemented in a record in which the charge storage element is a field effect The electric crystal is in which the charge storage element is in the field of a photoelectric crystal 130505.doc 200907975. 6. The method of the invention, wherein the non-volatile memory is embedded in a nasal device. Items 1 to 16 The method of claim 1, wherein the memory unit is one of a group of memory units that are stylized. 18. a non-volatile memory comprising: an array of alpha-clone single 7C, wherein The memory cells can be individually programmed to one of a range of threshold voltage levels; a write circuit for reading and programming one page of memory cells; L, slave, It is used to control the operation of the non-volatile memory including the read write circuits, the state machine: providing a predetermined function for one of the memory cells in the stylization, the function is based on a 5 memory unit Stylized to a threshold voltage level to generate a programmed voltage value; control to program the memory unit to a target threshold voltage level with a stylized voltage having an increasing amplitude; and at the stylized voltage substantially The stylization of the memory unit is stopped after the value determined by the function is evaluated at the target threshold voltage level. 19. The non-volatile memory of claim 18, wherein the stylized voltage having an increasing amplitude is a series of voltage pulses. 20. The non-volatile memory of claim 18 wherein the predetermined function is substantially a linear function. 130505.doc 200907975 η · The non-volatile memory of claim 18, wherein the "fourth" function providing the "(four) function further comprises: specifying one of the functions to detect a point as a program can be stylized by a corresponding checkpoint The voltage value is programmed to a predetermined checkpoint threshold voltage level; the programmed value of the corresponding checkpoint is determined by alternately stylizing and verifying until the checkpoint verifies the checkpoint threshold level; and The predetermined function is used to determine that the memory unit is programmed to correct the pre-twist function before the stylized electric dust value is generated. The checkpoint stylized voltage value at the time of the assessment. 22. The non-volatile memory of claim 21, wherein the target threshold voltage level is less than a predetermined voltage from the checkpoint threshold voltage level. 23. In the non-volatile memory of claim 21, one or more checkpoint threshold voltage levels are specified in the range of threshold voltage levels. 24. The non-volatile memory of claim 21, wherein the predetermined function is linear and is defined by an estimated slope and a checkpoint. 25. The non-volatile memory of claim 21 wherein the predetermined function is substantially linear and is defined by at least two checkpoints. 26. The non-volatile memory of claim 18, wherein the non-volatile memory has a memory unit that individually stores data for more than one bit. ~ 27. The non-volatile memory of claim 18 wherein the non-volatile memory has a memory unit that individually stores the data as a charge amount programmed into the charge storage element. 28. The non-volatile memory of claim 18, wherein the charge storage element is 130505.doc 200907975 one floating gate of one effect transistor. 29. The non-volatile memory of claim 18, wherein the % is a dielectric layer of a potential transistor. 30. The non-volatile memory of claim 18, wherein the non-volatile memory has a memory cell comprising a NAND structure. 3 1. If the non-volatile 兮ρ彳 sound body of § Qing seeking item 18, beans φ兮t + goods Wang. It has a non-volatile memory for a fast EEPROM. r 32. The non-volatile memory of claim 18, wherein the non-volatile memory is implemented in a memory card. &quot; 33. The non-volatile memory of claim 18, wherein the non-volatile memory is embedded in a computing device. 34. The non-volatile memory of any one of claims 18 to 33, wherein the memory unit is one of a group of memory units that are programmed together. A non-volatile memory comprising: a display of a memory cell, wherein the memory cell can be individually programmed to one of a range of threshold voltage levels, for providing For a component of a predetermined function in the stylized memory unit, the function generates a stylized voltage value according to the memory unit to be programmed to a threshold voltage level; „for control with an increasing amplitude The stylized power repeatedly rides the memory to the target threshold voltage level component; and is used in the stylized voltage caution ^ &amp; ^ . qualitatively reached by the target _ After the value of one of the Hungarians, the stylized component of the U-body is stopped. I30505.doc 200907975 36. The non-volatile memory of claim 35, further comprising: for specifying the function a checkpoint as a component of a specified checkpoint threshold voltage level that can be programmed by a corresponding checkpoint stylized voltage value; used for stylization and verification by the parent until the stylization verifies the checkpoint a component for determining a programmed check voltage value of the corresponding checkpoint; and a programmed voltage value for determining that the predetermined function is used to program the memory cell to the target threshold voltage level The predetermined function is previously corrected to produce a component of the checkpoint stylized voltage value when the checkpoint threshold voltage level is evaluated. 3 7. Non-volatile memory as claimed in claim 34 or 35, wherein The memory _ &quot;Τ' 7Q is one of a group of memory units that are programmed together. 130505.doc