CN101711414B - Non-volatile memory and method for predictive programming - Google Patents

Non-volatile memory and method for predictive programming Download PDF

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CN101711414B
CN101711414B CN 200880019574 CN200880019574A CN101711414B CN 101711414 B CN101711414 B CN 101711414B CN 200880019574 CN200880019574 CN 200880019574 CN 200880019574 A CN200880019574 A CN 200880019574A CN 101711414 B CN101711414 B CN 101711414B
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memory
programming
voltage level
threshold voltage
checkpoint
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CN101711414A (en
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劳尔-阿德里安·塞尔尼亚
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桑迪士克科技股份有限公司
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Priority to US11/733,706 priority patent/US7551483B2/en
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Priority to PCT/US2008/059740 priority patent/WO2008124760A2/en
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562Multilevel memory programming aspects
    • G11C2211/5621Multilevel programming verification

Abstract

在具有存储器单元的阵列的非易失性存储器中,其中这些存储器单元各自可编程到阈值电压电平的范围之一,提供了一种预测编程模式,其中预定函数预测需要施加什么编程电压电平以便将给定的存储器单元编程到给定的目标阈值电压电平。 In the non-volatile memory array having memory cells, wherein the memory cells are each programmable to one of a range of values ​​of the threshold voltage level, programming is provided a prediction mode, wherein the predetermined function predict what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. 以此方式,不需要进行验证操作,由此极大地改善了编程操作的性能。 In this way, no verify operation is performed, thereby greatly improving the performance of the programming operation. 在优选实施例中,该预定函数是线性的,并且通过一个或多个检查点对于处在编程下的每个存储器单元校准该预定函数。 In a preferred embodiment, the predetermined function is linear, and by one or more checkpoint function for each of the predetermined memory cell being programmed in the calibration. 该检查点是将讨论的存储器单元编程到被验证的指定阈值电压电平的实际编程电压。 The checkpoint memory cell is programmed will be discussed to a specified threshold voltage level is verified in the actual programming voltage.

Description

非易失性存储器和用于预测编程的方法 The nonvolatile memory and method for predicting programming

技术领域 FIELD

[0001] 本发明一般涉及诸如电可擦除可编程只读存储器(EEPROM)和快闪EEPROM之类的非易失性半导体存储器,特别涉及其中最小化编程验证操作的次数的存储器和编程操作。 [0001] The present invention relates generally such as electrically erasable programmable read only memory (EEPROM) and flash EEPROM non-volatile semiconductor memory or the like, and more particularly to a memory in which the number of programming operations to minimize program verify operation.

背景技术 Background technique

[0002] 能够非易失地存储电荷的、特别是以被封装为小形状因素卡(form factorcard)的EEPROM和快闪EEPROM形式的固态存储器近来已经变成各种移动和手持设备、新颖的信息装置和消费者电子产品中选择的存储器。 [0002] capable of storing charge in a nonvolatile manner, in particular in packaged as a small form factor card (form factorcard) in the form of EEPROM and flash EEPROM solid-state memory has become recently a variety of mobile and handheld devices, the novel apparatus information and consumer electronics products in the selected memory. 不像也是固态存储器的RAM(随机存取存储器)那样,闪存(flash memory)是非易失性的,并且即使在断电后也保存其存储的数据。 Unlike the solid-state memory is a RAM (Random Access Memory) as a flash memory (flash memory) are nonvolatile, and also save its stored data even after power-off. 尽管成本更高,但是闪存被越来越多地用于海量存储应用中。 Despite the higher cost, flash memory is increasingly being used in mass storage applications. 基于诸如硬盘驱动器和软盘之类的旋转磁介质的传统海量存储器不适合于移动和手持环境。 Based on conventional rotating magnetic media mass storage such as hard drives and floppy disk is unsuitable for the mobile and handheld environment. 这是因为趋于大容量的硬盘驱动器易出现机械故障,并具有高等待时间和高功率需求。 This is because tends to large-capacity hard drives are prone to mechanical failure and have high latency and high power requirements. 这些所不期望的属性使得基于盘的存储器在大多数移动和便携应用中不实用。 These undesirable attributes make disk-based storage impractical in most mobile and portable applications. 另一方面,嵌入式且以可移除卡的形式的闪存由于其小尺寸、低功耗、高速度和高可靠性的特征,在理想地适合于移动和手持环境。 On the other hand, and embedded in the form of a removable flash memory card because of its small size, low power consumption, high speed and high reliability features, ideally suited in the mobile and handheld environment.

[0003] EEPROM和电可编程只读存储器(EPROM)是可以被擦除的并将新的数据写到或“编程”到其存储器单元中的非易失性存储器。 [0003] EEPROM and electrically programmable read-only memory (EPROM) can be erased and new data written or "programmed" into their memory cells in a nonvolatile memory. 两者都利用在源极区和漏极区之间的、位于半导体衬底的沟道区上方的场效应晶体管结构的浮置(未连接的)导电栅极。 Both utilize between the source region and the drain region, a floating field effect transistor structure above the channel region of the semiconductor substrate, a conductive gate (unconnected). 然后在该浮置栅极上方提供控制栅极。 A control gate is then provided over the floating gate. 通过在浮置栅极上保持的电荷量来控制晶体管的阈值电压特性。 To control the threshold voltage characteristic of the transistor is held by the amount of charge on the floating gate. 即,对于浮置栅极上的给定水平的电荷,存在在晶体管被导通以允许在其源极区和漏极区之间的导电之前必需施加到控制栅极的相应电压(阈值)。 That is, for a given level of charge on the floating gate, there is a transistor is turned on to permit conduction between before its source and drain regions must be applied to the corresponding voltage (threshold) control gate.

[0004] 浮置栅极可以保持一定范围的电荷,因此可以被编程为在阈值电压窗口内的任意阈值电压电平。 [0004] The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. 阈值电压窗口的大小由器件的最小和最大阈值电平界定,该器件的最小和最大阈值电平又对应于可以被编程到浮置栅极上的电荷的范围。 Threshold voltage window size by the minimum and maximum threshold levels define the device, the device minimum and maximum threshold levels may be programmed and corresponding to the charge on the floating gate range. 阈值窗口一般取决于存储器器件的特性、操作条件和历史。 The threshold window generally depends on the memory device's characteristics, operating conditions and history. 窗口内的每个不同的、可分辨的(resolvable)阈值电压电平范围原则上可以用于指定该单元的明确存储器状态。 Each different, the (resolvable) principle threshold voltage level range of values ​​can be distinguished clearly unit used for specifying the memory state in the window. 当该阈值电压被划分成两个不同的区域时,每个存储器单元将能够存储一位数据。 When the threshold voltage is partitioned into two distinct regions, each memory cell will be able to store one bit of data. 类似地,当阈值电压窗口被划分成多于两个不同的区域时,每个存储器单元将能够存储多于一位的数据。 Similarly, when the threshold voltage window is partitioned into more than two distinct regions, each memory cell will be able to store more than one bit of data.

[0005] 在通常的两状态EEPROM单元中,建立至少一个电流断点(breakpoint)水平以便将导电窗口分成两个区域。 [0005] In the usual two-state EEPROM cell, at least one current breakpoint (Breakpoint) to horizontal conductive window into two regions. 当通过施加预定的固定电压来读取单元时,通过与断点水平(或参考电流IREF)比较,其源极/漏极电流被分辨为存储器状态。 When a cell is read by applying a predetermined fixed voltage, by the breakpoint level (or reference current IREF) compared to the source / drain current is resolved into a memory state. 如果读取的电流高于断点水平的电流,则确定该单元处于一个逻辑状态(例如“O”状态)。 If the current read is higher than the breakpoint level, the cell is determined to be in one logical state (e.g. "O" state). 另一方面,如果该电流小于断点水平的电流,则确定该单元处于另一逻辑状态(例如“I”状态)。 On the other hand, if the current is smaller than the current breakpoint level, the cell is determined in the other logical state (e.g. "I" state). 因此,这种两状态单元存储一位的数字信息。 Thus, such a two-state cell stores one bit of digital information. 通常提供可外部编程的参考电流源作为用于产生断点水平电流的存储器系统的部分。 Typically programmed to provide an external reference current source for generating a part of a memory system of the breakpoint level current.

[0006]为了增加存储器容量,随着半导体技术的状态的发展,密度越来越高地制造快闪EEPROM器件。 [0006] In order to increase memory capacity, with the development of the state of the semiconductor technology, the density of flash EEPROM devices manufactured crescendo. 用于增加存储器容量的另一方法是使每个存储器单元存储多于两个状态。 Another method for increasing storage capacity is to have each memory cell store more than two states. [0007] 对于多状态或多电平EEPROM存储器单元,通过多于一个断点将导电窗口划分成多于两个区域,使得每个单元能够存储多于一位的数据。 [0007] For a multi-state or multi-level EEPROM memory cell, by more than one breakpoint window is divided into more than two conductive regions, such that each cell can store more than one bit of data. 因此给定的EEPROM阵列可以存储的信息随着每个单元可以存储的状态的数量增加。 Thus the information that a given EEPROM array can store is increasing as the number of each cell can store a state. 在美国专利N0.5172338中描述了具有多状态或多电平存储器单元的EEPROM或快闪EEPROM。 In U.S. Patent No. N0.5172338 described EEPROM or flash EEPROM with multi-state or multi-level memory cell.

[0008] 通过两种机制之一典型地将用作存储器单元的晶体管编程为“被编程的”状态。 Programming transistor [0008] A memory cell used by one of two mechanisms typically a "programmed" state. 在“热电子注入”中,施加到漏极的高电压加速电子穿过衬底沟道区。 In "hot electron injection," a high voltage applied to the drain accelerated electrons across the substrate channel region. 同时,施加到控制栅极的高电压拉动热电子经过薄栅极电介质到达浮置栅极。 While applying a high voltage to the control gate pulls the hot electrons through a thin gate dielectric reach the floating gate. 在“隧道效应注入(tunnelinginjection)”中,高电压被施加到相对于该衬底的控制栅极。 In "tunneling injection (tunnelinginjection)", the high voltage is applied to the control gate relative to the substrate. 以此方式,将电子从衬底拉到居间的浮置栅极。 In this way, electrons are pulled from the floating gate intervening substrate.

[0009] 可以通过许多机制擦除该存储器器件。 [0009] The memory device may be erased by a number of mechanisms. 对于EPR0M,通过紫外照射从浮置栅极移除电荷可体(bulk)擦除该存储器。 For EPR0M, removed from the floating gate by ultraviolet irradiation can charge member (Bulk) erases the memory. 对于EEPR0M,通过相对于控制栅极将高电压施加到衬底以便诱导浮置栅极中的电子隧道穿过薄氧化物到衬底沟道区(即Fowler-Nordheim隧道效应),存储器单元是电可擦除的。 For EEPR0M, by applying the high voltage to the substrate relative to the control gate so as to induce electrons in the floating gate tunneling through a thin oxide to the substrate channel region (i.e., Fowler-Nordheim tunneling), the memory cells are electrically erasable. 典型地,可以逐字节擦除EEPROM。 Typically, it is erased byte by byte EEPROM. 对于快闪EEPR0M,可以一次全部或一次一个或多个块地电擦除该存储器,其中块可以由存储器的512字节或更多构成。 For flash EEPR0M, all at once or one at a time or more electrically erased memory blocks, where a block may be composed of more or 512 bytes of memory.

[0010] 存储器器件典型地包括可以安装在卡上的一个或多个存储器芯片。 [0010] The memory devices typically comprise one or more memory chips may be mounted on the card. 每个存储器芯片包括由诸如解码器和擦除、写入和读取电路之类的外围电路支持的存储器单元的阵列。 Each memory chip comprises an array such as decoders and erase, write and read circuits supported by peripheral circuits such memory cells. 更复杂的存储器器件利用执行智能的更高级别的存储器操作和接口对接(interfacing)的外部存储器控制器来操作。 Memory operation and a more complex interface, docking memory devices with a higher level of intelligence performed (Interfacing) is an external memory controller to operate.

[0011] 存在许多如今正在使用的商业上成功的非易失性固态存储器器件。 [0011] There are many successful non-volatile solid-state memory devices being used commercially today. 这些存储器器件可以是快闪EEPROM或者可以采用其他类型的非易失性存储器单元。 These memory devices may be flash EEPROM or may employ other types of nonvolatile memory cells. 在美国专利N0.5070032、5095344、5315541、5343063 和5661053,5313421 和6222762 中给出了闪存和制造闪存的系统和方法的例子。 Examples of flash memory and an example of manufacturing a flash memory in the system and method of U.S. Patent 5661053,5313421 and 6222762 and in N0.5070032,5095344,5315541,5343063. 具体地,在美国专利N0.5570315,5903495,6046935中描述了具有NAND串结构的闪存器件。 In particular, it described in U.S. Patent No. N0.5570315,5903495,6046935 flash memory devices with NAND string structures. 而且还从具有用于存储电荷的介电层的存储器单元制造非易失性存储器器件。 But are also manufactured from memory nonvolatile memory device having a dielectric layer for storing charge. 代替之前描述的导电浮置栅极元件,使用介电层(dielectric)。 Instead of the previously described conductive floating gate elements, a dielectric layer (dielectric). 利用电介质存储元件的这种存储器器件已经由Eitan等人在IEEE ElectronDevice Letters,第21 卷,2000 年11 月第11 号,543-545 页“NR0M:A NovelLocalized Trapping, 2-BitNonvolatile Memory Cell”中描述。 Utilizing dielectric storage element have such a memory device in IEEE ElectronDevice Letters, Vol. 21, November 2000, No. 11, pp. 543-545 described by Eitan et al: the "NR0M A NovelLocalized Trapping, 2-BitNonvolatile Memory Cell" Description . ONO介电层延伸穿过源极和漏极扩散区(diffusion)之间的沟道。 An ONO dielectric layer extends across the channel between source and drain diffusion regions (diffusion). 用于一个数据位的电荷位于与漏极相邻的介电层中,并且用于另一数据位的电荷位于与源极相邻的介电层中。 Charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is positioned adjacent to the source of the dielectric layer. 例如,美国专利N0.5768192和6011725公开了具有夹在两个二氧化娃层之间的俘获(trapping)电介质的非易失性存储器单元。 For example, U.S. Patent No. 6,011,725 ​​discloses N0.5768192 and a nonvolatile memory cell having a trapping (trapping The) dielectric is sandwiched between two oxide layers of the baby. 通过分别读取在电介质内的空间分离的电荷存储区的二进制状态来实现多状态数据存储。 Multi-state data storage is implemented by separately reading the binary states in the dielectric space separated charge storage regions.

[0012] 为了改善读取和编程性能,并行读取或编程在阵列中的多个电荷存储元件或存储器晶体管。 [0012] In order to improve read and program performance, read or programmed in parallel a plurality of charge storage elements or memory transistors in an array. 因此一起读取或编程一“页”存储器元件。 Thus read or programmed a "page" of memory elements together. 在现有的存储器结构中,一行典型地包含几个交织(interleaved)的页或它可以构成一页。 In existing memory architectures, a row typically contains several interleaved (Interleaved) pages or it may constitute one page. 将一起读取或编程一页的所有存储器元件。 All memory elements of a read or programmed together.

[0013] 使用一系列交替编程/验证循环的传统编程技术用于应对编程处理中的不确定性,在该编程处理中,响应于Vrai中相对较大的变化,该单元的阈值电压最初迅速增长。 [0013] using a series of alternating program / verify cycle of conventional programming techniques to cope with uncertainty in the programming process, the programming process in response to Vrai relatively large variation, the threshold voltage of the cell is initially rapid growth . 然而,随着被编程到浮置栅极中的电荷起屏蔽作用,减小了用于进一步将电子隧道进入浮置栅极的有效电场,该增长放慢并最终停止。 However, as programmed into the floating gate act as a shield in the charge, reducing the effective electric field for further tunneling electrons into the floating gate, the slower growth and eventually stops. 该过程看起来是高度非线性的,因此采用了反复试验(trial-and-error)方式。 The process appears highly non-linear, and therefore used the trial (trial-and-error) mode.

[0014] 该编程/验证编程技术的缺点是,验证循环花费时间并影响性能。 [0014] The disadvantage of the program / verify programming technique is that the verify cycle takes up time and impacts performance. 通过实现能够存储多个位的存储器单元,加剧了该问题。 By implementing a memory cell capable of storing a plurality of bits, exacerbated the problem. 本质上,需要对存储器单元的多个可能状态的每个执行验证。 Essentially, a plurality of memory cells may be performed for each validation status. 对于具有16个可能的存储器状态的存储器,这意味着每个验证步骤将引起至少16个感测操作。 For a memory with 16 possible memory states, this means each verify step would cause at least 16 sensing operations. 在一些其他方案中,甚至是几倍更多。 In some other scenarios, even several times more. 因此,随着多电平存储器单元(“MLC”)中的可区分的状态电平的数量增加,编程/验证方案的验证循环变得越来越耗时。 Therefore, as the number of multi-level memory cell ( "MLC") are distinguishable state level, the verify cycle program / verify scheme becomes increasingly time-consuming.

[0015]由 Loc Tu 等人在2006 年9 月12 日提交的题为“Method for Non-voIati IeMemorywith Linear Estimation of Initial Programming Voltage” 的美国专利申请序列号11/531227公开了通过线性估计来估计初始编程电压的方法。 [0015] entitled by the Loc Tu et al., Filed in 2006, September 12 "Method for Non-voIati IeMemorywith Linear Estimation of Initial Programming Voltage" US Patent Application Serial No. 11/531227 discloses the initial estimate by linear estimation the method of programming voltage. 为了实现对于非易失性存储器的良好编程性能,必须在出厂时最优地选择初始编程电压Vraro和步长(step)大小。 In order to achieve good programming performance for a non-volatile memory, must be optimally selecting the initial programming voltage Vraro and step (step) the size of the factory. 这通过测试每页存储器单元实现。 This is accomplished by testing each page of memory cells. 通过具有在脉冲之间的验证的阶梯波形的一系列电压脉冲来对耦接到所选页的字线连续编程,直到验证该页为指定的样式(pattern)。 It is programmed to the word line selected page of the continuous coupling by a series of voltage pulses having a staircase waveform verification between the pulses until the page is verified to a designated pattern (pattern). 在该页被编程验证时的编程电压将用于通过线性缩放(scaling)回到对于该页的开始编程电压的初始值来估计。 In the programming voltage at the time the page is programmed verified it will be used by linear scaling (Scaling) back to the initial value of the programming voltage to estimate the page. 通过在第二遍(pass)时使用来自第一遍的估计,进一步精确估计。 Using the estimated from the first pass through the second pass (pass), more accurate estimate. 因此,传统的交替编程和验证用于建立用于成功编程一页的最终编程电压。 Thus, conventional alternating programming and verifying for establishing the final programming voltage for successfully programming a page. 然后,将最终编程电压线性地缩放回到对于该页的估计的初始编程电压。 Then the final programming voltage is linearly scaled back to the initial programming voltage for the estimation of the page. 这种类型的缩放是在页级上的粗略尺度上,并且没有解决传统的基于逐单元编程和验证在该场中的存储器的缺点。 This type of scaling is on a coarser scale level on the page, and not resolved based on the drawback of conventional programming and verifying the memory cell by cell in the field of.

[0016] 因此,存在对于高容量和高性能非易失性存储器的普遍需要。 [0016] Accordingly, there is a general need for high capacity and high performance non-volatile memory. 具体地,存在对于最小化了前述缺点的具有改善的编程性能的高容量非易失性存储器的普遍需要。 In particular, there is a general need to minimize the aforementioned disadvantages of the high capacity nonvolatile memory with improved programming performance is.

发明内容 SUMMARY

[0017] 根据本发明的一个一般方面,在具有存储器单元的阵列的非易失性存储器中,其中可将存储器单元分别编程到阈值电压电平的范围之一,提供了预测需要施加多大的编程电压电平以便将给定的存储器单元编程到给定的目标阈值电压电平的预定函数(function)。 [0017] According to a general aspect of the present invention, in a nonvolatile memory array having memory cells, wherein each memory cell can be programmed to one of the range of the threshold voltage level is provided to be applied predict how much programming the voltage level for a given memory cell is programmed to a given target threshold voltage level of a predetermined function (function). 以此方式,不需要执行验证操作,由此极大地改善了编程操作的性能。 In this way, no verify operation is performed, thereby greatly improving the performance of the programming operation.

[0018] 在一个实施例中,通过对于给定的目标阈值电压电平成比例地产生编程电压电平的线性函数来近似该预定函数。 [0018] In one embodiment, the for a given target threshold voltage level of the programming voltage is generated in proportion to the level of the predetermined linear function approximated function. 该线性函数具有由可施加到存储器阵列的全体单元(population of cells)的预定平均值所给定的斜率。 The linear function having the all-cell (population of cells) is applied to the memory array by a predetermined average value given slope. 通过对于给定的存储器单元预定在线性函数上的检查点(checkpoint),来对于给定的存储器单元唯一地确定该线性函数。 By checking for a predetermined point (the checkpoint) on a linear function of a given memory cell to a given memory cell of the linear function is uniquely determined. 该检查点是基于将存储器单元编程到指定的阈值电压电平的实际编程电压。 The checkpoint is based on the actual programmed threshold voltage level programming memory cells to the specified. 优选地,该检查点对应于存储器单元的最低编程状态之一。 Preferably, the inspection point corresponds to one memory cell of the lowest programmed state. 通过例如传统的编程/验证编程技术来将存储器单元初始地编程到该检查点并进行验证。 For example, by a conventional program / verify programming technique initially programmed memory cells to the check point and verify it. 以此方式,确定将存储器单元编程到指定的存储器状态所需的实际编程电压的检查点值。 In this manner, the determined value of the actual checkpoint programming voltage of the memory cell is programmed to the desired memory state designated. 因此在预定函数被用于确定用于将存储器单元编程到目标阈值电压电平的编程电压值之前,当在检查点阈值电压电平处被估计时,该预定函数被校准以产生检查点编程电压值。 Thus before being used to determine a memory cell is programmed to programming voltage value of the target threshold voltage level, when estimated at the checkpoint threshold voltage level, the predetermined function is calibrated in a predetermined function to generate the checkpoint programming voltage value.

[0019] 在另一实施例中,可以在存储器单元所支持的可能的阈值电压电平的范围内指定多个检查点。 [0019] In another embodiment, a plurality of check points can be specified in the range of possible threshold voltage level of the memory cell supported. 每个检查点将被用于校准在每个检查点附近的局部预定函数。 Each inspection point is used to calibrate the predetermined function in the vicinity of each of the partial checkpoint. 该局部预定函数被用于预测用于编程到在相关的检查点附近的目标阈值电压电平的编程电压电平。 The predetermined function is used to predict the local program for programming voltage level to the target threshold voltage level in the vicinity of the relevant checkpoint. [0020] 预测编程技术的优点在于,编程到目标状态不需要验证操作。 [0020] Prediction advantage is that the programming, the programmed target state does not require verify operations. 仅需要验证操作用于确定检查点,这在数量上通常比可能的存储器状态的数量少得多。 Need only verify operation to determine the checkpoint, which is usually much less in number than the number of possible memory states.

[0021] 将存在致使预测编程产生错误结果的偏差,不过这些将是在统计上可预测的误差,其可通过适当的误差校正码(“ECC”)来处理。 [0021] The present prediction cause erroneous results programming bias, but these will be statistically predictable error that can be handled by appropriate error correction code ( "ECC").

[0022] 从以下本发明的优选实施例的描述中,将理解本发明的另外的特征和优点,其中该描述应该与附图相结合。 [0022] from the preferred embodiments described in the following embodiments of the present invention will be appreciated that additional features and advantages of the present invention, which should be described in conjunction with the accompanying drawings.

附图说明 BRIEF DESCRIPTION

[0023] 图1示意性地图示了可以实现本发明的非易失性存储器芯片的功能块。 [0023] FIG. 1 schematically illustrates the present invention may be implemented in a non-volatile memory chip functional blocks.

[0024] 图2示意性地图示了非易失性存储器单元。 [0024] FIG. 2 schematically illustrates a non-volatile memory cells.

[0025] 图3图示了对于浮置栅极可以在任意一个时刻选择性地存储的四个不同的电荷Q1-Q4的、在源极-漏极电流Id和控制栅极电压Va之间的关系。 [0025] FIG. 3 illustrates four different charges to the floating gate may be selectively storing at any one time of Q1-Q4, the source - drain current Id and the control gate voltage Va relationship.

[0026] 图4图示了存储器单元的NOR阵列的例子。 [0026] FIG 4 illustrates an example of an NOR array of memory cells.

[0027] 图5A示意性地图示了被组织成NAND串的存储器单元的串。 [0027] FIG 5A schematically illustrates the memory cells organized into a NAND string string.

[0028] 图5B图示了由诸如图5A所示的串之类的NAND串50构成的存储器单元的NAND阵列200的例子。 [0028] FIG. 5B illustrates an example of an NAND array of memory cells of the NAND strings is shown in FIG. 50 or the like configuration 200 of Fig. 5A.

[0029] 图6图示了用于将存储器单元编程到目标存储器状态的传统技术。 [0029] FIG. 6 illustrates a conventional technique for programming memory cells to a target memory state.

[0030] 图7图示了对在给定的存储器器件中的各个存储器单元进行编程的实例(sample)和在被施加的编程电压和阈值电压电平之间的观测到的关系。 [0030] FIG. 7 illustrates an example (sample) of each of the memory cells in a given memory device and programming observed between programming voltage and the threshold voltage level is applied to the relationship.

[0031] 图8示意性地图示了对于在给定的存储器器件中的存储器单元的实例的如图7所示的斜率的分布。 [0031] FIG 8 schematically illustrates the distribution of the slope of the example shown in FIG memory cells in a given memory device 7.

[0032] 图9图示了用于提供将存储器单元编程到目标阈值电压电平所需的编程电压的预定函数的优选实施例。 [0032] FIG 9 illustrates a preferred embodiment for providing a predetermined function of the memory cell programmed to a target threshold voltage level required programming voltage.

[0033] 图10是图示了根据本发明的一般实施例的预测编程的流程图。 [0033] FIG. 10 is a flowchart illustrating a general embodiment of the prediction program of the present invention.

[0034] 图11图示了在校准图9所示的预定函数之后在预测编程模式中应用该预定函数的情况下的时序上的编程电压。 [0034] FIG. 11 illustrates the program voltage application timing in the case where a predetermined prediction function in the programming mode after a predetermined calibration function shown in FIG 9.

[0035] 图12示意性地图示了在图11所示的编程处理期间一页存储器单元的各个存储器状态的分布。 [0035] FIG. 12 schematically illustrates the distribution of the individual memory states of a memory cell during the programming process shown in FIG. 11.

[0036] 图13是图示了包括使用检查点来校准用于存储器单元的预定函数的如图10所示的步骤300的流程图。 [0036] FIG. 13 is a flowchart illustrating the steps comprising the use of checkpoints illustrated to calibrate the predetermined function for a memory cell 300 in FIG. 10.

[0037] 图14图示了使用多于一个检查点的预测编程的实施例的第一例子。 The first example of an embodiment of a prediction program [0037] FIG. 14 illustrates the use of more than one checkpoint.

[0038] 图15图示了图14所示的检查点被用于校准这些检查点局部的各种相关预定函数的方式。 [0038] FIG. 15 illustrates a checkpoint is shown in FIG. 14 for calibrating the various localized manner associated predetermined functions these checkpoints.

[0039] 图16图示了使用多于一个检查点的预测编程的实施例的第二例子。 [0039] FIG. 16 illustrates an example of the second embodiment uses predictive programming more than one check point.

具体实施方式 Detailed ways

[0040] 存储器系统 [0040] Memory system

[0041] 图1到图5图示了可以实现本发明的各个方面的示例存储器系统。 [0041] Figures 1 to 5 illustrate various aspects may be implemented example memory system of the present invention.

[0042] 图6图示了传统的编程技术。 [0042] FIG. 6 illustrates a conventional programming techniques. [0043] 图7到图16图示了本发明的各个方面和实施例。 [0043] Figures 7 through 16 illustrate various aspects and embodiments of the present invention.

[0044] 图1示意性地图示了可以实现本发明的非易失性存储器芯片的功能块。 [0044] FIG. 1 schematically illustrates the present invention may be implemented in a non-volatile memory chip functional blocks. 该存储器芯片100包括存储器单元的二维阵列200、控制电路210和诸如解码器、读/写电路和多路复用器的外围电路。 The memory chip 100 includes a two-dimensional array of memory cells 200, control circuitry 210 and such as decoders, read / write circuit and a peripheral circuit of a multiplexer.

[0045] 存储器阵列200可由字线经由行解码器230 (分裂成230A、230B)以及由位线经由列解码器260(分成260A、260B)寻址(还参见图4和图5)。 [0045] The memory array 200 is addressable by word lines via row decoders 230 (split into 230A, 230B) and by bit lines via column decoders 260 (split into 260A, 260B) addressing (see also FIGS. 4 and 5). 读/写电路270 (分裂成270A、270B)允许并行地读取或编程一页存储器单元。 Read / write circuits 270 (split into 270A, 270B) to allow parallel read or programmed in a memory cell. 数据I/O总线231被耦接到读/写电路270。 Data I / O bus 231 is coupled to the read / write circuit 270.

[0046] 在优选实施例中,页由共享相同字线的相邻行的存储器单元构成。 [0046] embodiment, the page consists of memory cells share the same word line of the adjacent row in the preferred embodiment. 在另一实施例中,在一行存储器单元被划分成多个页的情况下,提供块多路复用器250(分裂成250A和250B)以将读/写电路270多路复用到各个页。 In the case of another embodiment, in a row of memory cells are partitioned into multiple pages, block multiplexers 250 provide (split into 250A and 250B) to the read / write circuits 270 to the individual pages multiplexer . 例如,分别由奇数列和偶数列的存储器单元形成的两个页被复用到读/写电路。 For example, each formed of odd columns and even columns of memory cells two pages are multiplexed to the read / write circuits.

[0047] 图1图示了如下优选布置,其中以对称方式在存储器阵列200的相对侧上实现由各种外围电路对该存储器阵列200的访问,使得在每侧上的访问线(access line)和电路的密度减少一半。 [0047] FIG. 1 illustrates a preferred arrangement is as follows, where implemented in a symmetrical manner on opposite sides of the memory array 200 by the various peripheral circuits access the memory array 200, such that on each side of the access line (access line) density circuits and reduced by half. 因此,行解码器被分为行解码器230A和230B,列解码器被分为列解码器260A和260B。 Thus, the row decoder is split into row decoders 230A and 230B, the column decoder into column decoders 260A and 260B. 在一行存储器单元被划分成多个页的实施例中,页多路复用器250被分裂成页多路复用器250A和250B。 In the row of memory cells is divided into a plurality of pages embodiments, the page multiplexer 250 is split into page multiplexers 250A and 250B. 类似地,读/写电路270被分裂成从阵列200的底部连接到位线的读/写电路270A和从阵列200的顶部连接到位线的读/写电路270B。 Similarly, the read / write circuits 270 are split into read bit line is connected from the bottom 200 of the array / write circuits 270A and the read bit line is connected from the top of the array 200 / write circuits 270B. 以此方式,读/写模块的密度以及由此的感测模块380的密度实质上减少了一半。 In this manner, the read / write modules, and thus the density of the sense module 380 is substantially halved.

[0048] 控制电路110是与读/写电路270合作以对存储器阵列200执行存储器操作的芯片上(on-chip)控制器。 [0048] The control circuit 110 is a read / write controller circuit 270 cooperate to on-chip memory array 200 to perform memory operations (on-chip). 控制电路110典型地包括状态机112和诸如芯片上地址解码器和功率控制模块之类的其他电路(未明确示出)。 The control circuit 110 typically includes a state machine 112 and other circuits such as an on-chip address decoder and a power control module or the like (not explicitly shown). 状态机112提供对存储器操作的芯片级控制。 The state machine 112 provides chip level control of memory operations. 控制电路经由外部存储器控制器与主机通信。 The control circuit communicates via an external memory controller and the host.

[0049] 存储器阵列200典型地被组织为以行和列排列的并且可由字线和位线寻址的存储器单元的二维阵列。 [0049] The memory array 200 is typically organized in rows and a two dimensional array and by word lines and bit lines in the addressed memory cells arranged in columns. 可以根据NOR型或NAND型体系结构来形成该阵列。 The array can be formed according to an NOR type or a NAND type architecture.

[0050] 图2示意性地图示了非易失性存储器单元。 [0050] FIG. 2 schematically illustrates a non-volatile memory cells. 可以通过具有诸如浮置栅极或介电层之类的电荷存储单元20的场效应晶体管来实现存储器单元10。 The memory unit 10 may be implemented by a field effect transistor having a charge storage unit such as a floating gate or dielectric layer 20 or the like. 存储器单元10还包括源极 The memory cell 10 also includes a source

14、漏极16和控制栅极30。 14, the drain 16 and control gate 30.

[0051] 存在许多如今正在使用的商业上成功的非易失性固态存储器器件。 [0051] There are many successful non-volatile solid-state memory devices being used commercially today. 这些存储器器件可以采用不同类型的存储器单元,每种类型具有一个或多个电荷存储元件。 These memory devices may employ different types of memory cells, each type having one or more charge storage element.

[0052] 典型的非易失性存储器单元包括EEPROM和快闪EEPROM。 [0052] Typical non-volatile memory cells include EEPROM and flash EEPROM. EEPROM单元的例子以及制造该单元的方法在美国专利N0.5595024中给出。 Examples of the cell and a manufacturing method of an EEPROM cell in given in U.S. Patent No. N0.5595024. 快闪EEPROM单元的例子、其在存储器系统中的使用以及制造其的方法在美国专利N0.5070032、5095344、5315541、5343063、5661053,5313421和6222762中给出。 Examples of flash EEPROM cells, which uses in memory systems and methods of making thereof are given in U.S. Patent No. 6,222,762 and in N0.5070032,5095344,5315541,5343063,5661053,5313421. 具体地,具有NAND单元结构的存储器器件的例子在美国专利N0.5570315,5903495,6046953中描述。 In particular, examples of memory devices with NAND cell structures are described in U.S. Patent No. N0.5570315,5903495,6046953. 而且,利用电介质存储元件的存储器器件的例子已经由Eitan等人在IEEE Electron Device Letters,第21卷,2000年11月第11期,543-545 页“NROM:A Novel Localized Trapping, 2-BitNonvolatile Memory Cell” 中以及在美国专利N0.5768192和N0.6011725中描述。 Also, examples of memory devices utilizing dielectric storage element have been described by Eitan et al., IEEE Electron Device Letters, Vol. 21, November 2000, No. 11, pp. 543-545 "NROM: A Novel Localized Trapping, 2-BitNonvolatile Memory Cell "and described in U.S. Patent N0.5768192 and in the N0.6011725.

[0053] 实践中,通常通过当参考电压被施加到控制栅极时感测经过单元的源极和漏极的导电电流来读取该单元的存储器状态。 [0053] In practice, usually it is applied to the control gate of the sensing electrode unit through the source and the drain conduction current to read a memory state of the cell when a reference voltage by. 因此,对于在单元的浮置栅极上的每个给定的电荷,可以检测到相对于固定的参考控制栅极电压的相应的导电电流。 Thus, for each given charge on the floating gate of a cell can be detected with respect to the fixed reference current corresponding to the conductive control gate voltage. 类似地,可编程到浮置栅极上的电荷的范围定义了相应的阈值电压窗口或相应的导电电流窗口。 Similarly, the range may be programmed into the floating charge on the gate defines a corresponding threshold voltage window or a corresponding conduction current window.

[0054] 可替换地,代替检测在划分的电流窗口之中的导电电流,能够在控制栅极处对于在测试下的给定存储器状态设置阈值电压,并检测导电电流低于还是高于阈值电流。 [0054] Alternatively, instead of detecting the conduction current among a partitioned current window, it is possible at the control gate, for a given memory state under test set threshold voltage, and the detected current is lower or higher than a conductive current threshold . 在一个实施方式中,通过检查导电电流通过位线的电容而放电的速率来完成导电电流相对于阈值电流的检测。 In one embodiment, the rate of the capacitor through checking the conduction current through the bit line discharged to complete the conduction current relative to a threshold current is detected.

[0055] 图3图示了对于在浮置栅极可以在任意一个时刻选择性地存储的四个不同的电荷Ql到Q4的源极-漏极电流Id和控制栅极电压Va之间的关系。 [0055] FIG. 3 illustrates the floating gate electrode to be at any one time four different charges selectively storing Ql to Q4 of the source - the relationship between the drain current Id and the control gate voltage Va . 四个实线的Id相对Vra曲线代表了可以被编程到存储器单元的浮置栅极上的四个可能的电荷水平,分别对应于四个可能的存储器状态。 Id four solid-line curve represents the relative Vra four possible charge levels that can be programmed into the floating gate memory cell, respectively corresponding to four possible memory states. 作为例子,全体单元的阈值电压窗口可以从0.5V到3.5V。 As an example, the threshold voltage window of a population of cells from 0.5V to 3.5V. 可以通过以每个0.5V的间隔将阈值窗口划分成5个区域来对分别代表一个可擦除的和六个编程的状态的七个可能的存储器状态“0”、“1”、“2”、“3”、“4”、“5”、“6”划界。 May be for representing a six erasable and programmable by the interval of each state of the 0.5V threshold window into five regions seven possible memory states "0", "1", "2" , "3", "4", "5", "6" demarcation. 例如,如果如所示地使用2μ A的参考电流IREF,则可以认为用Ql编程的单元处于存储器状态“ 1”,因为其曲线与Ikef相交在由VCG = 0.5V和1.0V划界的阈值窗口的区域中的。 For example, if a reference current, IREF 2μ A as shown, with Ql may be considered a memory cell is in a programmed state "1" since its curve intersects with Ikef threshold by VCG = 0.5V and 1.0V window delimitation the region. 类似地,Q4处于存储器状态“5”。 Similarly, Q4 is in a memory state "5."

[0056] 如从以上描述可见,使得存储器单元存储的状态越多,其阈值窗口划分得越精细。 [0056] As seen from the above description, so that the state of the memory cell stores more, its threshold window is more finely divided. 例如,存储器器件可以具有如下存储器单元,该存储器单元具有范围从-1.5V到5V的阈值窗口。 For example, the memory device may have a memory cell, the memory cell having a range from -1.5V to 5V threshold window. 这提供了6.5V的最大宽度。 This provides a maximum width of 6.5V. 如果存储器单元要存储16个状态,则每个状态可能占据阈值窗口中的200mV到300mV。 If the memory cell is to store 16 states, each state may occupy 200mV to 300mV threshold window. 这将要求编程和读取操作中的更高精度,以便能够实现要求的分辨率。 This programming and reading operations will require more precision in order to achieve the required resolution.

[0057] 图4图示了存储器单元的NOR阵列的例子。 [0057] FIG 4 illustrates an example of an NOR array of memory cells. 在存储器阵列200中,每行存储器单元通过其源极14和漏极16以菊花链(daisy-chain)方式连接。 In the memory array 200, each row of memory cells 14 and drains 16 in a daisy chain (daisy-chain) are connected by their sources. 该设计有时称作虚拟接地设计。 This design is sometimes referred to as a virtual ground design. 一行中的单元10具有连接到诸如字线42之类的字线的其控制栅极30。 Row unit 10 has connected to the word line such as word line 42 or the like of the control gate 30 thereof. 一列中的单元具有分别连接到诸如位线34和36之类的所选位线的其源极和漏极。 The unit has a source and a drain connected to bit line 34, such as a selected bit line 36 and the like.

[0058] 图5A示意性地图示了被组织成NAND串的存储器单元的串。 [0058] FIG 5A schematically illustrates the memory cells organized into a NAND string string. NAND串50包括通过 Through NAND string 50 comprises

其源极和漏极而菊花链连接的一系列存储器晶体管Ml、M2、......Mn (例如η = 4、8、16或 A series of memory transistors Ml and the source and drain of the daisy chain connection, M2, ...... Mn (η = 4,8,16 or e.g.

更高)。 higher). 一对选择晶体管S1、S2控制存储器晶体管链分别经由NAND串的源极端54和漏极端56与外部的连接。 A pair of select transistors S1, S2 controls the memory transistors chain are connected via a terminal 54 and terminal 56 to the external source and drain of the NAND string. 在存储器阵列中,当源极选择晶体管SI导通时,源极端被耦接到源极线(见图5B)。 In a memory array, when the source select transistor SI is turned on, the source terminal is coupled to a source line (see FIG. 5B). 类似地,当漏极选择晶体管S2导通时,NAND串的漏极端被耦接到存储器阵列的位线。 Similarly, when the drain select transistor S2 is turned on, the drain terminal of the NAND string is coupled to a bit line of the memory array. 该链中的每个存储器晶体管10用作存储器单元。 Each of the memory transistors in the chain 10 is used as a memory cell. 其具有用于存储给定量的电荷以便表不意图的存储器状态的电荷存储兀件20。 It has a charge for storing a given amount so that the table is not intended memory state of the charge storage element 20 Wu. 每个存储器晶体管的控制棚极30允许对读和写操作的控制。 Shed control electrode 30 of each memory transistor allows control over read and write operations. 如将从图5B中看到的,一行NAND串的相应存储器晶体管的控制栅极30全部被连接到相同的字线。 As seen from FIG. 5B, the control gates 30 of corresponding memory transistors of a row of NAND string are all connected to the same word line. 类似地,每个选择晶体管S1、S2的控制栅极32提供了分别经由其源极端54和56对NAND串的控制访问。 Similarly, each of the select transistors S1, the control gate 32, S2 provides control access respectively, via its source terminal 54 and 56 of the NAND string. 同样,一行NAND串的相应的选择晶体管的控制栅极32全部被连接到相同的选择线。 Similarly, the corresponding control gate select transistors of a row of NAND strings 32 are all connected to the same select line.

[0059] 当在编程期间读取或验证NAND串内的被寻址的存储器晶体管10时,向其控制栅极30供应适当的电压。 [0059] When the read or verify an addressed memory transistor within a NAND string during programming 10, supply an appropriate voltage to its control gate 30. 同时,NAND串50中的剩余未被寻址的存储器晶体管通过在其控制栅极上施加足够的电压而完全导通。 Meanwhile, the remaining non-addressed memory transistors in the 50 NAND string by applying sufficient voltage on their control gate is completely turned on. 以此方式,有效地建立从各个存储器晶体管的源极到NAND串的源极端54以及同样对于各个存储器晶体管的漏极到该单元的漏极端56的导电通路。 In this manner, effectively build from a source of the individual memory transistor to the source terminal 54 of the NAND string and likewise for the drain of the individual memory transistor to the drain terminal of the cell 56 conductive paths. 在美国专利N0.5570315、5903495、6046935中描述了具有这种NAND串结构的存储器器件。 In U.S. Patent No. N0.5570315,5903495,6046935 described Memory devices with such NAND string structures.

[0060] 图5B图示了由诸如图5A所示的NAND串的NAND串50构成的存储器单元的NAND阵列200的例子。 [0060] FIG. 5B illustrates an example of an NAND array of memory cells 200 consisting of NAND strings shown in FIG. 5A NAND strings 50 such as a. 沿着NAND串的每列,诸如位线36的位线耦接到每个NAND串的漏极端56。 Along each column of NAND strings, a bit line such as bit line 36 is coupled to the drain terminal 56 of each NAND string. 沿着NAND串的每排(bank),诸如源极线34的源极线被耦接到每个NAND串的源极端54。 Along each row (Bank) NAND strings, a source line such as source line 34 is coupled to the source terminal of each NAND string 54. 而且,沿着NAND串的排中的一行存储器单元的控制栅极被连接到诸如字线42的字线。 Further, connected to the word line such as word line 42 of the control gates along a row of memory cells in a row of NAND strings. 沿着NAND串的排中的一行选择晶体管的控制栅极被连接到诸如选择线44的选择线。 Control gates are connected along rows of the NAND string selection transistor to the row select line such as line 44. 可以通过对NAND串的排的字线和选择线上的适当的电压来对NAND串的排中的整个行的存储器单元寻址。 It can be addressed through the rows of the memory cells of the NAND string and the word line select line of appropriate voltages to an entire row of NAND strings row. 当NAND串内的存储器晶体管正被读取时,该串中剩余的存储器晶体管经由其关联的字线而艰难地导通,使得流经该串的电流基本上取决于正被读取的单元中存储的电荷的水平。 When a memory transistor within a NAND string is being read, the remaining memory transistors in the string via their associated word lines turned on hard so that the current flowing through the string is essentially dependent on the cell being read level of stored charge.

[0061] 图6图示了用于将存储器单元编程到目标存储器状态的传统技术。 [0061] FIG. 6 illustrates a conventional technique for programming memory cells to a target memory state. 经由耦接的字线将编程电压Vrai施加到存储器单元的控制栅极。 Coupled via a word line program voltage Vrai applied to the control gate of the memory cell. Vrai是以从初始电压电平Vraro开始的阶梯形波形的形式的一系列编程电压脉冲。 Vrai form of a stepped waveform starting from an initial voltage level Vraro series of programming voltage pulses. 正在被编程的单元经历该一系列编程电压脉冲,每次试图将增量的电荷添加到该浮置栅极。 It is subjected to the cell programmed series of programming voltage pulses, each time attempting to add incremental charges to the floating gate. 在编程脉冲之间,回读(read back)或验证该单元以确定相对于断点水平的其源极-漏极电流。 In between programming pulses, read back (read back) unit or verified to determine the breakpoint level with respect to its source - drain current. 该回读处理可以包含一个或多个感测操作。 The read back process may comprise one or more sensing operation. 当已经验证了达到目标状态时,对于单元停止编程。 When the state has been verified to reach the target, to stop the programming unit. 使用的编程脉冲串可以具有增加的周期或幅值,以便抵消被编程到存储器单元的电荷存储单元中的累积的电子。 Programming pulse train used may have increasing period or amplitude in order to counteract the accumulation of the memory cell is programmed into the charge storage unit electrons. 编程电路通常将一系列编程脉冲施加到所选择的字线。 Programming circuits generally a series of programming pulses to a selected word line. 以此方式,可以对其控制栅极被耦接到该字线的一页存储器单元一起编程。 In this manner, it can be coupled to the word line of a memory cell programmed with its control gate. 无论何时已经将该页的存储器单元编程到其目标状态,则其被禁止编程,同时其他单元继续经历编程,直到该页的所有单元都已经被编程验证。 Whenever a memory cell has been programmed to its target state to the page, it is program-inhibited while the other cells continue to experience programming until all cells of the page have been program- verified.

[0062] 使用一系列交替的编程/验证循环的传统编程技术用于应对如下编程处理中的不确定性,在该编程处理中响应于VrcM的相对较大的变化,该单元的阈值电压初始地迅速增长。 [0062] using a series of alternating program / verify cycles is to deal with conventional programming techniques to uncertainties in the programming process, the programming process in response to a relatively large change VrcM, the threshold voltage of the cell is initially fast growing. 然而,随着被编程到浮置栅极中电荷用作用于减小使得电子进一步穿越进入浮置栅极的有效电场的屏蔽,该增长放慢并最终停止。 However, as programmed into the floating gate so that charge used for reducing electron entering further effectively shield the electric field across the floating gate, which is slow and eventually stop the growth. 该过程看起来是高度非线性的,因此采用了反复试验(trial-and-error)方式。 The process appears highly non-linear, and therefore used the trial (trial-and-error) mode.

[0063] 该编程/验证编程技术的缺点是,验证循环花费时间并影响性能。 [0063] The disadvantage of the program / verify programming technique is that the verify cycle takes up time and impacts performance. 通过实现能够存储多个位的存储器单元,加剧了该问题。 By implementing a memory cell capable of storing a plurality of bits, exacerbated the problem. 本质上,需要对存储器单元的多个可能状态的每个执行验证。 Essentially, a plurality of memory cells may be performed for each validation status. 对于具有16个可能的存储器状态的存储器,这意味着每个验证步骤将引起至少16个感测操作。 For a memory with 16 possible memory states, this means each verify step would cause at least 16 sensing operations. 在一些其他方案中,其甚至是几倍多。 In some other scenarios, it may even be several times more. 因此,随着多电平存储器单元(“MLC”)中的状态电平的数量增加,编程/验证方案的验证循环变得越来越耗时。 Thus, as the number of state-level multi-level memory cell ( "MLC") in, verify cycle program / verify scheme becomes increasingly time-consuming.

[0064] 因此,存在对于最小化前述缺点的、具有改善的编程性能的存储器器件的需要。 [0064] Therefore, there is minimized the shortcomings, a memory device having a need for improved programming performance. _5]预测编程技术 [5] predictive programming technology

[0066] 根据本发明的一个一般方面,在具有存储器单元的阵列的非易失性存储器中,其中可将存储器单元分别编程到阈值电压电平的范围之一,提供了预测需要施加多大的编程电压电平以便将给定的存储器单元编程到给定的目标阈值电压电平的预定函数。 [0066] According to a general aspect of the present invention, in a nonvolatile memory array having memory cells, wherein each memory cell can be programmed to one of the range of the threshold voltage level is provided to be applied predict how much programming the voltage level for a given memory cell is programmed to a predetermined function of a given target threshold voltage level. 以此方式,不需要执行验证操作,由此极大地改善了编程操作的性能。 In this way, no verify operation is performed, thereby greatly improving the performance of the programming operation.

[0067] 在一个实施例中,通过对于给定的目标阈值电压电平按比例地产生编程电压电平的线性函数来近似该预定函数。 [0067] In one embodiment, the predetermined function is approximated by a linear function for a given target threshold voltage level of the programming voltage level is generated proportionally. 线性函数具有由可施加到存储器阵列的全体单元的预定平均值给定的斜率。 Linear function having a predetermined average population of cells applied to the memory array by a given slope. 通过对于给定的存储器单元预定在线性函数上的检查点,对于给定的存储器单元唯一地确定该线性函数。 By checking for a given point on the linear function a predetermined memory cell, for a given memory cell of the linear function is uniquely determined. 该检查点是基于将存储器单元编程到指定的阈值电压电平的实际编程电压。 The checkpoint is based on the actual programmed threshold voltage level programming memory cells to the specified. 优选地,该检查点对应于存储器单元的最低编程状态之一。 Preferably, the inspection point corresponds to one memory cell of the lowest programmed state. 通过例如传统的编程/验证编程技术来将存储器单元初始地编程到该检查点并进行验证。 For example, by a conventional program / verify programming technique initially programmed memory cells to the check point and verify it. 以此方式,确定将存储器单元编程到指定的存储器状态所需的实际编程电压的检查点值。 In this manner, the determined value of the actual checkpoint programming voltage of the memory cell is programmed to the desired memory state designated. 因此在预定函数被用于确定用于将存储器单元编程到目标阈值电压电平的编程电压值之前,当在检查点阈值电压电平处被估计时,该预定函数被校准以产生检查点编程电压值。 Thus before being used to determine a memory cell is programmed to programming voltage value of the target threshold voltage level, when estimated at the checkpoint threshold voltage level, the predetermined function is calibrated in a predetermined function to generate the checkpoint programming voltage value.

[0068] 在另一实施例中,可以在存储器单元所支持的可能的阈值电压电平的范围内指定多个检查点。 [0068] In another embodiment, a plurality of check points can be specified in the range of possible threshold voltage level of the memory cell supported. 每个检查点将被用于校准在每个检查点附近的局部预定函数。 Each inspection point is used to calibrate the predetermined function in the vicinity of each of the partial checkpoint. 该局部预定函数被用于预测用于编程到在相关的检查点附近的目标阈值电压电平的编程电压电平。 The predetermined function is used to predict the local program for programming voltage level to the target threshold voltage level in the vicinity of the relevant checkpoint.

[0069] 预测编程技术的优点在于,编程到目标状态不需要验证操作。 [0069] The predictive programming technique is that the advantages, programmed to a target state does not require verify operations. 仅需要验证操作用于确定检查点,这在数量上通常比可能的存储器状态的数量少得多。 Need only verify operation to determine the checkpoint, which is usually much less in number than the number of possible memory states.

[0070] 将存在致使预测编程产生错误结果的偏差,不过这些将是在统计上可预测的误差,其可通过适当的误差校正码(“ECC”)来处理。 [0070] The present prediction cause erroneous results programming bias, but these will be statistically predictable error that can be handled by appropriate error correction code ( "ECC").

[0071] 图7图示了对给定的存储器器件中的各种存储器单元编程的实例以及在施加的编程电压和阈值电压电平之间的观测到的关系。 [0071] FIG. 7 illustrates a relationship observed between the various instances of the memory cell is programmed to a given memory device and a programming voltage and the threshold voltage level applied. 可以看出,即使跨越阈值窗口的实际范围,各个存储器单元的编程行为不可思议地是线性的。 As can be seen, even if the actual range crosses the threshold window, each memory cell programming behavior is linear incredible. 在阵列内的各个单元或多或少表现如下相同的方式,其中被编程的阈值电压的变化与编程电压电平的变化基本成比例。 Each cell in the array is more or less the same performance as the manner in which the change in programming voltage level changes with the programmed threshold voltage substantially proportional. 由于各个单元被擦除得有多深以及其他因素,各个单元可能相差几个编程脉冲以到达指定的检查点,但是各个单元的每个的预定函数具有基本类似的斜率。 Since each cell is erased how deep and other factors, the individual cells may differ by a few programming pulses to reach the check point, but the function of each of the predetermined cells each having a substantially similar slope. 图7示出了慢编程单元、快编程单元的每个的例子以及中间速率编程单元的一些例子(实线)。 Figure 7 shows a slow programming unit, each of some of the examples (solid line) and an example of a fast programming unit programming unit intermediate rate. 可以看出,不同例子间的斜率的变化很小。 As can be seen, the slope changes very little between different examples.

[0072] 图8示意性地图示了对于在给定的存储器器件中的存储器单元的实例的、如图7所示的斜率的分布。 [0072] FIG 8 schematically illustrates examples for memory cells in a given memory device, the slope of the distribution as shown in Fig. 该分布基本呈现出平均斜率在0.9左右并且标准偏差接近0.1的正态分布。 The basic distribution exhibits an average slope of about 0.9 and a standard deviation of approximately 0.1 normal. 实际的编程采用了两个不同的编程电压步幅大小。 The actual programming using two different program voltage step size. 已经观测到,这两个步幅大小产生了类似的分布和平均的斜率。 Has been observed, both produced a similar step size distribution and average slope.

[0073] 图9图示了用于提供将存储器单元编程到目标阈值电压电平所需的编程电压的预定函数的优选实施例。 [0073] FIG 9 illustrates a preferred embodiment for providing a predetermined function of the memory cell programmed to a target threshold voltage level required programming voltage. 通过如下关系来用其中给定目标阈值电平Vt为编程电压VrcM的函数的线性函数来近似预定函数: Wherein the relationship used by a given target threshold voltage level Vt is the programming function VrcM linear function approximated predetermined function:

[0074] Vt(Vpgm) = <Slope>VPGM+VT(0)式(I) [0074] Vt (Vpgm) = <Slope> VPGM + VT (0) of formula (I)

[0075](其中〈slope〉= Δ Vt/Δ Vpgm) [0075] (where <slope> = Δ Vt / Δ Vpgm)

[0076]相反, [0076] In contrast,

[0077] Vpgm(Vt) = l/<Slope>[VT-VT(0)]式(2) [0077] Vpgm (Vt) = l / <Slope> [VT-VT (0)] of formula (2)

[0078] 在优选实施例中,平均〈slope (斜率)> 可以通过在从类似产品批次中的工厂抽样时测试来预定。 [0078] embodiment, the average <slope (slope)> can be tested at a predetermined sampling from similar products in a batch plant in a preferred embodiment. 例如,该测试可以得到〈slope〉是0.9。 For example, the test can be <slope> 0.9. Vt(O)是取决于单元的并且在每个单元的预测编程之前通过来自每个存储器单元的检查点来预定。 Vt (O) depends on the predetermined unit and to pass a checkpoint from each memory cell prior to a predictive programming of each cell. 一旦〈slope〉和Vt(O)已知,就定义了用于该存储器单元的预定函数,并且等式(2)可以用于获得编程到目标阈值电压电平所需的编程电压电平。 Once <slope> and Vt (O) is known, the predetermined function is defined for the memory cell, and the equation (2) can be used to obtain the programming voltage level needed to program to a target threshold voltage level. [0079] 图10是图示了根据本发明的一般实施例的预测编程的流程图。 [0079] FIG. 10 is a flowchart illustrating a general embodiment of the prediction program of the present invention.

[0080] 步骤300:提供用于编程下的存储器单元的预定函数,该函数产生编程电压值作为存储器单元将被作为目标编程到的阈值电压电平的函数。 [0080] Step 300: providing the predetermined function of memory cells for programming the function of the threshold voltage function generating a programming voltage level as the memory cell to be programmed to a target.

[0081] 步骤310:利用具有增加的幅值的编程电压将存储器单元编程到目标阈值电压电平。 [0081] Step 310: using the increased programming voltage having a magnitude of memory cells programmed to the target threshold voltage level. 编程电压经由耦接的字线被施加到存储器单元的控制栅极。 Programming voltage is applied to the control gates of the memory cells via word lines coupled.

[0082] 步骤320:在编程电压基本达到如由在目标阈值电压电平处所估计的预定函数所确定的值后,停止存储器单元的编程。 [0082] Step 320: after the programming voltage reaches a value substantially the predetermined function of the target threshold voltage level of the premises as determined by the estimated stop programmed memory cells. 典型地,耦接到相同字线的一页存储器单元同时被编程。 Typically, the word lines coupled to the same page of memory cells simultaneously programmed. 当正讨论的存储器单元已经接收到由在目标阈值电压电平处所估计的预定函数所确定的值时,不管对于该页的其他存储器单元的在字线上的可能的另外的编程脉冲,仍禁止进一步的编程。 When the memory cell in question has received the predetermined value by the function at the target threshold voltage estimated at the level of the determined regardless of possible for further programming pulses other memory cells of the page in the word line, data is inhibited further programming.

[0083] 通常,不需要通过线性函数来近似预定函数。 [0083] Generally, the predetermined function need not be approximated by a linear function. 如果该预定函数要准确地覆盖宽范围的阈值电压电平,则它可以通过在工厂时测试产品批次以及通过某种适当的函数建模来确定。 If the predetermined function is to accurately cover a wide threshold voltage level range, it may be tested at the factory and the product lot is determined by some suitable function modeling.

[0084] 通常,正被编程的存储器单元是同时处于编程下的一页类似的存储器单元之一。 [0084] Generally, the memory cell being programmed at the same time is one similar to a memory cell under programming. 将存在为该页的每个存储器单元而提供的预定函数。 The presence of a predetermined function for each of the memory cells of the page provided. 由于该页的所有存储器单元共享相同的字线,因此一旦已经通过预测编程电压将该页的存储器单元编程,则禁止对其进一步编程。 Since all the page memory cells share the same word line, so once it has been predicted by the programming voltage to program memory cells of the page, its further programming is inhibited.

[0085] 优选地在控制存储器阵列200的存储器操作的控制电路110中的状态机112中(见图1)实现图10所示的预测编程模式。 [0085] Preferably, the memory control circuit 110 controls the memory array 200 operating in the state machine 112 (see FIG. 1) to achieve predictive programming mode 10 shown in FIG.

[0086] 图11图示了在校准图9所示的预定函数之后在预测编程模式中应用该预测函数的情况下的时序上的编程电压。 [0086] FIG. 11 illustrates a program voltage application timing in the case where the prediction function in the predictive programming mode after a predetermined calibration function shown in FIG 9.

[0087] 在初始阶段中,对于存储器单元的检查点(O) (checkpoint (O))被指定为处于稍微高于被认为与擦除状态相关联的电压电平的阈值电压电平(检查点阈值电压电平)处。 [0087] In the initial stage, for the checkpoint (O) (checkpoint (O)) is designated as a memory cell is considered to be slightly higher than the threshold voltage level (checkpoint voltage level associated with the erased state the threshold voltage level) at. 施加一系列增加的编程电压脉冲以将该存储器单元朝检查点阈值电压电平编程。 Applying a series of increasing programming voltage pulses to the memory cell toward the checkpoint threshold voltage level programming. 该编程模式可以是交替地编程和验证直到检查点阈值电压电平被编程验证的传统编程模式。 The programming mode may be alternately programming and verifying until the checkpoint threshold voltage level is program-verified traditional programming mode. 一旦已知用于checkpoint (O)的坐标集[VrcM, VT]cheekp()int((l),则可以对于Vt (O)来求解以等式⑵为形式的预定函数(见图9)并将其完整地表示。 Once known for the checkpoint (O) set of coordinates [VrcM, VT] cheekp () int ((l), it is possible for Vt (O) a predetermined function to be solved in the form of equation ⑵ (see FIG. 9) and represented in its entirety.

[0088] 在表示了以等式(2)为形式的预定函数后,随后可以使用该预定函数在编程模式中对存储器单元编程,以对于目标阈值电压电平或者对于目标存储器状态提供估计的编程电压电平。 [0088] representing a predetermined function of equation (2) is in the form of post, then you can use the predetermined function in the program mode of the memory cell is programmed to the target threshold voltage level or provide an estimate of the target memory state programmed voltage level. 在优选实施例中,调整编程电压步幅大小,使得每个增加脉冲(addition pulse)将把存储器单元编程到下一存储器状态。 In a preferred embodiment, the programming voltage step size adjustment, so that each additional pulse (addition pulse) will program the memory cell to the next memory state. 对于具有16个可能的存储器状态的存储器单元的例子,脉冲大小可以是300mV。 For the example of a memory cell with 16 possible memory states, the pulse size may be 300mV. 以此方式,一个增加的脉冲将把存储器编程到状态(1),另一增加的脉冲将把存储器编程到状态(2)等等。 In this manner, a pulse will increase memory programmed to state (1), further increasing pulse will program the memory to State (2) and the like. 因此,可以将编程到给定的存储器状态的步骤减少为从状态(O)起对状态的数量计数并供应相同数量的脉冲。 Thus, the step of programming to a given memory state can be reduced and count number of pulses supplied from the same number of states from the state (O). 例如,可以每次在状态(O)中设置标记,其后,可以通过与目标状态距状态(O)的状态数量相同的数量的脉冲对存储器单元编程。 For example, each time a flag is set in a state (O), thereafter, it may be the same state by the target state from the state (O) to the number of pulses for programming the memory cell.

[0089] 其他编程脉冲大小也是可能的。 [0089] Other programming pulse sizes are possible. 例如,对于具有16个可能的存储器状态的存储器单元,脉冲大小可以是150mV。 For example, for a memory cell with 16 possible memory states, the pulse size may be 150mV. 在该情况下,将用两个脉冲来从一个存储器状态编程到下一相邻的存储器状态。 In this case, the two pulses to program from one memory state to the next adjacent memory state. 这将在编程中提供更精细的分辨率,这在采用了距目标阈值的余量的某些实施方式中是有用的。 This will provide finer resolution in the programming, which uses the threshold from the target balance of certain embodiments is useful.

[0090] 图12示意性地图示了在图11所示的编程处理期间一页存储器单元的各种存储器状态的分布。 [0090] FIG. 12 schematically illustrates the distribution of the various memory states of a memory cell during the programming process shown in FIG. 11. 该页存储器单元以所有存储器单元处于被擦除状态开始,其可能处于任何一个低阈值电压电平。 The page of memory cells to all the memory cells in the erased state starts, which may be in any of a low threshold voltage level. 在初始的编程阶段期间,一系列编程/验证循环(例如总共X个编程脉冲加上n*x个验证步骤(Skp))将把存储器单元从擦除状态编程到状态(O)。 During the initial programming phase, a series of program / verify cycles (e.g., a total of X program pulses plus n * x verifying step number (Skp)) memory cells will be programmed from the erased state to a state (O). 通常,对于每个存储器单元的X彼此独立。 Typically, X independently of one another for each memory cell. 一旦存储器单元处于状态(O),预测编程模式开始,并且每个增加的脉冲将把存储器单元编程到下一存储器状态。 Once the memory cell is in state (O), predictive programming mode is started, and each additional pulse will program the memory cell to the next memory state.

[0091] 图13是图示了包括使用检查点校准用于存储器单元的预定函数的图10中所示的步骤300的流程图。 [0091] FIG. 13 is a flowchart illustrating the steps shown in FIG. 10 include the use of check-point calibration function for a predetermined memory cell 300.

[0092] 步骤302:指定所述函数的检查点作为可由相应的检查点编程电压值编程的、指定的检查点阈值电压电平。 [0092] Step 302: Specify the checkpoint as a function of the corresponding checkpoint programming voltage value programmed, designated checkpoint threshold voltage level may be.

[0093] 步骤304:通过交替地编程和验证直到该检查点阈值电压电平被编程验证,确定相应的检查点编程电压值。 [0093] Step 304: by alternately programming and verifying until the checkpoint is verified threshold level programming voltage, determines the corresponding checkpoint programming voltage value.

[0094] 步骤306:在预定函数被用于确定将存储器单元编程到目标阈值电压电平的编程电压值之前,当在检查点阈值电压电平处被估计时,校准该预定函数以产生检查点编程电压值。 [0094] Step 306: is used to determine the memory cell is programmed prior to programming voltage value of the target threshold voltage level, when estimated at the checkpoint threshold voltage level, to calibrate the predetermined function a predetermined function to produce a checkpoint programming voltage value.

[0095] 图14图示了使用多于一个检查点的预测编程的实施例的第一例子。 The first example of an embodiment of a prediction program [0095] FIG. 14 illustrates the use of more than one checkpoint. 在第一例子中,在检查点模式下被编程的存储器状态在要通过预测模式编程的每个存储器状态之前。 In a first example, in the checkpoint mode is programmed through the memory state prior to programming each memory mode prediction state. 在图13中在步骤302和步骤304中描述了检查点模式。 In Figure 13 depicts the checkpoint mode in step 302 and step 304. 如果存储器单元可以逐步地被编 If the memory cell may be programmed to gradually

程为状态(O)、状态(I)、状态(2),......,则可以指定偶数状态,状态(O)、状态(2)、状态 Cheng state (O), state (the I), the state (2), ......, you can specify an even state, state (O), the state (2), the state

(4),......为检查点。 (4), ...... checkpoint. 通过编程/验证编程模式(见图6)从前一状态到达这些状态。 By the program / verify programming mode (see FIG. 6) reaches the state from the previous state. From

每个检查点,可以校准预测函数,并将其用于预测性地编程下一存储器状态,例如奇数状态⑴、状态⑶、状态(5),......[0096] 图14所示的实施例允许预测模式下的编程最准确,这是因为每隔一个存储器状态来重新校准该预定函数,并且在这种短间隔中,单元编程行为呈现出良好的线性。 Each checkpoint, the prediction function may be calibrated and used predictively next programmed memory state, for example, an odd state ⑴, state ⑶, state (5), ...... [0096] 14 shown in FIG. embodiment allows programming in the most accurate prediction mode, because every memory state to recalibrate the predetermined function, and in such a short interval, the cell programming behavior exhibited good linearity. 由于仅每隔一个存储器状态在检查点模式下被编程,因此避免了传统编程(见图6)中的至少一半的验证操作。 Since at least half of a verify operation in the memory state is programmed mode only every check point, thus avoiding traditional programming (see FIG. 6).

[0097] 图15图示了图14所示的检查点用于校正在这些检查点局部的各种相关的预定函数的方式。 [0097] FIG. 15 illustrates a checkpoint shown in FIG. 14 for correcting various related embodiment local predetermined function of these checkpoints. 将看出,所有的局部预定函数都是线性的,且具有相同的预定平均斜率。 It will be seen, all of the predetermined functions are locally linear, and having the same predetermined average slope. 检查点 checking point

(O)被用于设置用于局部预定函数400的边界条件。 (O) is used for setting a predetermined function of the local boundary conditions of 400. 类似地,检查点(2)被用于设置用于局部预定函数420的边界条件,且检查点(4)被用于设置用于局部预定函数440的边界条件, Similarly, the inspection point (2) is used for setting a predetermined function of the local boundary conditions 420, and the check point (4) is used to set boundary conditions for locally predefined function 440,

坐坐寸寸ο Begins to sit ο

[0098] 一旦设置了局部预定函数,其可以被用于产生用于下一存储器状态的编程电压电平。 [0098] Once a predetermined function is provided locally, it may be used to generate the programming voltage level for the next memory state. 因此,局部预定函数400被用于产生将该单元编程到状态(I)的编程电压电平,局部预定函数420被用于产生将该单元编程到状态(3)的编程电压电平,且局部预定函数440被用于产生将该单元编程到状态(5)的编程电压电平,等等。 Thus, the local 400 are used to generate a predetermined function of the cell is programmed to programming voltage level state (I), the local 420 are used to generate a predetermined function of the cell is programmed to state (3) the programming voltage level, and local 440 is used to generate a predetermined function of the cell is programmed to state (5) of the programming voltage level, and the like.

[0099] 图16图示了使用多于一个检查点的预测编程的实施例的第二例子。 [0099] FIG. 16 illustrates an example of the second embodiment uses predictive programming more than one check point. 与图14和图15中所示的第一例子相反,第二例子每四个(every four)存储器状态指定一个检查点。 In contrast, the second example every four (every four) memory state of a check point 14 and the first example shown in FIG. 15. 因此,在状态(O)、在状态(4)、在状态(8)等处指定检查点(O)。 Thus, in a state (O), in the state (4), in the state (8), etc. designated checkpoint (O). 由检查点(O)设置的局部预定函数将被用于预测分别用于下三个存储器状态、即状态(I)、状态(2)和状态(3)的编程电压。 Partially predetermined set by the function checkpoint (O) will be used for the prediction are three memory state, i.e. the state (the I), the state (2) and a state (3) of the programming voltage. 类似地,由检查点(4)设置的局部预定函数将被用于预测分别用于下三个状态、即状态(5)、状态¢)、状态(7)等等的编程电压。 Similarly, the local predetermined function (4) is provided by a checkpoint to be used for the prediction are three states, i.e., state (5), ¢ state), a state (7) the programming voltage or the like. 从第二例子得到的预测的编程电压将不如第一例子那样准确,但是在很多应用中也可能是足够的。 Prediction programming voltage obtained from the second example of the first example will not be as accurate, but in many applications it may be sufficient. 其具有进一步减少编程验证操作的次数的优点。 Which has the advantage of further reducing the number of program verify operation.

[0100] 在存储器单元的阈值窗口中的阈值的范围内的指定的检查点的其他变化是可能的。 [0100] Other variations to the specified checkpoint threshold range of the threshold window of the memory cells is possible. 可以根据性能和准确性之间的平衡做出选择。 You can make a choice based on a balance between performance and accuracy.

[0101] 例如,在某些编程算法中,第一遍将该页存储器单元都编程为靠近其各自的目标状态。 [0101] For example, in some programming algorithm, the first pass, the page memory cells are programmed to be near their respective target states. 然后,第二遍编程将完成到各自目标状态的编程。 Then, the second programming pass to complete the programming of the respective target state. 两遍的方法被用于减轻在相邻存储器单元的浮置栅极之间的编程干扰。 The method of two-pass programming is used to mitigate interference between the floating gates of neighboring memory cells. 由于第一遍编程没有要求像第二遍那样高的精确度,因此可以使用预测编程模式进行这第一遍以节省时间。 Since the first programming pass, like the second pass as high accuracy is not required, it is possible to use first-pass this predictive programming mode in order to save time. 在一些实施方式中,也将第二遍编程也构思为优选地适当地利用多个检查点来采用预测编程模式。 In some embodiments, the second programming pass can also be conceived to appropriately use a plurality of preferably checkpoint predictive programming mode.

[0102] 预测编程模式不排除越过(overshoot)目标阈值电压电平的极小的可能性(估计为小于0.1% )。 Remote possibility [0102] predictive programming mode does not exclude crossed (overshoot) the target threshold voltage level (estimated to be less than 0.1%). 在目标存储器状态被越过的情况下,可以通过实施的误差校正码来校正误差。 In the case where the target memory state to be crossed, an error can be corrected by the error correcting code implementation.

[0103] 当可用两个检查点时,能够独立地设置预定函数的斜率。 [0103] When the two check points is available, it can be provided independently of the slope of the predetermined function. 一旦如此规定了预定函数,就可以将其用于产生用于随后的存储器状态的编程电压电平。 Once a predetermined function so specified, it may be used to generate the programming voltage level for a subsequent memory states.

[0104]为了所有目的,将在此参考的所有专利、专利申请、文章、书目、规范、其他公开、文件和事物通过对其全部的此引用而合并于此。 [0104] For all purposes, this All patents, patent applications, articles, books, specifications, other publications, documents and things by their all this reference incorporated herein. 对于在并入的任何出版物、文件或事物与本发明的文本之间的术语的定义和使用不一致或相矛盾的地方,将以本文中的术语的定义或使用为准。 For the definitions of terms between any publication incorporated text file or things and the present invention where the use of inconsistent or contradictory, definition or use of terms herein will prevail.

[0105] 尽管已经针对某些实施例描述了本发明的各个方面,应理解,本发明的权利在于在所附权利要求的完全范围内的保护。 [0105] Having described various aspects of the invention with respect to certain embodiments, it should be understood that the claims of the present invention is protected within the full scope of the appended claims.

Claims (33)

1.一种在具有存储器单元的阵列的非易失性存储器中,其中存储器单元各自可被编程到阈值电压电平的范围之一,将存储器单元编程到目标阈值电压电平的方法包括: 为处在编程下的存储器单元提供预定函数,该函数产生编程电压值作为存储器单元被作为目标编程到的阈值电压电平的函数; 利用具有增加的幅值的编程电压,将存储器单元编程到目标阈值电压电平;以及在所述编程电压基本达到由在所述目标阈值电压电平处估计的预定函数所确定的值后,停止存储器单元的编程;以及其中所述提供预定函数包括: 指定所述函数的检查点作为可由相应的检查点编程电压值编程的指定的检查点阈值电压电平; 通过交替地编程和验证直到该检查点阈值电压电平被编程验证,来确定该相应的检查点编程电压值;以及在预定函数被用于确定将存储器单元编程到 1. A nonvolatile memory array having memory cells in which each memory cell can be programmed to one of a range of values ​​of the threshold voltage level, the memory cell programming method to the target threshold voltage level comprises: is in the programmed memory cells to provide a predetermined function that generates the programming voltage value as a target program to a memory cell function of the threshold voltage level; using a programming voltage having an increased amplitude, the memory cell is programmed to the target threshold the voltage level; and after the programming voltage reaches substantially the predetermined function of the estimated value of the target threshold voltage level is determined, the programmed memory cell is stopped; and wherein said predetermined function comprises: specifying the checkpoint as a function of designated checkpoint threshold voltage level of the corresponding checkpoint programming voltage value of the program may be; by alternately programming and verifying until the checkpoint threshold voltage level is program-verified to determine whether the corresponding checkpoint programming voltage; and a function for determining the predetermined memory cell is programmed to 标阈值电压电平的编程电压值之前,当在检查点阈值电压电平处估计时,校准所述预定函数以产生检查点编程电压值。 Before programming voltage standard threshold voltage level, when the estimated value at the checkpoint threshold voltage level, said predetermined calibration function so as to generate the checkpoint programming voltage value.
2.如权利要求1所述的方法,其中所述具有增加的幅值的编程电压是一系列电压脉冲。 2. The method according to claim 1, wherein said voltage magnitude with increasing programming voltage pulses is a series.
3.如权利要求1所述的方法,其中所述预定函数基本上是线性函数。 The method according to claim 1, wherein the predetermined function is substantially a linear function.
4.如权利要求1所述的方法,其中目标阈值电压电平小于来自检查点阈值电压电平的预定电压。 4. The method according to claim 1, wherein the target threshold voltage level is less than the predetermined voltage from the checkpoint threshold voltage level.
5.如权利要求1所述的方法,其中在阈值电压电平的范围内指定一个或多个检查点阈值电压电平。 5. The method according to claim 1, wherein the range of the threshold voltage level of the one or more designated checkpoint threshold voltage level.
6.如权利要求1所述的方法,其中所述预定函数是线性的,并由估计的斜率和检查点来定义。 And the slope of the checkpoint method as claimed in claim 1, wherein said predetermined function is linear, the estimated by defined.
7.如权利要求1所述的方法,其中所述预定函数基本是线性的,并由至少两个检查点来定义。 7. The method according to claim 1, wherein the predetermined function is substantially linear, at least by two checkpoints defined.
8.如权利要求1所述的方法,其中所述非易失性存储器具有各自存储多于一位的数据的存储器单元。 8. The method according to claim 1, wherein said nonvolatile memory has memory cells each stores more than one bit of data.
9.如权利要求1所述的方法,其中所述非易失性存储器具有各自存储作为被编程到电荷存储元件中的电荷量的数据的存储器单元。 9. The method according to claim 1, wherein said nonvolatile memory has a respective memory as the amount of charge programmed into the memory element of the memory cell data.
10.如权利要求9所述的方法,其中所述电荷存储元件是场效应晶体管的浮置栅极。 10. The method according to claim 9, wherein said charge storage element is a floating gate field effect transistor.
11.如权利要求9所述的方法,其中所述电荷存储元件是场效应晶体管中的介电层。 11. The method according to claim 9, wherein said charge storage element is a dielectric layer in a field effect transistor.
12.如权利要求1所述的方法,其中所述非易失性存储器具有NAND结构的存储器单元。 12. The method according to claim 1, wherein said nonvolatile memory has memory cells with a NAND structure.
13.如权利要求1所述的方法,其中所述非易失性存储器是快闪EEPROM。 13. The method according to claim 1, wherein said nonvolatile memory is a flash EEPROM.
14.如权利要求1所述的方法,其中所述非易失性存储器被实现在存储卡中。 14. The method according to claim 1, wherein said nonvolatile memory is implemented in a memory card.
15.如权利要求1所述的方法,其中所述非易失性存储器被嵌入在计算设备中。 15. The method according to claim 1, wherein said nonvolatile memory is embedded in a computing device.
16.如权利要求1-15任意一项所述的方法,其中所述存储器单元是被一起编程的一组存储器单元中的一个。 16. A method as claimed in any one of claims 1-15 any, wherein said memory cells are a group of memory cells are programmed with one.
17.一种非易失性存储器,包括: 存储器单元的阵列,其中所述存储器单元各自可被编程到阈值电压电平的范围之一;读/写电路,用于并行读取并编程一页存储器单元; 状态机,用于控制包括所述读/写电路的所述非易失性存储器的操作,所述状态机:为处在编程下的存储器单元提供预定函数,该函数产生编程电压值作为存储器单元被作为目标编程到的阈值电压电平的函数; 利用具有增加的幅值的编程电压,控制将存储器单元编程到所述目标阈值电压电平;以及在所述编程电压基本达到由在所述目标阈值电压电平处估计的预定函数所确定的值后,停止存储器单元的编程; 指定所述函数的检查点作为可由相应的检查点编程电压值编程的指定的检查点阈值电压电平; 通过交替地编程和验证直到检查点阈值电压电平被编程验证,确定相应的检查点编程电压 17. A nonvolatile memory, comprising: an array of memory cells, wherein each one may be programmed to a threshold voltage level range of the memory cell; read / write circuits for reading and programming a page in parallel memory cells; state machine for controlling comprises operating the read / write circuit of a nonvolatile memory, the state machine: providing a predetermined function in a memory cell under programming, this function generates the programming voltage was programmed to the target memory cell as a function of the threshold voltage level; using a programming voltage having a magnitude increase, controls the memory cells programmed to the target threshold voltage level; and substantially reaches the programming voltage in a after the value of a predetermined function of the target threshold voltage level is estimated at the determined stop programmed memory cells; checkpoint specifying the function as a designated checkpoint threshold voltage level of the corresponding checkpoint programming voltage value of the program may be ; by alternately programming and verifying until the checkpoint threshold voltage level is program-verified, determining the corresponding checkpoint programming voltage ;以及在预定函数被用于确定将存储器单元编程到目标阈值电压电平的编程电压值之前,当在检查点阈值电压电平处估计时,校准预定函数以产生检查点编程电压值。 ; And a means for determining the programmed memory cells to the programming voltage value before the target threshold voltage level, when the estimated value at the checkpoint threshold voltage level, a predetermined calibration function to generate the checkpoint programming voltage value of a predetermined function.
18.如权利要求17所述的非易失性存储器,其中所述具有增加的幅值的编程电压是一系列电压脉冲。 18. The nonvolatile memory according to claim 17, wherein said amplitude with increased programming voltage is series of voltage pulses.
19.如权利要求17所述的非易失性存储器,其中所述预定函数基本上是线性函数。 19. The nonvolatile memory according to claim 17, wherein the predetermined function is substantially a linear function.
20.如权利要求17所述的非易失性存储器,其中所述目标阈值电压电平小于来自检查点阈值电压电平的预定电压。 20. The nonvolatile memory according to claim 17, wherein said target threshold voltage level is less than the predetermined voltage from the checkpoint threshold voltage level.
21.如权利要求17所述的非易失性存储器,其中在阈值电压电平的范围内指定一个或多个检查点阈值电压电平。 The nonvolatile memory according to claim 21. 17, wherein the range of the threshold voltage level of the one or more designated checkpoint threshold voltage level.
22.如权利要求17所述的非易失性存储器,其中所述预定函数是线性的,并且由估计的斜率和检查点来定义。 The nonvolatile memory according to claim 22. 17, wherein said predetermined function is linear, and is defined by an estimated slope and a checkpoint.
23.如权利要求17所述的非易失性存储器,其中所述预定函数基本是线性的,并且由至少两个检查点来定义。 The nonvolatile memory according to claim 23. 17, wherein said predetermined function is substantially linear and is defined by at least two checkpoints.
24.如权利要求17所述的非易失性存储器,其中所述非易失性存储器具有各自存储多于一位的数据的存储器单元。 24. The nonvolatile memory according to claim 17, wherein said nonvolatile memory has memory cells each stores more than one bit of data.
25.如权利要求17所述的非易失性存储器,其中所述非易失性存储器具有各自存储作为被编程到电荷存储元件中的电荷量的数据的存储器单元。 25. The nonvolatile memory according to claim 17, wherein said nonvolatile memory has memory cells as the amount of charge in charge storage elements are programmed to their respective data storage.
26.如权利要求25所述的非易失性存储器,其中所述电荷存储元件是场效应晶体管的浮置栅极。 The nonvolatile memory according to claim 26. 25, wherein said charge storage element is a floating gate field effect transistor.
27.如权利要求25所述的非易失性存储器,其中所述电荷存储元件是场效应晶体管中的介电层。 The nonvolatile memory according to claim 27. 25, wherein said charge storage element is a dielectric layer in a field effect transistor.
28.如权利要求17所述的非易失性存储器,其中所述非易失性存储器具有NAND结构的存储器单元。 28. The nonvolatile memory according to claim 17, wherein said nonvolatile memory has memory cells with a NAND structure.
29.如权利要求17所述的非易失性存储器,其中所述非易失性存储器是快闪EEPROM。 29. The nonvolatile memory according to claim 17, wherein said nonvolatile memory is a flash EEPROM.
30.如权利要求17所述的非易失性存储器,其中所述非易失性存储器被实现在存储卡中。 30. The nonvolatile memory according to claim 17, wherein said nonvolatile memory is implemented in a memory card.
31.如权利要求17所述的非易失性存储器,其中所述非易失性存储器被嵌入在计算设备中。 31. The nonvolatile memory according to claim 17, wherein said nonvolatile memory is embedded in a computing device.
32.—种非易失性存储器,包括: 存储器单元的阵列,其中所述存储器单元各自可被编程到阈值电压电平的范围之一;用于为处在编程下的存储器单元提供预定函数的部件,该函数产生编程电压值作为存储器单元被作为目标编程到的阈值电压电平的函数; 用于利用具有增加的幅值的编程电压来控制将存储器单元编程到所述目标阈值电压电平的部件;以及用于在所述编程电压基本达到由在所述目标阈值电压电平处估计的预定函数所确定的值后,停止存储器单元的编程的部件; 用于指定所述函数的检查点作为可由相应的检查点编程电压值编程的指定的检查点阈值电压电平的部件; 用于通过交替地编程和验证直到检查点阈值电压电平被编程验证来确定相应的检查点编程电压值的部件;以及用于在预定函数被用于确定将存储器单元编程到目标阈值电压电平 32.- kinds of non-volatile memory, comprising: an array of memory cells, wherein each one of the memory cells may be programmed to a threshold voltage level range; means for providing a predetermined function in a memory cell under programming member, the threshold voltage level of the programming voltage function generating the target value is programmed into the memory cell as a function of; for utilizing a programming voltage having a magnitude to increase the control program the memory cell to the target threshold voltage level member; and a rear base for the programming voltage reaches a value estimated by a predetermined function in said target threshold voltage level is determined, the programmed memory cell is stopped; means for specifying the checkpoint as a function of from the corresponding designated checkpoint threshold voltage level member checkpoint programming voltage value programmed; means for determining a component corresponding checkpoint programming voltage value by alternately programming and verifying until the checkpoint threshold voltage level is program-verified ; and means for determining the predetermined function is used to program the memory cell to the target threshold voltage level 编程电压值之前,当在检查点阈值电压电平处估计时,校准预定函数以产生检查点编程电压值的部件。 Before programming a voltage value, when the estimated value at the checkpoint threshold voltage level, a predetermined calibration function to generate the checkpoint programming voltage value member.
33.如权利要求17-32中的任意一项所述的非易失性存储器,其中所述存储器单元是被一起编程的一组存储器单兀中的一个。 The nonvolatile memory according to any one of 17-32 as claimed in claim 33, wherein said memory cell is programmed with a set of memory unit Wu.
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Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007132453A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Ltd. Distortion estimation and cancellation in memory devices
WO2007132452A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Reducing programming error in memory devices
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
WO2007132456A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Ltd. Memory device with adaptive capacity
WO2007132457A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
WO2008026203A2 (en) 2006-08-27 2008-03-06 Anobit Technologies Estimation of non-linear distortion in memory devices
CN101601094B (en) 2006-10-30 2013-03-27 苹果公司 Reading memory cells using multiple thresholds
WO2008053472A2 (en) 2006-10-30 2008-05-08 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
US8151163B2 (en) 2006-12-03 2012-04-03 Anobit Technologies Ltd. Automatic defect management in memory devices
US7706182B2 (en) 2006-12-03 2010-04-27 Anobit Technologies Ltd. Adaptive programming of analog memory cells using statistical characteristics
US7900102B2 (en) 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US7751240B2 (en) 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
CN101715595A (en) 2007-03-12 2010-05-26 爱诺彼得技术有限责任公司 Adaptive estimation of memory cell read thresholds
US8001320B2 (en) 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
WO2008139441A2 (en) 2007-05-12 2008-11-20 Anobit Technologies Ltd. Memory device with internal signal processing unit
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
US8068360B2 (en) 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8527819B2 (en) 2007-10-19 2013-09-03 Apple Inc. Data storage in analog memory cell arrays having erase failures
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
WO2009063450A2 (en) 2007-11-13 2009-05-22 Anobit Technologies Optimized selection of memory units in multi-unit memory devices
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8085586B2 (en) 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US7924587B2 (en) 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
WO2009151894A1 (en) * 2008-06-12 2009-12-17 Sandisk Corporation Nonvolatile memory and method with index programming and reduced verify
US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US8498151B1 (en) 2008-08-05 2013-07-30 Apple Inc. Data storage in analog memory cells using modified pass voltages
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8713330B1 (en) 2008-10-30 2014-04-29 Apple Inc. Data scrambling in memory devices
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8223556B2 (en) * 2009-11-25 2012-07-17 Sandisk Technologies Inc. Programming non-volatile memory with a reduced number of verify operations
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8493781B1 (en) 2010-08-12 2013-07-23 Apple Inc. Interference mitigation using individual word line erasure operations
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
US8681562B2 (en) 2011-01-10 2014-03-25 Micron Technology, Inc. Memories and methods of programming memories
JP2014053060A (en) 2012-09-07 2014-03-20 Toshiba Corp Semiconductor storage device and control method of the same
JP2017168165A (en) * 2016-03-15 2017-09-21 東芝メモリ株式会社 Semiconductor storage device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729489A (en) 1995-12-14 1998-03-17 Intel Corporation Programming flash memory using predictive learning methods
EP0913832A1 (en) 1997-11-03 1999-05-06 SGS-THOMSON MICROELECTRONICS S.r.l. Method for multilevel programming of a nonvolatile memory, and a multilevel nonvolatile memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0453096A (en) * 1990-06-19 1992-02-20 Toshiba Corp Analog storage device
EP1074995B1 (en) * 1999-08-03 2005-10-26 SGS-THOMSON MICROELECTRONICS S.r.l. Method for programming multi-level non-volatile memories by controlling the gate voltage
US6504760B1 (en) * 2001-06-22 2003-01-07 Intel Corporation Charging a capacitance of a memory cell and charger
US7042766B1 (en) * 2004-07-22 2006-05-09 Spansion, Llc Method of programming a flash memory device using multilevel charge storage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729489A (en) 1995-12-14 1998-03-17 Intel Corporation Programming flash memory using predictive learning methods
EP0913832A1 (en) 1997-11-03 1999-05-06 SGS-THOMSON MICROELECTRONICS S.r.l. Method for multilevel programming of a nonvolatile memory, and a multilevel nonvolatile memory

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