KR20090117032A - Semiconductor plastic package and fabricating method therefore - Google Patents

Abstract

PURPOSE: A semiconductor plastic package and a fabricating method therefore are provided to excellent connection reliability since bending and twist between substrates contacting with a semiconductor chip. CONSTITUTION: In a semiconductor plastic package and a fabricating method therefore, a release sheet(140) is laminated on an area for mounting a semiconductor chip in a core substrate(110). A build-up insulating layer(130) is laminated on the core substrate. An opening is formed on a build up insulating layer by removing the build up insulating layer corresponding to a mold-release sheet so that they are separated from each other. A semiconductor chip is built in the opening and is connected with the core substrate through a flip chip type. A coefficient of thermal expansion of the core substrate is -10 or 9 ppm / °C. The core substrate is made of one of a glass fiber or a metal material.

Description

Semiconductor plastic package and its manufacturing method {SEMICONDUCTOR PLASTIC PACKAGE AND FABRICATING METHOD THEREFORE}

The present invention relates to a semiconductor plastic package and a method of manufacturing the same.

 Recently, electronic devices are becoming smaller, thinner, and lighter, and the accompanying connection method of semiconductor chips has been changed from wire-bonding to flip chip-bonding. . As the semiconductor chip mounting method is changed to a flip chip bonding method, high reliability and high density are also required for multilayer printed circuit boards on which the semiconductor chip is mounted and connected.

In the conventional multilayer printed circuit board, glass fiber woven fabric is used as the reinforcing material, and E-glass fiber is generally used as the glass fiber component.

The glass fiber woven fabric is produced by impregnating and drying the thermosetting resin composition in a B-stage state, and then processing it into a copper clad laminate. This copper foil laminated board is used to fabricate an inner layer core printed circuit board. The B-stage thermosetting resin composition sheet for build-up is disposed on both sides of the core printed circuit board, and laminated, and then fabricated into a multilayer printed circuit board.

In the structure of the multilayer printed circuit board manufactured as described above, a resin composition for build-up having a large coefficient of thermal expansion (generally, a coefficient of thermal expansion in the longitudinal and transverse directions of 18 to 100 ppm / 占 폚) is disposed in many layers, Each layer includes a copper (Cu) layer with a thermal expansion coefficient of 17 ppm / ° C. In the outermost layer, a layer of solder resist (typically 50 to 150 ppm / ° C) having a higher thermal expansion coefficient is formed. The coefficient of thermal expansion in the longitudinal and transverse directions of the entire multilayer printed circuit board that can be finally produced is about 10 to 30 ppm / ° C.

On the other hand, when a wholly aromatic polyamide fiber fabric is used as the reinforcing base material, the coefficient of thermal expansion in the longitudinal and horizontal directions of the double-sided printed circuit board serving as the inner core material is 10 ppm / 占 폚 or less. However, this also includes a resin composition for build-up and a copper layer between layers, and when a high multilayer printed circuit board is manufactured, a thermal expansion coefficient is increased to produce a high multilayer printed circuit board having a thermal expansion coefficient of more than 10 ppm / ° C. .

However, due to the difference in thermal expansion coefficient between the semiconductor chip and the multilayer printed circuit board, the high-layer multilayer printed circuit board manufactured by using the wholly aromatic polyaramid fiber is made of glass fiber nonwoven fabric having high rigidity throughout the printed circuit board. Since the rigidity is smaller than that of the fabricated printed circuit board, it is easy to bend or warp, and since the reinforcing substrate and the resin composition are organic materials, the thermal expansion coefficient in the thickness direction of the multilayer printed circuit board is large and reliability is also generated.

On the other hand, even when E-glass fiber cloth and wholly aromatic polyaramid fiber cloth are used in combination, the entire printed circuit board is also affected by the influence of the resin for build-up and the copper layer having a large thermal expansion coefficient of 17 ppm / 占 폚. It was difficult to produce a printed circuit board having a thermal expansion coefficient of 10 ppm / 占 폚 or less and further 9 ppm / 占 폚 or less in the longitudinal and horizontal directions.

When the semiconductor chip is mounted and connected to the multilayer printed circuit board, an underfill resin is used to absorb the stress generated by the expansion and contraction during heating and cooling, but the coefficient of thermal expansion is 2 to 3 ppm. When a semiconductor chip having a temperature of / deg. C was mounted and connected, a warped or splashed state occurred due to the difference in each thermal expansion coefficient. In addition, when a semiconductor chip is mounted and connected without using an underfill resin to perform a reliability test such as a temperature cycle test, in particular, when a semiconductor chip having a thermal expansion coefficient of about 3 ppm / ° C is mounted and connected using a lead-free solder, Particularly, defects such as cracking and peeling between the semiconductor chip and the solder have occurred in the lead-free solder and the semiconductor chip.

On the other hand, multilayered printed circuit boards are fabricated by using a conductive carbon fiber woven fabric and a metal plate such as copper-invar as a core material in the center, and coated with a thermosetting resin composition to ensure insulation therein. Similarly, due to the influence of the resin composition for build-up and the copper layer having a large thermal expansion coefficient of 17 ppm / ° C., the thermal expansion coefficient of a high multilayer printed circuit board is 10 ppm / ° C. or more. In addition, in the case of such a multilayer printed circuit board, the material price is high, processing is difficult, and reliability and economical efficiency are caused. In addition, when the underfill resin is used, it is not economical because the semiconductor plastic package itself is not reworked when a failure occurs in the semiconductor chip or the multilayer printed circuit board.

SUMMARY OF THE INVENTION The present invention provides a semiconductor plastic package which is excellent in connection reliability between a semiconductor chip and a circuit board without bending or warping between the semiconductor chip and the substrate connected thereto, and which can be repaired without using an underfill resin, and a method of manufacturing the same.

According to an aspect of the invention, providing a core substrate, laminating a release sheet in the area where the semiconductor chip is to be mounted in the core substrate, laminating a build-up insulating layer on the core substrate, build corresponding to the release sheet A method of manufacturing a semiconductor plastic package includes forming an opening in a buildup insulating layer to be spaced apart from each other by removing the up insulating layer, and embedding a semiconductor chip in the opening to connect the core substrate to a flip chip method.

The thermal expansion coefficient of the core substrate may be -10 to 9 ppm / ℃, the core substrate may comprise any one of the invar (Invar) or the Inba, and includes any of the wholly aromatic polyamide non-woven or woven substrate It can be done by.

In addition, the core substrate may be made of T (S) glass fiber or a metal material, and may include a liquid crystal polyester resin having a melting point of 270 ° C. or higher. The liquid crystal polyester resin may be formed of glass fiber or wholly aromatic polyamide. Fiber, polyoxybenzazole fiber may be made of any one selected from the group consisting of.

In addition, the core substrate may include a carbon fiber woven substrate.

On the other hand, the thermal expansion coefficient of the build-up insulating layer may be 10 to 25 ppm / ℃.

In addition, the release sheet and the buildup insulating layer may be stacked on both sides of the core substrate.

According to another aspect of the present invention, a semiconductor package including a core substrate, openings formed to be spaced apart from each other, a build-up insulating layer stacked on the core substrate, and a semiconductor chip embedded in the opening and connected and connected to the core substrate in a flip chip manner. Is provided.

The thermal expansion coefficient of the core substrate may be -10 to 9 ppm / ℃, the core substrate may comprise any one of the invar (Invar) or the Inba, and includes any of the wholly aromatic polyamide non-woven or woven substrate It can be done by.

In addition, the core substrate may be made of T (S) glass fiber or a metal material, and may include a liquid crystal polyester resin having a melting point of 270 ° C. or higher. The liquid crystal polyester resin may be formed of glass fiber or wholly aromatic polyamide. Fiber, polyoxybenzazole fibers can be made of any one selected from the group consisting of.

In addition, the core substrate may include a carbon fiber woven substrate.

On the other hand, the thermal expansion coefficient of the build-up insulating layer may be 10 to 25 ppm / ℃.

In addition, the release sheet and the buildup insulating layer may be stacked on both sides of the core substrate.

The semiconductor plastic package and the manufacturing method thereof according to the present invention have excellent connection reliability because there is no warpage or warpage between the semiconductor chip and the substrate to be connected. It is possible to prevent cracking or peeling of the chip and rework is possible when a defect occurs because the underfill resin is not used.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a flowchart illustrating a method of manufacturing a semiconductor plastic package according to an embodiment of the present invention, and FIGS. 2 to 5 are flowcharts illustrating a method of manufacturing a core substrate according to an embodiment of the present invention, and FIG. 8 is a cross-sectional view illustrating a state in which a build-up insulating layer is stacked on both surfaces of a core substrate in a method of manufacturing a semiconductor plastic package according to an embodiment of the present disclosure, FIG. 7 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, and FIG. 8. Is a perspective view of a semiconductor package according to an embodiment of the present invention.

2 to 8, the semiconductor package 100, the core substrate 110, the core substrate 111, the resin composition 112, the copper foil 113, the insulating layers 114 and 122, the copper conductor 116, Circuit 117, Land 118, Through Hole 119, Via 120, Solder Resist 121, Build-Up Insulation Layer 130, Release Sheet 140, Opening 150, Semiconductor Chip 160, a semiconductor chip connecting material 161 is shown.

In the method of manufacturing a semiconductor plastic package according to the present embodiment, a core substrate is provided, a release sheet is laminated on an area where a semiconductor chip is to be mounted on the core substrate, and then a build-up insulating layer is laminated on the core substrate and corresponds to the release sheet. After removing the build-up insulating layer to form an opening in the build-up insulating layer so as to be spaced apart from each other, a semiconductor chip is embedded in the opening and connected to the core substrate in a flip chip method.

To this end, first, as shown in FIGS. 2 to 5, the core substrate 110 is provided (S10). The core substrate 110 is a printed circuit board having a low coefficient of thermal expansion having a coefficient of thermal expansion in the range of -10 to 9 ppm / ° C. The thermal expansion coefficient of the core substrate is preferably -1 to 5 ppm / 占 폚, and more preferably the thermal expansion coefficient of about 1 to 55 ppm / 占 폚 semiconductor chip. At this time, if the coefficient of thermal expansion is out of the above range it may cause a connection problem of the substrate may cause cracks.

The method of forming the core substrate 110 is as follows. First, as shown in FIG. 2, the core substrate 111 is provided, the core substrate 111 is drilled to selectively form through holes, and the resin composition 112 is filled in the through holes. Next, as shown in FIG. 3, the copper foil 113 having the insulating substrate adhered to both surfaces of the core substrate 111 is attached.

Next, as shown in FIG. 4, the copper foil 113 of the outer layer is etched, and the resin composition 112 filled in the through holes is drilled to selectively form the electrically conductive through holes 119. A circuit is formed in the copper foil 113 and the electrically conductive through hole 119 of the outer layer, and the electrically conductive through hole 119 is plated to transmit an electric signal.

Next, as shown in FIG. 5, the insulating layer and the copper foil are laminated and formed on the core substrate 111, and the via 120 is selectively formed by drilling and plating the insulating layer and the copper foil. A circuit 117 is formed on the copper foil and the via 120, and the via 120 is plated to transmit an electrical signal, thereby forming a core substrate having two or more layers.

The core substrate 110 may be formed of a resin in which one or more of a general thermosetting resin, a thermoplastic resin, a UV curable resin, or an unsaturated group-containing resin is mixed.

Examples of the thermosetting resin used for the core substrate 110 include epoxy resins, cyanate ester resins, bismaleimide resins, maleimide cyanate ester resins, benzocyclobutene resins, polyimide resins, and cardo. ), A functional group-containing polyphenylene ether resin, or a phenol resin, or a combination of two or more thereof.

In order to prevent migration between penetrating holes or circuits becoming narrower, cyanate ester resins and maleimide cyanate ester resins can be suitably used. Moreover, the said well-known resin which is further cancelled or flame retarded by phosphorus can also be used. Although the thermosetting resin of this invention hardens | cures by heating itself, since hardening rate is slow and productivity is inferior, it is used suitably by adding an appropriate amount of a hardening | curing agent and a thermosetting catalyst to the thermosetting resin used.

In such a thermosetting resin, what mix | blended various additives known as a resin composition can be used generally. For example, thermosetting resins, thermoplastic resins, other resins, known organic inorganic fillers, dyes, pigments, thickeners, lubricants, antifoaming agents, dispersants, leveling agents, gloss agents, thixoproic agents, etc. Various additives are added and used in appropriate amounts depending on the purpose and use. It is also possible to use a flame retardant by adding an appropriate amount of a known substance such as phosphorus, flame retarded to bromine, or a form containing no halogen.

In order to reduce the coefficient of thermal expansion, inorganic fillers such as spherical, flat plate, amorphous silica, alumina, talc, wollastonite and other low thermal expansion coefficients are added to the resin and 10 to 90% by weight to be uniformly dispersed.

Although the inorganic filler can be used after the surface of the filler is untreated, it is preferable to treat it in advance with a silane coupling agent, a titanium coupling agent, etc. from the point of improving moisture absorption, heat resistance, etc., and can also use a nano filler. have.

As the thermoplastic resin used very suitably in the present invention, generally known ones can be used. Specifically, a liquid crystalline polyester resin, a polyurethane resin, a polyamide-imide resin, a polyphenylene ether resin, etc. are mentioned, These are used 1 type or in combination or 2 or more types.

However, since the core substrate 110 requires a high temperature reflow treatment when mounting components, the core substrate 110 has a melting point at which the core substrate 110 does not generate defects at a reflow temperature. The thermoplastic resin whose melting | fusing point is 270 degreeC or more can be used. It is possible to add and use an appropriate amount of the above-mentioned various additives also in such a thermoplastic resin. These can also be used in combination with the said thermosetting resin.

In addition to the said thermosetting resin and a thermoplastic resin, UV curable resin, radical curable resin, etc. can also be used 1 type or in combination of 2 or more types. Furthermore, it can use combining said thermosetting resin and a thermoplastic resin. Even in this case, the above-mentioned various additives such as a photopolymerization initiator and a radical polymerization initiator, a curing agent, and a catalyst that promote crosslinking can be used in combination.

However, in the present invention, a thermosetting resin and a heat resistant thermoplastic resin can be suitably used in view of the reliability of the printed circuit board which can be produced.

In addition, the reinforcing base material used for the core substrate 110 may use a nonwoven fabric, a woven fabric, or a metal material of inorganic fibers or organic fibers.

As the inorganic fiber, for example, T-glass fiber, S-glass fiber, ceramic fiber or the like having a low coefficient of thermal expansion may be used. In addition, the organic fibers may have a low coefficient of thermal expansion and non-woven or woven fabrics such as heat-resistant poly-oxibenzazol fibers, wholly aromatic polyaramid fibers, liquid crystal polyester fibers, and carbon fibers.

In addition, a film having a low coefficient of thermal expansion such as a wholly aromatic polyaramid film, a polyoxybenzazole film, a liquid crystal polyester film, a polyimide film, or the like may be used as the reinforcing base material. Such reinforcement base material can perform a well-known process on the surface of a reinforcement base material, in order to improve the adhesive force with resin. For example, glass fibers may be treated with a silane coupling agent, and organic fibers such as film materials may be selectively subjected to plasma treatment, corona treatment, various chemical treatments, blast treatment, and the like.

In the case of a film material, the method of affixing an adhesive agent on both surfaces of this film, and bonding a copper foil, and the copper foil sheet which directly bonded the copper foil by a well-known method can be used. From the viewpoint of reducing the coefficient of thermal expansion, the latter is preferable.

In addition, a metal material having a low thermal expansion coefficient is also used. For example, a metal material of low thermal expansion coefficient, such as invar or copper-invar, may be used. The core substrate 110, which is the low thermal expansion coefficient of the present invention, is a printed circuit board composed of two or more metal circuit layers, but in order to mount the semiconductor chip 160, it is important that the thermal expansion coefficient does not differ significantly from the semiconductor chip.

In order to produce a multilayer core substrate having two or more layers, it is preferable to use a metal material for the core substrate to lower the number of layers. In this case, the coefficient of thermal expansion of the entire core substrate using the metal material is -10 to 9 ppm / 占 폚, preferably -10 to 7.5 ppm / 占 폚. More preferably, it is 1-5 ppm / degrees C. More preferably, the coefficient of thermal expansion is about the same as that of the semiconductor chip. It is also preferable to use a printed circuit board or ceramic printed circuit board using a glass plate having a low thermal expansion coefficient.

Even if the core substrate 110 is made of a printed circuit board having a low thermal expansion coefficient, when the build-up insulating layer 130 having a relatively large thermal expansion coefficient of 10 to 25 ppm / ° C laminated on at least one side of the core substrate 110 is used, Since a force that grows in the longitudinal and horizontal directions is generated at the time of heating, the buildup insulating layer 130 is not disposed in the region and the opening 150 for mounting and connecting the semiconductor chip 160. During heating, the core substrate 110, which is a low thermal expansion coefficient, expands and contracts along the large stretch of the build-up insulating layer 130 having a relatively large thermal expansion coefficient stacked to be spaced apart from each other.

This value is larger than the coefficient of thermal expansion when only the core substrate 110 having a low thermal expansion coefficient used therein is heated, but the semiconductor chip 160 and the core substrate 110 having a low thermal expansion coefficient are mounted and connected to the chip. Since is bonded to the electrically conductive material, when heated, the stretching is slightly reduced due to the stress relaxation of the electrically conductive material. As a result, the core substrate 110 on which the semiconductor chip 160 is mounted and connected cannot be expanded and contracted so much, and defects such as cracking and peeling of the semiconductor chip 160 and the connection member 161 are less likely to occur.

In addition, since the surfaces of the build-up insulating layer 130 and the semiconductor chip 160 have the same shape, warpage and distortion are hardly generated. In the case where the thickness of the core substrate 110, which is a low thermal expansion coefficient to which the semiconductor chip 160 is mounted and connected, is thin, there is a risk that the semiconductor chip 160 may be destroyed by bending, the core substrate 110 having the low thermal expansion coefficient. I can thicken it. When the film base material is used as the reinforcing base material, since the film base material is flexible, the semiconductor chip 160 may not be broken.

The build-up insulating layer 130 may have a size equal to or smaller than that of the core substrate 110. However, the build-up insulating layers 130 laminated on the surface and adhered to each other are bonded to the same position on the surface by using insulating layers having the same size and the same thermal expansion coefficient in order to prevent bending or warping. The build-up insulating layer 130 has a larger thermal expansion coefficient than that of the core substrate, which is a low thermal expansion coefficient for mounting and connecting the semiconductor chip 160, so that the overall price can be lowered.

Although the core board 110 which is the low thermal expansion coefficient of this invention differs in the manufacturing method of a core board according to the material used, all can use a well-known method. In addition, the material used for the manufacture of the core substrate, which has a low coefficient of thermal expansion, has a coefficient of thermal expansion of -10 to 9 ppm / ° C, preferably -1 to 5 ppm / ° C, and more preferably, a substrate having a low coefficient of thermal expansion substantially the same as that of a semiconductor chip. Choose the ingredients you can.

There is no particular limitation on the method for producing a core substrate having a low thermal expansion coefficient. The manufacturing method is as follows, for example. When using a wholly aromatic polyaramid fiber woven or nonwoven fabric of para or meta form, the wholly aromatic polyaramid fiber is impregnated with a thermosetting resin composition and dried to produce a resin in a B-stage state, and copper foil is provided on both sides. After disposing, they are laminated and molded to form a double-sided copper foil laminated plate. Through-holes are formed in the double-sided copper-clad laminates using a laser, followed by desmearing, copper plating, and circuit formation to form a core substrate.

Copper-clad laminates using T-glass fiber woven fabric or S-glass fiber woven fabric also produce printed circuit boards in this manner. In this case, however, a mechanical drill may be used when machining the through hole. The coefficient of thermal expansion of this double-sided copper clad laminate can be changed by the type and amount of inorganic filler to be blended in the resin. Increasing the compounding amount of the inorganic filler decreases the coefficient of thermal expansion of the resin, so that an appropriate amount is used in combination with the resin. Therefore, the amount of the inorganic filler to be blended is such that the thermal expansion coefficient of the double-sided copper clad laminate is -10 to 9 ppm / ° C or less, preferably -10 to 7.5 ppm / ° C, and more preferably -1 to 5 ppm / ° C. The degree to which a printed circuit board having a coefficient can be manufactured should be blended.

A method of manufacturing a core substrate when using a carbon fiber woven fabric as a reinforcing substrate is as follows. The carbon fiber is impregnated with a thermosetting resin composition and dried to prepare an insulating substrate having the thermosetting resin in a B-stage state. A double-sided copper-clad laminate is produced by arranging and laminating copper foils on both sides of the insulating base. Clear through-holes are machined into the copper clad laminate. This clearance through hole is machined larger than the electrically conductive through hole. The clearance through hole is filled with a resin composition and cured, and then the resin composition that comes out of the surface is polished to make the surface flat. Afterwards, the conductive through-hole is processed so as not to contact the carbon fiber woven fabric in the center of the resin composition again using a laser. Electroconductive through-holes are subjected to desmearing and copper plating to form a circuit on an insulating substrate to produce a core substrate having a low coefficient of thermal expansion.

For example, the method of manufacturing a core substrate when a glass sheet is used as a reinforcing substrate is as follows. The glass plate is formed of an electrically conductive through hole by a known method using a laser or chemicals such as hydrofluoric acid. On the surface of the glass plate, a thin copper layer is formed by sputtering or the like, electrolytic copper plating is performed to form a high copper plating, and a circuit is formed to produce a core substrate having a low thermal expansion coefficient.

For example, a method of manufacturing a core substrate in the case where an invar or a copper inbar is used as a reinforcing substrate is as follows. The clearance through hole is machined using a laser. This clearance through hole is machined larger than the electrically conductive through hole. Copper is thinly plated on the entire surface of the invar or the copper invar using a known method such as sputtering. The clearance through hole is filled with a resin composition and then cured. The copper foil with a thin insulating base material is arranged above and below the Invar or the Copperbar, and then laminated and molded. The thermosetting resin composition layer of a thin B-stage state is further arrange | positioned on this surface, copper foil is arrange | positioned on both surfaces of a resin composition, it laminates and shape | molds. Then, an electrically conducting through hole smaller than the clearance through hole is processed while being careful not to contact the center of the resin composition with the invar or the invar using a laser again. Thereafter, desmearing, electroless copper plating, and electrolytic copper plating are performed, and a circuit is formed on an insulating substrate to produce a core substrate having a low thermal expansion coefficient.

When the resin composition is directly adhered to the surface of the invar or the copper invar, irregularities may be applied to the surface of the invar or the copper invar using chemicals, or a known chemical treatment may be performed to improve adhesion to the resin composition. Can be. However, the manufacturing method of the core substrate which is each low thermal expansion coefficient is not limited to this, It can manufacture by a well-known manufacturing method.

6 is a cross-sectional view illustrating a state in which a buildup insulating layer is stacked on both surfaces of a core substrate in a method of manufacturing a semiconductor plastic package according to an embodiment of the present invention.

Referring to FIG. 6, the build-up insulating layer 130, which is a printed circuit board having a relatively large thermal expansion coefficient on the outside bonded to the low thermal expansion core substrate 110, may include a printed circuit board having a larger thermal expansion coefficient than that of the core substrate 110. use.

The buildup insulating layer 130 refers to a printed circuit board having a relatively large thermal expansion coefficient having a thermal expansion coefficient of 10 to 25 ppm / ° C in the vertical and horizontal directions. The material used for the build-up insulating layer 130 is not particularly limited, and insulating materials such as various resins and various additives and reinforcing base materials can be used. However, in order to lower the price of the entire multilayer printed circuit board, it is desirable to form a buildup insulating layer using an E-glass fiber woven fabric as a reinforcing substrate. The number of layers of the build-up insulating layer is made of two or more printed circuit boards depending on the use and design thereof.

This printed circuit board is made by forming a circuit on one side, leaving copper foil on one side. Then, after surface-treating on the copper foil of a board | substrate, adhesive sheets, such as a prepreg, are arrange | positioned, laminated | stacked and shape | molded, and it adhere | attaches with the core board which is a low coefficient of thermal expansion. Next, through holes are formed to electrically connect the core substrate 110, which is a low thermal expansion coefficient, and the build-up insulating layer 130, to fabricate a multilayer printed circuit board.

In addition, a multilayer printed circuit board may be manufactured by the following method. First, the core substrate 110 having a low thermal expansion coefficient is manufactured, and the solder resist 121 is formed to a corner of the core substrate 110 so as to be spaced apart from each other in a slightly wider range than the semiconductor chip 160 is mounted and connected. Form. The region where the semiconductor chip 160 is mounted and connected is formed by opening a land, and then subjected to nickel plating or gold plating.

As shown in FIG. 6, the release sheet 140 is stacked on the core substrate 110 in the region where the semiconductor chip 160 is to be mounted (S20), and the buildup insulating layer 130 is disposed on the core substrate 110. Lamination (S30). In this case, the release sheet 140 and the build-up insulating layer 130 may be stacked on both surfaces of the core substrate 110.

Next, the opening 150 is formed in the build-up insulating layer 130 to be spaced apart from each other by removing the build-up insulating layer 130 corresponding to the release sheet 140.

That is, the release sheet 140 is arrange | positioned in the range which formed the soldering resist 121, the insulating layer 122, such as a prepreg, is laminated | stacked on it, and copper foil is arrange | positioned and laminated | stacked, blind via hole processing, and desmear. The process, copper plating, circuit formation, chemical treatment, and lamination can be repeated to produce a multilayer printed circuit board.

In the range in which the release sheets 140 are stacked, the openings 150 are formed to be spaced apart from each other in a region in which the semiconductor chip 160 is mounted and connected by using a laser, router, or other cutting method. The opening 150 is formed on both sides of the printed circuit board. At this time, the opening 150 is cut so that the same area can be opened.

When the release sheet 140 is stacked, the build-up insulating layer 130 may be easily removed from the core substrate 110, so that the semiconductor chip 160 may be more easily mounted. In addition, when a problem occurs in the region where the semiconductor chip 160 is to be mounted in the build-up insulating layer 130, it may be easily removed. In this case, the release sheet 140 may be a Teflon film.

The warpage caused by the area difference of the build-up insulation layer 130 having a relatively large thermal expansion coefficient remaining after removal is not a problem if it occurs within a predetermined range, but it is no problem that the same area of the build-up insulation layer to be removed is equal to the warpage or distortion. It is preferable from a viewpoint. In addition, the thickness of the core substrate, which is a low thermal expansion coefficient, is also not limited. However, if the core substrate is too thick, the semiconductor chip 160 may crack or be connected to the semiconductor chip connection material 161 due to stress such as curling or the like. Suitably, the thickness of the core substrate is at least 0.4 mm.

Next, as shown in FIGS. 7 and 8, the semiconductor chip 160 is embedded in the opening 150 to be connected to the core substrate 110 in a flip chip manner (S50).

The thickness of the build-up insulating layer 130 is not particularly limited, but when the semiconductor chip 160 is mounted and connected, the height of the semiconductor chip 160 and the connecting material is equal to the height after the adhesion of the build-up insulating layer 130. Or lower.

By doing so, a defect such as the semiconductor chip 160 being broken under pressure in the longitudinal and transverse directions of at least two surfaces may not occur. Furthermore, since the semiconductor chip 160 is mounted and connected on a core substrate having a low thermal expansion coefficient, problems such as cracking and breakage of the semiconductor chip 160 and the connecting member can hardly occur. In addition, since the underfill resin does not have to be used, when there is a defect in the semiconductor chip 160, rework can be performed and the economy is excellent.

The semiconductor chip 160 is mounted and connected to a printed circuit board having a low thermal expansion coefficient therein by a known method such as gold bumps, lead-free solders, and general solders.

When manufacturing the build-up insulating layer 130 having a relatively large coefficient of thermal expansion, it is not necessary to use only materials of the same resin composition described above. Examples of the material that can be used are as follows. As a core board for inner layer, the copper clad laminated board manufactured by impregnating an epoxy resin composition in the reinforcement base material of E-glass fiber woven fabric is used, and it is used for cyanate ester resin composition of B-stage state which does not contain a reinforcement base material for lamination. The sheet | seat with copper foil, the unsaturated-group-containing polyphenylene ether resin composition sheet of B-stage state, the resin composition sheet of B-stage state of various base materials, etc. can be selected suitably.

Of course, the multilayered printed circuit board of the special structure of the present invention is a printed circuit board suitable for mounting and connecting the semiconductor chip 160, but wire bonding connection is also possible.

Hereinafter, the present invention will be described in detail with Examples and Comparative Examples. In addition, "part" shows a weight part unless there is particular notice.

Preparation Example 1 Preparation of Prepreg for Printed Circuit Boards with Low Thermal Expansion Coefficient and Laminated B-Stage Resin Composition Sheet (Prepreg) Used in Examples

550 parts by weight of 2,2-bis (4-cyanatephenyl) propane monomer was dissolved at 160 ° C and reacted for 4.5 hours while stirring to obtain a mixture of monomer and prepolymer. This is dissolved in methyl ethyl ketone, and 100 parts by weight of bisphenol A type epoxy resin (brand name: Epicoat 1001, Japan epoxy resin Co., Ltd.), phenol novolak type epoxy resin (brand name: DEN-431, Dow 150 parts by weight of Chemical <Co., Ltd.), 200 parts by weight of cresol novolac-type epoxy resin (brand name: ESCN-220F, Sumitomo Chemical Co., Ltd.) are incorporated, and 0.2 parts by weight of octylic acid zinc methyl ketone as a curing catalyst. It was dissolved in, stirred and mixed to prepare a varnish.

Varnish A was prepared by adding 1000 parts by weight of spherical silica (average particle diameter; 0.9 μm) as an inorganic filler and 10 parts by weight of an epoxy silane coupling agent to the varnish.

On the other hand, varnish A was impregnated and dried in a carbon fiber woven fabric having a thickness of 200 μm to prepare a prepreg B having a gelation time of 105 seconds (temperature: 170 ° C.) and a thickness of 205 μm. Further, varnish A was impregnated and dried to aramid fiber woven fabric having a thickness of 200 μm to prepare a prepreg C having a gelation time (temperature: 170 ° C.) for 110 seconds and a thickness of 207 μm. Varnish A was impregnated and dried to 95 micrometers thick T (S) -glass fiber woven fabric, and the prepreg D of 100 micrometers in thickness was produced for 102 second of gelation times. Varnish A was impregnated and dried to 100-um thick E-glass fiber woven fabric as a B-stage resin composition sheet for lamination, and prepreg E with a gelation time of 116 seconds and a thickness of 125 um was produced. In addition, varnish A was impregnated and dried to a 30-um thick E-glass fiber woven fabric to prepare a prepreg F having a gelation time of 122 seconds and a thickness of 55 um. In addition, varnish A was impregnated and dried to T (S) -glass fiber woven fabric of 30 micrometers in thickness, and the prepreg G of thickness of 55 micrometers and 55 micrometers was produced.

Example 1 Fabrication of Low Thermal Expansion Semiconductor Plastic Package Using Copper Bar

A clearance through hole with a hole diameter of 200 μm is machined into a 0.4 mm thick copper bar (Cu thickness / Invar thickness / Cu thickness = 2um / 396um / 2um) with a UV-YAG laser. After attaching a copper layer having a thickness of 722 kPa (Om Strong) to the entire surface of the copper bar plate by sputtering, the inside of the formed clearance through hole was filled with a resin composition for hole filling (trade name; FP-R200, manufactured by Asahi Chemical Research Institute, Tg; 179 ° C.) is filled with the resin composition for hole filling only in the through-hole portion by a screen printing method. After removing the resin composition for hole filling which flowed out of the clearance through-hole, after hardening at 140 degreeC for 50 minutes and 155 degreeC for 1 hour, black copper oxide treatment is applied to the surface. Copper foil (brand name; CRS-501, copper foil thickness 12um, product made by Mitsubishi Gas Chemical Co., Ltd.) to which the thermosetting resin composition of the 10-micrometer-thick B-stage state adhere | attached on both surfaces of this copper-in-bar plate, 190 degreeC, 20 kgf / After lamination | stacking and shaping | molding in the vacuum state of cm <2> and 2 mmHg for 90 minutes, the copper foil of this copper foil surface was etched to 1 micrometer. In the center of the clearance through-hole filled with the hole filling resin composition, a CO2 laser was used to drill an electric conduction through-hole of 100um in diameter, and 1.0um of electroless copper plating and 15um of electrolytic copper plating were attached to the circuit to make a land for connection. It was. After carrying out CZ treatment of Mec Co., one sheet of prepreg G was placed on this surface, and laminated and molded in the same manner, and the inside of the electrically conductive through hole was filled with a resin composition to prepare a four-layer copper-clad laminate. This was irradiated with a UV-YAG laser to form a blind via hole having a diameter of 50 μm, and the inside of the hole was filled with copper plating. After the circuits and lands are formed on the surface again and subjected to CZ treatment, one side of the semiconductor chip is mounted to one side by 3 mm larger than the width to which the semiconductor chip is mounted and connected, and the other two sides are soldered to the edges of the printed circuit board. Trade name; PSR4000AUS308, manufactured by Daiyo Ink Co., Ltd.). The solder resist was exposed and developed to open to the extent where the bumps of the semiconductor chip were mounted and connected, and the same area was also covered with the solder resist. Thereafter, nickel plating and gold plating were performed. The distance between the lands was 425um, the land diameter was 150um, and the land passage was 100um diameter. The coefficient of thermal expansion of the portion where this semiconductor chip was mounted and connected was 3.9 ppm / 占 폚 in the longitudinal and horizontal directions. Teflon tape having a thickness of 10 μm was attached to the four corners a little smaller than the width direction coated with the solder resist and slightly smaller than the other two directions or the work size, and one prepreg F was placed thereon. Electrolytic copper foil with a thickness of 12 micrometers was arrange | positioned at the both sides, and it laminated | stacked and shape | molded for 90 minutes in the vacuum of 190 degreeC, 25 kgf / cm <2>, and 2 mmHg, and produced 6 layers of double-sided copper foil laminated sheets. After the copper layer on the surface of the copper foil was etched to 1.2 um, blind via holes having a diameter of 50 um were formed on both sides with a UV-YAG laser outside the range covered with the solder resist. After the formed via hole was desmeared, the inside of the blind via hole was filled with copper plating. Through-holes were coated with copper plating on the hole walls, and then a circuit was made on the surface. This was repeated to form four layers of circuit layers on only one side, and finally, the through hole penetrating the front and back was punched out with a hole diameter of 200 um. The through-hole was subjected to a desmear treatment, and the inside of the blind via hole was filled with copper plating. At the same time, the through-holes were copper-plated on the wall surface of the hole distribution, to produce a total of 12 layers of printed circuit boards. Using the liquid thermosetting type solder resist on the surface of the printed circuit board, the solder resist was formed to a thickness of 15 um except for the range where the core substrate surface of the low thermal expansion coefficient was covered with the above solder resist, and then the thermosetting was performed. The multilayer printed circuit board H was manufactured by the following procedure. The part to which the semiconductor chip of this multilayer printed circuit board H is mounted, connected, and the Teflon tape previously attached so as to be spaced apart from each other were processed by UV-YAG laser from above, and punched. The coefficient of thermal expansion in the longitudinal and horizontal directions of the four-layer printed circuit board formed by stacking on one side of the core substrate as the low thermal expansion coefficient was 23 ppm / 占 폚 in the longitudinal direction and 24 ppm / 占 폚 in the horizontal direction. The semiconductor chip was mounted and connected by the reflow method using the lead-free solder (maximum reflow temperature: 260 degreeC) to the land of this open part, and the semiconductor plastic package I was produced. The evaluation results are shown in Table 1.

Example 2 Fabrication of Low Thermal Expansion Semiconductor Plastic Package Using Carbon Fiber Fabrics

Using two pieces of prepreg B made of a carbon fiber woven fabric, an electrolytic copper foil having a thickness of 12 μm was placed on both sides of the prepreg, and laminated and molded at 190 ° C., 20 kgf / cm 2, and vacuum of 2 mmHg for 90 minutes to 0.4 mm in thickness. The double-sided copper foil laminated plate of was produced. The copper foil of this double-sided copper-clad laminated board was etched to 5 micrometer thickness, and the clearance drilled hole of 200 micrometers of hole diameters was formed by the CNC drill. After filling and curing the resin composition for hole filling used in Example 1 inside this clearance through hole, the resin composition which flowed out of the through hole was polished flat, being careful not to grow a base material. After etching copper foil of both surfaces of this copper foil laminated board to 1.5-2.2 micrometer thickness, the electrically conductive through-hole of diameter 100um was processed into the center of this hole filling resin composition with CO2 laser. After the desmearing treatment was carried out in the through holes, the electroless copper plating was attached with a thickness of 0.9 µm and the electrolytic copper plating was 15 µm thick, and then circuits and connection lands were formed on the surface. After the CZ treatment was carried out on the copper layer, one sheet of prepreg F was placed on each side, and laminated and molded in the same manner as in Example 1 to produce a four-layer copper-clad laminate. In addition, as in Example 1, the solder resist was attached to open the opening, and nickel plating and gold plating were performed to obtain a core substrate J having a low thermal expansion coefficient. The thermal expansion coefficient in the longitudinal and horizontal directions of the range in which the semiconductor chip was mounted and connected to the core substrate J was 7.3 ppm / 占 폚 in the vertical direction and 7.5 ppm / 占 폚 in the horizontal direction. Next, after laminating and processing in the same manner as in Example 1, four layers were formed on the both sides, and the two sides were processed and removed in the same manner as the solder resist portion formed on the core substrate having a low thermal expansion coefficient. K was produced. Semiconductor chips were mounted and connected to both surfaces of the multilayer printed circuit board by lead-free solder to form a semiconductor plastic package L. The evaluation results are shown in Table 1.

To mount and connect the semiconductor chips in Examples 1 and 2, lead-free solder (Sn-8.0Zn-3.0Bi, melting temperature range 190 ~ 197 ℃) was used, and was bonded at a maximum temperature of 220 ℃ in the reflow process.

Example 3 Fabrication of Low Thermal Expansion Semiconductor Plastic Package Using Aramid Fiber Fabric

Using two pieces of prepreg C using the above aramid fiber woven reinforcing base material, an electrolytic copper foil having a thickness of 12 μm was placed on both sides thereof, and laminated at 90 ° C. in a vacuum of 190 ° C., 20 kgf / cm 2, and 2 mmHg for 90 minutes. It molded and the double-sided copper-clad laminated board of thickness 0.4mm was produced. Using this double-sided copper-clad laminate, the copper foil on the surface was etched and removed to a thickness of 1.2 μm, and then a through hole having a diameter of 150 μm was drilled with a CO 2 laser. The desmear process was performed to this through-hole, 1 micrometer of electroless copper plating and 15 micrometers of electrolytic copper plating were attached, and the surface produced the circuit and the land for connection. Thereafter, the surface of the copper plating was subjected to a Mec treatment, and then one piece of prepreg F was placed on each side of the printed circuit board, and an electrolytic copper foil having a thickness of 12 um was placed on the outside thereof, and laminated and molded as in Example 1 A layer double-sided copper-clad laminate was produced. After forming circuits and lands on this surface and applying CZ treatment, the width of the semiconductor chip is 3 mm larger in one direction than the range in which the semiconductor chip is mounted and connected, and the other two directions are within 5 mm from the edge of the work size. The used solder resist was formed. The portion where the semiconductor chip was mounted and connected was drilled to perform nickel plating and gold plating. On this solder resist, in order to prevent contamination that may occur during the next process, Teflon tape having a thickness of 20 μm was adhered to the periphery to prepare a core substrate N having a low thermal expansion coefficient.

One sheet of prepreg E was placed on each side of the core substrate N having a low thermal expansion coefficient, and an electrolytic copper foil having a thickness of 12 μm was placed on both sides thereof, and laminated and molded in the same manner as above to prepare a six-layer double-sided copper foil laminated plate. . The copper foil on the surface of this copper foil laminated plate was etched and removed to 1.2 micrometers in thickness, and the blind via hole of 50 micrometers in diameter was processed on this by UV-YAG laser. The via hole was subjected to a desmear treatment, and the inside of the via hole was filled with copper plating. After forming a circuit and land thereon, coating it with a solder resist, and continuing processing similarly to the above, after forming four layers on both surfaces of the core board which are low thermal expansion coefficients, respectively, after forming a low thermal expansion coefficient of Both sides were cut and removed with a UY-YAG laser to the Teflon cover film coated on the core substrate, thereby manufacturing a multilayer printed circuit board O. The thermal expansion coefficient in the vertical and horizontal directions of the range in which the semiconductor chip of the multilayer printed wiring O was mounted and connected was 6.7 ppm / 占 폚 in the vertical direction and 7.0 ppm / 占 폚 in the horizontal direction. The semiconductor chip was mounted and connected to both surfaces by the lead-free solder, and it was called semiconductor plastic package P. The evaluation results are shown in Table 1.

Example 4 Fabrication of Low Thermal Expansion Semiconductor Plastic Package Using T-Glass Fiber Fabric

800 weight part of silica was added to said varnish A, and it mixed with stirring, and produced varnish Q. This varnish Q was impregnated in T (S) -glass having a thickness of 95 µm and dried to prepare a prepreg R having a gelation time of 101 seconds (temperature: 170 ° C) and a thickness of 103 µm. Using four pieces of this prepreg R, 12um thick electrolytic copper foil was placed on both surfaces, and laminated and molded for 90 minutes under vacuum at 190 ° C, 40 kgf / cm2, and 2 mmHg to form a 0.4 mm thick double-sided copper foil laminated plate. Produced. The copper foil of this copper foil laminated board surface was etched to 1.2 micrometer thickness, and the through hole of 150 micrometers of hole diameters was processed with the CNC drill. After the desmearing treatment was performed on the through hole, copper plating was applied as in Example 1, and circuits and connection lands were formed on the surface. After carrying out CZ process on this copper plating surface, each prepreg G was arrange | positioned one by one, and it laminated | stacked and shape | molded like Example 1, and produced the 4 layer double-sided copper foil laminated board. After copper foil of both surfaces of this copper clad laminated board was etched to 1.2um, the blind via hole of 50um in diameter was formed by UV-YAG laser. Thereafter, via holes were filled with copper plating in the same manner as described above, and circuits and lands were formed on surfaces. In the same manner as above, the solder resist is coated, and nickel plating and gold plating are applied, and two directions are 3 mm wider than the range in which the semiconductor chip is mounted and connected, and the other two directions are extended to the ends of the printed circuit board. The core substrate R, which has a low coefficient of thermal expansion, was fabricated with Teflon tape from the edge of the work size to 5 mm inside.

One prepreg E was placed on each side of the core substrate R, and an electrolytic copper foil having a thickness of 12 um was placed on the outside thereof, and laminated and molded as in Example 1. Thereafter, as in Example 3, four build-up layers were prepared on both sides, thereby fabricating a total of 12 printed circuit boards. The substrate was cut by removing both sides to a core substrate having a low coefficient of thermal expansion by applying a Teflon tape with a UV-YAG laser to fabricate a multilayer printed circuit board S.

The coefficient of thermal expansion in the longitudinal and horizontal directions of the range in which the semiconductor chip was mounted and connected to the printed circuit board was 7.7 ppm / 占 폚 in the vertical direction and 7.4 ppm / 占 폚 in the horizontal direction.

A semiconductor chip was mounted and connected to both surfaces of the printed circuit board by lead-free solder to form a semiconductor plastic package T. The evaluation results are shown in Table 1.

Example 5 Preparation of Low Thermal Expansion Semiconductor Plastic Package Using Liquid Crystal Polyester Resin Composition

8 liquid crystal polyester resin composition sheets (brand name; FA film, coefficient of thermal expansion; -7 ppm / degreeC, melting | fusing point 280 degreeC, <stock> Kuraray agent) of thickness of 50um are used, and T (S)-of thickness 30um in this center The glass fiber woven fabric was arrange | positioned, the electrolytic copper foil of thickness 12um was arrange | positioned on both sides, and it laminated | stacked and shape | molded for 20 minutes under vacuum of 290 degreeC, 20 kgf / cm <2>, and 2 mmHg, and produced the copper foil laminated board of thickness 0.4mm. The copper foil of both surfaces of this copper clad laminated board was etched to 1.2 micrometers, and the through hole of 150 micrometers of hole diameters was formed by CNC drill. After performing a desmear process using plasma, electroless copper plating and electrolytic copper plating were performed like Example 1, and the circuit and the connection land were formed in the front and back. Prepreg F was arrange | positioned by each of these surfaces, and the electrolytic copper foil of thickness 12um was arrange | positioned at the other side, and it laminated | stacked and shape | molded like Example 1, and produced the four-layer double-sided copper foil laminated board. After forming a circuit and land on both surfaces of this copper foil laminated board, and forming a soldering resist, nickel plating and gold plating were performed. A 10 μm thick Teflon tape with an adhesive was applied around the solder resist coated area, one prepreg E was placed thereon, and a 12 μm thick electrolytic copper foil was placed on the outside thereof, and then laminated and molded in the same manner as above. It was. This was processed in the same manner as in Example 1 to produce four build-up layers on one side of the low thermal expansion coefficient core substrate. Subsequently, the thermosetting resin composition was covered with a thickness of 20 μm and cured in the entirety of the portions except the circuits were formed and removed. After that, the surface on which the Teflon tape was attached was removed by UV-YAG laser, and then the Teflon tape was peeled off to prepare a total 12-layer printed circuit board U. The coefficient of thermal expansion in the longitudinal and horizontal directions of the range in which the semiconductor chip of the printed circuit board U was mounted and connected was 3.2 ppm / 占 폚 in the vertical direction and 3.5 ppm / 占 폚 in the horizontal direction. A semiconductor chip was mounted and connected to one surface of this printed circuit board to form a semiconductor plastic package V. FIG. In addition, this multilayer printed circuit board is cut and removed in the same range on both sides, so that warpage and distortion are not generated. The evaluation results are shown in Table 1.

In Examples 3, 4, and 5, a semiconductor chip was bonded to a maximum temperature of 260 ° C. in a reflow process using a lead-free solder (Sn-3.5Ag, melting temperature of 221 to 223 ° C.) on a core substrate having a low coefficient of thermal expansion.

The whole semiconductor chip connection is not limited to this method, but can be bonded by various bonding methods.

Comparative Example 1

In the 12-layer multilayer printed circuit board manufactured in Example 5 above, a 12-layer printed circuit board was manufactured by attaching Teflon tape to only one surface of the substrate. After that, only the part where Teflon tape was attached to one side was cut and removed, thereby manufacturing a multilayer printed circuit board W. This was very warped and distorted so that a semiconductor chip could not be mounted and connected. The evaluation results are shown in Table 2.

Comparative Example 2

In Example 3, a circuit and via hole were formed in the inner layer in the range in which the semiconductor chip was mounted and connected to each other, whereby a multilayer printed circuit board X having 12 layers as a whole was produced. The thermal expansion coefficient in the longitudinal and horizontal directions of the range in which the semiconductor chip was mounted and connected was 23 ppm / 占 폚 in the same manner as in the longitudinal direction and in the transverse direction. Thus, the semiconductor chip was mounted and connected directly on both surfaces, and it was set as the semiconductor plastic package Y. The evaluation results are shown in Table 2.

Comparative Example 3

The T-glass fibers used in Example 4 were all replaced with E-glass fibers to prepare a 12-layer multilayer printed circuit board Z without forming convex portions. The thermal expansion coefficient in the vertical and horizontal directions of the range in which the semiconductor chip was mounted and connected was 32 ppm / 占 폚 in the same manner as in the longitudinal direction and in the transverse direction. Semiconductor chips were mounted and connected to both surfaces to form a semiconductor plastic package α. The evaluation results are shown in Table 2.

[Comparative Example 4]

In Example 1, a 12-layer printed circuit board β was manufactured by forming a circuit without forming an opening in the front and back. The thermal expansion coefficient in the vertical and horizontal directions of the range in which the semiconductor chip was mounted and connected was 12.5 ppm / 占 폚 in the vertical direction, and 13.6 ppm / 占 폚 in the horizontal direction. The semiconductor chip was mounted and connected to this one surface to form a semiconductor plastic package γ. The evaluation results are shown in Table 2.

Table 1 Evaluation Results for Examples 1-5

Item Example 1 Example 2 Example 3 Example 4 Example 5 Semiconductor chip mounting section both sides both sides both sides section Connection material between semiconductor chip and core board Lead free solder balls Bending and torsion (μm) 16 24 17 29 31 Flow out onto printed circuit board of semiconductor chip (㎛) 0 0 0 0 0 Number n (n / 100) without cracks and poor peeling 100 100 100 100 100

TABLE 2 Evaluation results for Comparative Examples 1 to 4

Item Comparative Example 1 Comparative Example 2 Comparative Example 3 Comparative Example 4 Semiconductor chip mounting section both sides both sides section Connection material between semiconductor chip and printed circuit board Lead free solder balls Bending and torsion (μm) 1000 < 276 337 121 After semiconductor chip connection (㎛) Not mounted 315 507 229 Flow out onto printed circuit board of semiconductor chip (㎛) 0 About 450 About 450 About 450 Number n (n / 100) without cracks and poor peeling Not mounted 22 7 45

[How to measure]

(1) semiconductor chip mounting connection

It was shown whether it was connected to one side or both sides.

(2) Connection between semiconductor chip and core board with low coefficient of thermal expansion

The connection material was described.

(3) warping or warping

The warpage or distortion was measured using a laser measuring device using 100 printed circuit boards each having a size of 10 x 10 mm and a 400 μm thick semiconductor chip each connected to both sides of the multilayer printed circuit board. After mounting and connecting a semiconductor chip, the maximum value of curvature or distortion was measured with the laser measuring apparatus.

(4) Crack, Peeling Defect Measurement

100 x 40 x 40mm printed circuit boards each equipped with one 10 x 10mm and 200um thick semiconductor chip on both sides of the printed circuit board are held at -45 ℃ for 30 minutes, and the temperature is increased by 30 After 1,000 cycles of the thermal shock temperature cycle test held for minutes, the quality of the connection was confirmed by an electric check. A resistance change rate of more than 10% was considered defective. In addition, cracking of a semiconductor chip, solder by a cross section, the crack of an electrically conductive adhesive, and peeling were also considered defective. The molecule showed good yield.

As can be seen in Table 1 and Table 2, the semiconductor package according to the embodiments of the present invention can be seen that not only less warpage and distortion than the comparative examples but also less defects for cracks.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

1 is a flow chart showing a method for manufacturing a semiconductor plastic package according to an embodiment of the present invention.

2 to 5 is a flow chart showing a method of manufacturing a core substrate according to an embodiment of the present invention.

6 is a cross-sectional view showing a state in which a buildup insulating layer is stacked on both surfaces of a core substrate in a method of manufacturing a semiconductor plastic package according to an embodiment of the present invention.

7 is a cross-sectional view of a semiconductor plastic package according to an embodiment of the present invention.

8 is a perspective view of a semiconductor plastic package according to an embodiment of the present invention.

<Explanation of symbols for parts of the drawings>

100: semiconductor package 110: core substrate

111 core substrate 112 resin composition

113: copper foil 114,122: insulating layer

116: copper conductor 117: circuit

118 land 119: electrical through hole

120: via 121: solder resists

130: build-up insulation layer 140: release sheet

150: opening 160: semiconductor chip

161: Semiconductor Chip Connecting Material

Claims (20)

Subtracting the core substrate; Stacking a release sheet on a region in which the semiconductor chip is to be mounted on the core substrate; Stacking a buildup insulating layer on the core substrate; Forming openings in the build-up insulating layer to be spaced apart from each other by removing the build-up insulating layer corresponding to the release sheet; And And embedding the semiconductor chip in the opening and connecting the core substrate to the core substrate in a flip chip manner. The method of claim 1, The thermal expansion coefficient of the core substrate is a manufacturing method of a semiconductor plastic package, characterized in that -10 to 9 ppm / ℃. The method of claim 1, The core substrate is a method for manufacturing a semiconductor plastic package, characterized in that it comprises any one of Invar (Invar) or Copper Invar. The method of claim 1, The core substrate is a semiconductor plastic package manufacturing method characterized in that it comprises any one of a wholly aromatic polyamide nonwoven or woven substrate. The method of claim 1, The core substrate is a semiconductor plastic package manufacturing method comprising a glass fiber or a metal material. The method of claim 1, The core substrate is a semiconductor plastic package manufacturing method comprising a liquid crystal polyester resin having a melting point of 270 ℃ or more. The method of claim 6, The liquid crystal polyester resin is a semiconductor plastic package manufacturing method, characterized in that made of any one selected from the group consisting of glass fibers, wholly aromatic polyamide fibers, polyoxybenzazole fibers. The method of claim 1, The core substrate is a semiconductor plastic package manufacturing method comprising a carbon fiber woven substrate. The method of claim 1, The thermal expansion coefficient of the build-up insulating layer is a semiconductor plastic package manufacturing method, characterized in that 10 to 25 ppm / ℃. The method of claim 1, The release sheet and the build-up insulating layer is a semiconductor plastic package manufacturing method, characterized in that laminated on both sides of the core substrate. A core substrate; Openings formed to be spaced apart from each other, and a buildup insulating layer laminated on the core substrate; And And a semiconductor chip embedded in the opening and connected to the core substrate in a flip chip manner. The method of claim 11, The thermal expansion coefficient of the core substrate is a semiconductor plastic package, characterized in that -10 to 9 ppm / ℃. The method of claim 11, The core substrate is a semiconductor plastic package, characterized in that it comprises any one of Invar (Invar) or Copper Invar. The method of claim 11, The core substrate is a semiconductor plastic package, characterized in that it comprises any one of a wholly aromatic polyamide nonwoven or woven substrate. The method of claim 11, The core substrate is a semiconductor plastic package, characterized in that comprising any one of glass fiber or metal material. The method of claim 11, The core substrate is a semiconductor plastic package, characterized in that comprises a liquid crystal polyester resin having a melting point of 270 ℃ or more. The method of claim 16, The liquid crystal polyester resin is a semiconductor plastic package, characterized in that made of any one selected from the group consisting of glass fibers, wholly aromatic polyamide fibers, polyoxybenzazole fibers. The method of claim 11, The core substrate is a semiconductor plastic package, characterized in that comprising a carbon fiber woven substrate. The method of claim 11, The thermal expansion coefficient of the build-up insulating layer is a semiconductor plastic package, characterized in that 10 to 25 ppm / ℃. The method of claim 11, The build-up insulating layer is a semiconductor plastic package, characterized in that laminated on both sides of the core substrate.

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