KR100885900B1 - Multilayered printed circuit board and fabricating method therefof - Google Patents

Abstract

A multi-layer printed circuit board and a manufacturing method thereof are provided to prevent bent and twist of a printed circuit board in mounting a flip chip by coating a metal layer having a lower thermal expansion coefficient than that of a core substrate on both surfaces of the core substrate. A core substrate having an outer layer circuit is provided. The thermal expansion coefficient of the core substrate is 10~25 ppm/°C at temperature of -60~150°C. A metal layer is coated at both sides of the core substrate. The thermal expansion coefficient of the metal layer is -5~8 ppm/°C. The metal layer includes a first metal layer, a second metal layer(146) and an insulating layer(144). A pad(162) is formed by partial removal of the metal layer. At this time, the residual rate of the metal layer is 50% or more. Insulating material is filled between the remaining metal layer and the pad. The pad is electrically connected with an outer layer circuit of the core substrate.

Description

Multilayer printed circuit board and its manufacturing method {MULTILAYERED PRINTED CIRCUIT BOARD AND FABRICATING METHOD THEREFOF}

The present invention relates to a multilayer printed circuit board and a method of manufacturing the same.

Currently, electronic devices are becoming smaller, thinner, and lighter, and the mounting connection method of semiconductor chips is changing from a wire-bonding method to a flip chip method with a large number of terminals. As the semiconductor chip mounting method is changed to a flip chip, a multilayer printed circuit board on which the chip is mounted is also required to have a high-density multilayer printed circuit board having high reliability.

In the conventional multilayer printed circuit board, when glass fiber woven fabric is used as the substrate, E glass fiber is generally used as the glass component. The glass fiber woven fabric is impregnated with a thermosetting resin composition and dried to form a B stage, and then an inner layer core circuit board is manufactured using a copper clad laminate. Then, a B stage thermosetting resin composition sheet for build up is laminated on both surfaces of the core circuit board to manufacture a multilayer printed circuit board.

The multilayer printed circuit board thus manufactured uses a resin composition for buildup having a high thermal expansion rate (generally in the longitudinal and horizontal directions of 18 to 100 ppm / ° C), and a solder resist having a higher thermal expansion rate at the surface layer ( In general, since 50 to 150 ppm / ° C.) is used, the thermal expansion coefficient of the entire multilayer printed circuit board finally obtained is 13 to 30 ppm / ° C. in the vertical and horizontal directions. However, the thermal expansion coefficient of such a multilayer printed circuit board is relatively large for a semiconductor chip having a thermal expansion coefficient of 2-3 ppm / 占 폚.

As such, when there is a difference in thermal expansion coefficient between the semiconductor chip and the multilayer printed circuit board on which the semiconductor chip is mounted, a defect such as cracking, peeling, or destruction of the semiconductor chip at the connection portion between the semiconductor chip and the substrate during the semiconductor chip mounting process This will occur. When the semiconductor chip is stacked only on one side of the multilayer printed circuit board, a problem arises in that the multilayer printed circuit board is bent or distorted.

The present invention provides a multilayer printed circuit board having excellent connection reliability between a chip and a circuit board, and a method of manufacturing the same.

According to one aspect of the present invention, there is provided a method of manufacturing a multilayer printed circuit board, the method including: providing a core substrate having an outer layer circuit and having a coefficient of thermal expansion of -60 to 150 ° C of 10 to 25 ppm / ° C. Laminating a metal layer having a coefficient of −5 to 8 ppm / ° C., removing a portion of the metal layer to form a pad and electrically connecting the pad and the outer circuit of the core substrate.

Embodiments of the method of manufacturing a multilayer printed circuit board according to the present invention may have one or more of the following features. For example, in the step of providing a multilayer printed circuit board, the coefficient of thermal expansion of the metal layer may be -3 to 5 ppm / ° C. In the removing of the metal layer, the residual ratio of the metal layer may be 50% or more, and an insulating material may be filled between the remaining metal layer and the pad.

The metal layer includes invar, and copper may be attached to the invar. In addition, after forming fine concavo-convex on one surface of the metal layer, the metal layer may be laminated through the interlayer insulating layer, or the metal layer may be laminated after black copper oxide treatment or Mack CZ treatment. In addition, a solder ball connected to the semiconductor chip may be formed on the pad.

According to another aspect of the present invention, a multilayer printed circuit board includes a core substrate having an outer layer circuit and having a thermal expansion coefficient of -60 to 150 ° C. of 10 to 25 ppm / ° C., laminated on both outer sides of the core substrate, and having a coefficient of thermal expansion of -5. It includes a metal layer of ~ 8ppm / ℃, the metal layer is formed by removing a portion of the metal layer is provided with a pad that is electrically connected to the outer circuit of the core substrate.

Multilayer printed circuit board according to embodiments of the present invention may have one or more of the following features. For example, the coefficient of thermal expansion of the metal layer may be -3 to 5 ppm / ℃, the residual ratio of the metal layer may be 50% or more. An insulating material may be filled between the remaining metal layer and the pad.

The metal layer may comprise an invar, and copper may be attached to the surface of the invar. In addition, fine unevenness may be formed on one surface of the metal layer, and fine unevenness may be formed on the copper foil by black copper oxide treatment or CZ treatment of Mack's company. In addition, a solder ball connected to the semiconductor chip may be formed on the pad.

The present invention can provide a method for manufacturing a multilayer printed circuit board with small thermal expansion of the entire substrate.

The present invention can provide a method for manufacturing a multilayer printed circuit board which can prevent bending and warping during flip connection of a flip chip.

Hereinafter, an embodiment of a multilayer printed circuit board and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same or corresponding components are given the same reference numerals. And duplicate description thereof will be omitted.

1 is a flowchart illustrating a method of manufacturing a multilayer printed circuit board according to an exemplary embodiment of the present invention.

1, a method of manufacturing a multilayer printed circuit board according to an embodiment of the present invention includes the steps of providing a core substrate having an outer layer circuit and having a thermal expansion coefficient of -60 to 150 ° C of 10 to 25 ppm / ° C, Laminating a metal layer having a thermal expansion coefficient of −5 to 8 ppm / ° C. on both sides of the core substrate, and removing a part of the metal layer to form a pad and electrically connecting the pad and the outer circuit of the core substrate.

In the method of manufacturing a multilayer printed circuit board according to the present embodiment, when a flip chip is mounted and connected to a multilayer printed wiring board having a thermal expansion coefficient similar to that of a semiconductor chip by laminating a metal layer having a lower thermal expansion coefficient than that of the core substrate on both sides of the core substrate. It is characterized by preventing bending and warping of the entire circuit board. The multilayer printed circuit board manufactured by the above method may be mounted on a semiconductor chip by using a known one such as a general solder ball, a solder ball free of lead, and a solder ball formed of gold on a pad. In addition, in a semiconductor plastic package in which a flip chip is mounted and connected with a lead-free solder, reliability is excellent without a crack or peeling of the solder in a cold heat cycle test or the like.

Hereinafter, a method of manufacturing a multilayer printed circuit board according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 6.

FIG. 2 is a cross-sectional view illustrating a state in which the interlayer insulating layer 148 and the metal layer 140 are sequentially positioned on both outer sides of the core substrate 120, and FIG. 3 is an interlayer insulating layer 148 and a metal layer in FIG. 2. It is sectional drawing which shows the state which laminated | stacked 140.

Referring to FIG. 2, an interlayer insulating layer and a metal layer 140 are sequentially stacked on both outer sides of the core substrate 120. The core substrate 120 generally has a thermal expansion rate of 10 to 25 ppm / ° C at -60 to 150 ° C. And the thermal expansion coefficient of the metal layer 140 is -5 ~ 8ppm / ℃. Therefore, since the thermal expansion coefficient of the metal layer 140 is smaller than that of the core substrate 120, the metal layer 140 suppresses the thermal expansion coefficient of the core substrate 120 to reduce the overall thermal expansion coefficient, thereby becoming similar to the thermal expansion coefficient of the semiconductor chip. The bump metal to which the flip chip is mounted also has a thermal expansion coefficient close to that of the semiconductor chip, thereby reducing the stress between the semiconductor chip and the bump when the flip chip is mounted and connected in the reflow process, thereby preventing warping or warping of the multilayer printed circuit board. In addition, even after the semiconductor chip is mounted, excellent overall reliability can be obtained.

The inner circuit 126 and the build-up insulating layer 122 are sequentially formed on both surfaces of the core insulating layer 124 of the core substrate 120, and the outer circuit 136 is formed on the outermost layer. The build-up insulating layer 122 may be stacked on both outer sides of the core insulating layer 124 in the same number of layers. The build-up resin composition or IVH filling ink 132 is filled between the core insulating layers 124.

As the core substrate 120, a general multilayer printed circuit board may be used. For example, an epoxy resin composition circuit board, a polyimide resin composition circuit board, a cyanate ester resin composition circuit board, a cyanate ester marimid resin composition circuit board, a benzocyclobutene resin composition circuit board, and a functional group-containing polyphenyl The ethylene ether resin composition circuit board may be used, but is not limited thereto. Among them, the epoxy resin or the cyanate ester resin composition has an advantage of relatively low cost.

In general, the double-sided copper clad laminate used for the core substrate 120 may use a nonwoven or woven fabric of inorganic or organic fibers as a reinforcing substrate. As an inorganic fiber, E, D (S), NE glass fiber, etc. are mentioned, for example. Further, the organic fibers include heat resistant fibers such as poly-oxibenzol fibers, wholly aromatic polyamide fibers, or liquid crystal polyester fibers. And polyimide film, wholly aromatic polyamide film, liquid crystal polyester film, etc. can also be used as a reinforcement base material. In order to improve the adhesiveness with such a resin, such a base material is well-known to the surface of a base material, for example, an inorganic fiber, such as glass fiber cloth, a silane coupling agent process, an organic substance, such as a film material, plasma processing, corona treatment, various Chemical treatment or blast treatment may be optionally performed. In the case of the film material, a copper sheet may be used by adhering an adhesive to both sides of the film to bond the copper foil or directly adhering the copper foil by a known method.

In general, the copper-clad laminate and the build-up insulating layer 122 may be formed of one or two or more kinds of known thermosetting resins, thermoplastic resins, UV curable resins, unsaturated group-containing resins, and the like. In particular, a thermosetting resin composition or a heat resistant thermoplastic resin composition having a melting point of 270 ° C. or higher may be used.

As the thermosetting resin used as the resin of the insulating layer of the core substrate 120, generally known ones can be used. For example, a composition in which known resins such as epoxy resins, cyanic acid ester resins, bismarimide resins, polyimide resins, functional group-containing polyphenylene ether resins, cardh resins, or phenol resins are used alone or in combination of two or more thereof. Used as And cyanic acid ester resin may be used to prevent further narrowing of through-holes or circuits. In addition, known resins flame retarded with phosphorus may also be used.

The thermosetting resin according to the present embodiment is cured by heating itself, but since the curing speed is slow and the productivity is inferior, an appropriate amount of a curing agent or a thermosetting catalyst can be used for the thermosetting resin.

What mix | blends various well-known additives as a composition with such a thermosetting resin can be used generally. For example, thermosetting resins, thermoplastic resins, other resins, well-known organic and inorganic fillers, dyes, pigments, thickeners, lubricants, defoamers, dispersants, leveling agents, gloss agents, thixoproic imparting agents other than the above Various additives may be added in appropriate amounts depending on the purpose and use. In addition, flame retardants, flame retardant with bromine, non-halogen type (non halogen type) and the like can be used.

Generally known thermoplastic resins can be used. Specifically, liquid crystal polyester resins, polyurethane resins, polyamideimide resins, polyphenylene ether resins and the like may be used alone or in combination of two or more thereof. And as a thermoplastic resin, the thing which has a melting point of 270 degreeC or more which temperature does not produce a defect in a wiring board in the high temperature reflow process can be used. It is also possible to add appropriate amounts of the various additives described above in the thermoplastic resin. And a thermoplastic resin and a thermosetting resin can be mixed and used.

In addition to the thermosetting resin and the thermoplastic resin, one or two or more kinds of resins cured with UV or radically cured resins can be used. And the photoinitiator which promotes crosslinking, a radical polymerization initiator, or the various additives mentioned above can be mix | blended and used suitably.

When manufacturing the core substrate 120, it is not necessary to necessarily use only the materials of the same resin composition described above, for example, the core insulating layer 124 using the E glass fiber woven base material epoxy resin composition copper clad laminated board, build As the up insulation layer 122, the sheet | seat with copper foil of the B-stage cyanate ester system resin composition which does not contain a reinforcing base material, the sheet | seat of the B-stage unsaturated group containing polyphenylene ether resin composition, etc. can be used.

The core substrate 120 is a multilayer printed circuit board generally manufactured by a known method, and is a copper-clad laminate such as an inexpensive material such as an E glass fiber woven base epoxy resin composition or an E glass fiber woven base cyanate ester resin composition. , Prepregs and the like can be used. At this time, when the thermal expansion coefficient of the core substrate 120 is to be lowered, the thermal expansion coefficient is 10ppm by using an expensive all-aromatic polyamide fiber or T (S) glass fiber woven fabric alone or in combination as a copper clad laminate or a prepreg. It can be close to / ℃.

The method of manufacturing the core substrate 120 is not particularly limited, but there are conventional subtractive methods or semi-additive methods. Although the thermal expansion coefficient of the core board | substrate 120 is measured by well-known methods, such as TMA, when a reinforcing base material or resin to be used differs, these are shown by the combined thermal expansion coefficient.

The metal layer 140 is positioned on the outermost layer and is formed of an invar first metal layer 142, an invar second metal layer 146, a first metal layer 142, and a first etching layer. The insulating layer 144 is interposed between the two metal layers 146.

The first metal layer 142 or the second metal layer 146 used in the present embodiment is not particularly limited, but an alloy such as invar or copper invar is used. Invar is an alloy of iron (Fe) and nickel (Ni) and has a thermal expansion coefficient of 1 ppm / ° C or less at 100 ° C or less. Cobalt (Co), manganese (Mn), niobium (Nb), aluminum nitride (AlN) and the like can be added to Invar in a small amount. Moreover, the material which aged this (aging) can also be used.

The copper invar may be a metal having a three-layer structure in which copper having a thickness of 1 to 200 μm is attached to both surfaces of the invar by rolling. Of course, the metal foil of the 3-layered structure which adhere | attached 1 micrometer or less copper layer by sputtering etc. can also be used. If the thickness of copper is thick, the coefficient of thermal expansion of copper is 17ppm / ° C. Therefore, the integrated copper invar uses a thin copper layer so that the coefficient of thermal expansion does not exceed 8ppm / ° C. When the copper layer is thick, the copper layers on both sides may be etched to have a thickness of 5 μm or less. In addition, when the copper layer is thin, a copper inbar having a copper layer attached to one side may be used. Instead of copper, other metals such as nickel can be used.

The coefficient of thermal expansion, thickness, and number of sheets of copper foil used for the metal layer 140 are selected in consideration of the coefficient of thermal expansion of the core substrate 120. Of course, it is also possible to produce the core substrate 120 from a metal having a low thermal expansion coefficient having a structure of three or more layers. In addition, the metal layer 140 may increase the residual ratio of the metal layer 140 in a later process in order to obtain a desired coefficient of thermal expansion even with a small number of layers, which will be described in detail below.

Referring to FIG. 3, the metal layer 140 is laminated on both outer sides of the core substrate 120 to be integrated using an interlayer insulating layer 148 such as a prepreg. In this case, fine unevenness may be formed on the core substrate 120 by chemical etching or sand blasting, and in some cases, chemical treatment may be possible.

In the case of copper invar, the copper foil of the surface layer is etched thinly in the thickness direction to have a thickness of 1 to 3 μm, and then the copper foil is subjected to a known black copper oxide treatment or CZ treatment of Mack, etc. to obtain an interlayer insulating layer such as prepreg (148). ) Is laminated. If the copper layer remains thick, the coefficient of thermal expansion increases. Of course, general electrolytic copper foil mat surface treatment which improves adhesiveness with a resin composition is also possible.

As a method of forming the via hole by processing the copper invar or the invar, for example, there is a method in which a UV-YAG laser, a diamond drill, or etching is performed alone or in parallel. In addition, etching liquids, such as ferric chloride, can be used for circuit preparation. In this way, a portion of the second metal layer 146 may be removed to form a via hole (see 166 of FIG. 4) connecting the pad of the outer layer (see 162 of FIG. 4) and the outer circuit 136 of the core substrate. It can provide a space.

4 illustrates a state in which a pad 162 and a via hole 166 to which the pad 162 and the outer circuit 136 of the core substrate are connected are formed in the first metal layer 142 after the metal layer 140 is stacked. It is a cross section.

Referring to FIG. 4, a portion of the first metal layer 142 positioned at the outermost layer is removed to form a pad 162. A solder resist 164 is formed between the pad 162 and the metal remaining portion 168 for insulation, and the pad 162 and the outer layer circuit 136 of the core substrate are connected by the via hole 166. The pad 162 is formed with solder balls (see 174 in FIG. 6) by a later process. If necessary, a through hole 152 may be formed in the multilayer printed circuit board 100.

5 illustrates a pad 162 and a metal remaining portion 168 formed by removing a portion of the first metal layer 142.

The pad 162 is formed with solder balls 174 of FIG. 6. Although the shape of the pad 162 is generally circular, the shape of the pad 162 may vary depending on the connection pad of the semiconductor chip. As described above, by increasing the area of the pad 162 and the metal remaining portion 168 to about 50% or more of the area of the first metal layer 142, an increase in the thermal expansion rate of the metal layer can be prevented.

6 is a cross-sectional view illustrating a state in which a flip chip package 160 is formed by mounting a semiconductor chip 172 on a multilayer printed circuit board 100 according to an exemplary embodiment of the present invention.

Referring to FIG. 6, solder balls 174 are formed on pads 162 of the multilayer printed circuit board 100. The solder ball 174 is connected to the connection pad 176 of the semiconductor chip 172. A metal layer having excellent electrical conductivity such as gold may be formed on the pad 162. In FIG. 6, the semiconductor chip 172 is mounted on both surfaces of the multilayer printed circuit board 100, but the semiconductor chip 172 may be mounted on only one surface if necessary.

The multilayer printed circuit board 100 according to the present exemplary embodiment mounts the semiconductor chip by a flip chip method, but may also mount the semiconductor chip using wire bonding. In the case where the semiconductor chip is mounted on one side, the solder ball may be bonded to the other side to form a ball grid array package.

FIG. 7 is a cross-sectional view illustrating a flip chip package 160 formed by mounting a semiconductor chip 172 on a multilayer printed circuit board 100 according to an exemplary embodiment of the present invention. The state in which the solder ball 174 is formed in 163 is shown.

As shown in FIG. 7, the solder ball 174 may be formed in the portion 163 extending from the pad 162 to avoid the portion of the via hole 166. For this reason, the solder ball 174 can be easily positioned.

Hereinafter, the configuration and features of the present invention will be described in more detail by preparing examples and comparative examples according to the present invention. Hereinafter, "part" means a weight part unless there is particular notice.

Example 1

(1) Core board production

The surface layer copper foil of the epoxy-type double-sided copper clad laminated board (brand name; ELC-4785GS, CTEα1; 11ppm / degree, Sumitomo Bakelite Co., Ltd.) of thickness 0.2mm which insulated the electrolytic copper foil of thickness 12μm on both surfaces is etched, and it is 1.8 micrometer in thickness . Then, a through hole having a hole inner diameter of 150 μm was formed using a metal drill, and after desmear treatment, 0.9 μm of electroless copper plating and 20 μm of electrolytic copper plating were attached. Thereafter, a circuit of line / space = 40/40 μm is formed by a subtractive method, followed by black copper oxide treatment. Then, each of the two sheets of 40 μm-thick build up sheet (trade name; APL-3601, Sumitomo Bakelite Co., Ltd.) was placed on each side, and 12 μm-thick electrolytic copper foil was placed on both sides thereof, and then 200 ° C and 25 kgf / A four-layer double-sided copper clad laminate was produced by lamination for 90 minutes in a vacuum of cm ² and 2 mmHg.

Then, the surface layer of the electrolytic copper foil is etched to 2.0 μm, a blind via hole having a diameter of 50 μm is formed using a UV-YAG laser, and then desmeared. Then, after filling the inside of a hole with copper plating, the outer layer circuit was produced on the surface. This process was repeated to produce a six-layer printed circuit board A (core substrate). In addition, the CZ treatment of Mack Corporation was performed on the surface of the printed circuit board A to form a six-layer printed circuit board B. The printed circuit board A has a thermal expansion coefficient of 17.8 ppm / 占 폚 (TMA measurement) in the longitudinal direction of the range in which the semiconductor chip is mounted and connected.

(2) Manufacture of multilayer printed circuit board with metal layer

30 µm thick metal insulating layer (trade name; APL) after forming fine surface unevenness (Rz; 3.2 µm) in an in-bar (Fe-Ni-Co alloy; thermal expansion coefficient 0.4 ppm / ° C, Hitachi Metal Co., Ltd.) having a thickness of 20 µm and 50 µm. -3651, Sumitomo Bakelite Co., Ltd.) was laminated on both sides under vacuum at 200 ° C., 30 kgf / cm ^2, and 2 mmHg for 90 minutes to form a metal layer. Then, a 50 μm-thick Invar circuit was formed with a ferric chloride solution to form a metal layer C.

The metal layer thus formed was stacked on both outer layers of the six-layer printed circuit board B, each having an interlayer insulating layer APL-3651 having a thickness of 40 μm, and the metal layer C was laminated to prepare 10 copper-clad laminates D. A hole-forming auxiliary sheet (trade name; LE400, Mitsubishi Gas Chemical Co., Ltd.) was placed on top of this, and a paper phenol plate of 1.6 mm thickness was placed on the bottom, and a through hole was formed by a diamond drill having a diameter of 200 μm. Subsequently, after removing the upper and lower hole forming auxiliary sheets, blind via holes having a diameter of 85 μm were formed on both sides by using a UV-YAG laser, and then desmearing was performed to sputter with a thickness of 710 kPa on the front surface to form a copper film. .

And after forming 0.9μm of copper foil with electroless copper plating, blind via holes were filled with electrolytic copper plating. Moreover, the copper layer copper-plated on the surface was etched until it became 1.3 micrometers in thickness, and the thickness of copper was thinned. A land having a pitch of 400 µm and a terminal diameter of 180 µm were formed on the surface. The inba part of the outermost layer and the two layers from the top made the inba residual ratio as high as possible by excluding a circuit formation part. Solder resistors (trade name: PSR4000AUS308, Taiyo Ink Manufacturing Co., Ltd.) were formed on both surfaces to form a thickness of 15 µm, and copper exposed portions including the through holes were subjected to nickel plating 5 μm and gold plating 0.2 μm, respectively. Produced.

The semiconductor chip was bonded to the printed circuit board E using a lead-free solder ball (Sn-3.5Ag, melting temperature of 221 to 223 캜) and heated to a maximum temperature of 260 캜 through a reflow process.

Table 1 shows the experimental results of the flip chip package formed through such a process.

Example 2

(1) Core board production

After dissolving 550 parts of 2,2,-screw (4-cyanaphenyl phenyl) propane monomers at 150 degreeC, it stirred for 4.5 hours of stirring quality, and obtained the mixture of a monomer and a prepolymer. This was dissolved in methyl ethyl ketone, 100 parts of bisphenol A type epoxy resin (trade name: Epicoat 1001, Nippon Epoxy Resin Co., Ltd.), 150 parts of phenol novolak type epoxy resin (brand name: DEN-431, Dow Chemical Co., Ltd.), cresol novolac After blending 200 parts of a type epoxy resin (trade name: ESCN-220F, Sumitomo Chemical Co., Ltd.), zinc octylate was dissolved in 0.2 parts of methyl ethyl ketone as a curing catalyst, stirred and mixed to form varnish F. And 1000 parts of inorganic filler spherical silica (average particle diameter; 0.9 micrometer) were added, it stirred, and it disperse | distributed and it was set as varnish G.

On the other hand, varnish F was impregnated and dried to aramid fiber woven fabric having a thickness of 200 µm, and prepreg H having a resin composition content of 43% by weight was produced at 112 seconds for gelation time (at170 ° C).

Furthermore, varnish G was impregnated and dried to a 50 micrometer-thick T (S) glass fiber woven base material, and the prepreg I of 73 weight% of resin composition content was produced for 146 seconds of gelation time (at170 degreeC).

One piece of prepreg H was used, and an electrolytic copper foil having a thickness of 12 μm was placed on both sides thereof, and laminated at 90 ° C., 20 kgf / cm ² , and vacuum of ² mmHg for 90 minutes to prepare a double-sided copper clad laminate having a thickness of 0.2 mm. After etching the copper foil of both surfaces of this double-sided copper clad laminated board to 1.4 micrometer, the through hole of 150 micrometers in diameter was formed with the carbon dioxide laser, and 0.9 micrometer of electroless copper plating and 20 micrometers of electrolytic copper plating were formed after the desmear process. And the circuit of line / space = 40 / 40micrometer was formed in the surface using the subtractive method. Further, after applying CZ treatment to Mack's copper foil, a prepreg (trade name; APL-3651, Sumitomo Bakelite Co., Ltd.) having a thickness of 40 μm was placed on both sides, and an electrolytic copper foil having a thickness of 12 μm was placed on the outside. In the same manner, the laminate was molded to produce a four-layer double-sided copper clad laminate.

The copper foil on the surface of the four-layer double-sided copper clad laminate was etched to a thickness of 1.3 μm and then irradiated with UV-YAG laser to form a blind via hole having a diameter of 50 μm. After the desmear treatment, the inside of the hole was filled with copper plating. After that, a circuit was formed on the front and back, and the CZ treatment, lamination, and circuit formation were repeated to produce a six-layer printed circuit board J. CZ treatment was performed on the surface thereof to form a six-layer printed circuit board K, that is, a core substrate. The thermal expansion coefficient of the semiconductor chip mounting portion of the six-layer printed circuit board J was 11.7 ppm / 占 폚.

(2) Manufacture of multilayer printed circuit board

1 sheet of each prepreg I was placed on both sides of a six-layer printed circuit board K, and a copper invar plate (coefficient of thermal expansion; 4.0 ppm / ° C) having a copper layer of 3 μm was placed on both sides of an invar having a thickness of 25 μm on the outside thereof. It laminated-molded and produced the 8 layer copper clad laminated board L. Blind via holes having a diameter of 70 μm were formed on both surfaces by using a UV-YAG laser, and after the desmear treatment with plasma, the inside of the holes was filled with copper plating. The copper plated copper layer on this surface was etched to a thickness of 1.2 μm to minimize thermal expansion. On this surface, an integrated eight-layer printed circuit board was fabricated by forming a pitch for connection at 400 mu m and a pad diameter at the same time as a bonding pad at 180 mu m. As for the copper invar part, except for the circuit formation part, it was made to remain | survive copper inbar on each 1st floor up and down. A solder resistor (trade name; PSR4000AUS308, Taiyo Ink Manufacturing Co., Ltd.) was formed on the surface with a thickness of 15 µm, and nickel plating 5 µm and gold plating 0.2 µm were formed to form an eight-layer printed circuit board M.

A semiconductor chip to which lead-free solder (Sn-3.5Ag, melting temperature of 221 to 223 ° C.) was bonded was attached to both sides of an 8-layer printed circuit board M at a maximum temperature of 260 ° C. using a reflow process to form a flip chip package.

Table 1 shows the evaluation results of the flip chip package formed by the above method.

Example 3 and Example 4

In Example 1 and Example 2, only one side of the semiconductor chip was mounted on the integrated 10-layer printed circuit board E and the 8-layer printed circuit board M, and the same test was performed as in Example 1 and Example 2.

Table 1 shows the evaluation results.

Example 5

In the eight-layer printed wiring board M, the metal residual ratio of the copper invar of the outermost layer was reduced, and in the same manner, an eight-layer printed circuit board N was produced. Then, a semiconductor chip was mounted on one side of the printed circuit board N.

The evaluation results thereof are shown in Table 1.

Comparative Example 1

In the first embodiment, a multilayer printed circuit board B having six layers is used, and one prepreg (trade name; GEA-679 FGR, Hitachi Chemical Co., Ltd.) having a thickness of 40 μm is placed on both sides, and the thickness thereof is on the other side. Each 12 micrometer electrolytic copper foil was arrange | positioned, it laminated | stacked and shape | molded for 90 minutes by the vacuum of 200 degreeC, 25 kgf / cm <^2> , and 2 mmHg, and produced eight double-sided copper clad laminated board O. In addition, the blind via hole was formed in the same manner as in the embodiment, and the same method was repeated to fabricate the printed circuit board P having 10 layers. Then, semiconductor chips were mounted on both sides.

Table 2 shows the results of the evaluation.

Comparative Example 2

Using the six-layer printed circuit board K used in Example 2, one prepreg (trade name; APL-3651, Sumitomo Bakelite Co., Ltd.) having a thickness of 40 µm is disposed on both sides thereof. Then, an electrolytic copper foil having a thickness of 12 μm was placed on the other side, and laminated molding was performed to produce an eight-layer printed circuit board Q. Then, semiconductor chips were mounted on both sides.

Table 2 shows the results of the evaluation.

Comparative Example 3 and Comparative Example 4

The 10-layer and 8-layer printed circuit boards P and Q produced in Comparative Example 1 and Comparative Example 2 were used, and a semiconductor chip was mounted on one side thereof.

Table 2 shows the results of the evaluation.

Comparative Example 5

In Comparative Examples 1 to 4, since the copper layer was used for the outermost layer, increasing the copper residual ratio increases the thermal expansion coefficient of the integrated multilayer printed circuit board, and the copper residual ratio is increased in order to avoid a large difference in thermal expansion coefficient with the semiconductor chip. It fell to 50% or less. In Comparative Example 5, only the outermost layer of the eight-layer printed circuit board Q was raised to 50% or more, and the other layer was formed in the same manner to produce an eight-layer printed circuit board R. The semiconductor chip was mounted on one surface.

Table 2 shows the results of the evaluation.

TABLE 1 Evaluation results for Examples 1 to 5

Item Example  One Example 2 Example 3 Example 4 Example 5 Metal Retention Rate (%) Outermost layer 67 82 67 82 45 2nd layer from outermost layer 85 - 85 - - Semiconductor chip mounting both sides both sides One side One side One side Solder ball Lead free solder balls Bending and torsion (μm) 75 60 101 121 189 Number n (n / 50) without crack and poor peeling 50 50 50 50 50

TABLE 2 Evaluation results for Comparative Examples 1 to 5

Item Comparative example  One Comparative Example 2 Comparative Example 3 Comparative Example 4 Comparative Example 5 Metal Retention Rate (%) Outermost layer 40 49 40 49 82 2nd layer from outermost layer 85 - 85 - - Semiconductor chip mounting both sides both sides One side One side One side Solder ball Lead free solder balls Bending and torsion (μm) 121 115 598 332 761 Number n (n / 50) without crack and poor peeling 5 14 0 7 50

How to measure

(1) bending and torsion

Using 50 laser modules of 40 × 100 mm, each having a 10 × 10 mm flip chip having a thickness of 400 μm and a thickness of 400 μm, each of which was connected to each of two sides or one side, each of the 40 × 100 mm modules was measured using a laser measuring device. The bending and torsion of the first printed circuit board was selected using 50 ± 5 μm, and the maximum value of the bending and torsion was measured by a laser measuring device after the flip chip was mounted and connected.

(2) Crack and peeling failure

-50 ° C / 30min. By using 50 modules of 40x100 mm each having 10 x 10 mm and 400 μm thick flip chips each connected to two sides or one side to the left and right and the center (6 in total). → After 1000 cycles of the temperature cycling test of 125 degreeC / 30min., The quality of the connection was confirmed. Here, the resistance change rate exceeded +/- 10% as defect. In addition, after confirming cracking and peeling of the lead-free solder ball due to the cleavage and cross-section of the semiconductor chip, the number without defect is shown in Table 1 and Table 2.

In contrast to Tables 1 and 2, it can be seen that the flip chip package using the multilayered printed circuit board according to the embodiments of the present invention exhibits less warpage and distortion as well as less cracking and peeling defects than the comparative examples. This is because a metal layer having a small coefficient of thermal expansion is stacked on the outermost layer of the multilayer printed circuit board according to the embodiment of the present invention.

As can be seen from Table 1, the case where the semiconductor chip is mounted on both sides of the semiconductor chip on one side shows less warpage and distortion of the entire flip chip package. The higher the metal residual ratio of the outermost metal layer, the less the warpage and distortion of the entire flip chip package.

Although the embodiments of the present invention have been described above, various changes and modifications of the present invention should also be construed as falling within the scope of the present invention as long as the technical idea of the present invention is implemented.

1 is a flowchart illustrating a method of manufacturing a multilayer printed circuit board according to an exemplary embodiment of the present invention.

2 is a cross-sectional view showing a state before laminating an interlayer insulating layer and a metal layer on both outer layers of a core substrate in a method of manufacturing a multilayer printed circuit board according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a state in which an interlayer insulating layer and a metal layer are laminated on both outer layers of the core substrate in FIG. 2.

4 is a cross-sectional view of the multilayer printed circuit board having through holes and pads formed therein in FIG. 3.

5 is a plan view illustrating a state in which a pad is formed by removing a portion of the first metal layer;

6 and 7 are cross-sectional views illustrating a semiconductor chip mounted on a multilayer printed circuit board according to an exemplary embodiment of the present invention.

<Description of Drawing>

100: multilayer printed circuit board 120: core board

140: metal layer 162: pad

172: semiconductor chip 174: solder ball

Claims (18)

Providing a core substrate having an outer layer circuit and having a coefficient of thermal expansion of -60 to 150 ° C of 10 to 25 ppm / ° C; Stacking metal layers having a coefficient of thermal expansion of −5 to 8 ppm / ° C. on both outer sides of the core substrate; Removing a portion of the metal layer to form a pad and electrically connecting the pad and the outer layer circuit of the core substrate; The method of claim 1, The thermal expansion coefficient of the metal layer is -3 to 5 ppm / ℃ manufacturing method of a multilayer printed circuit board. The method of claim 1, In the step of removing the metal layer, the residual ratio of the metal layer is a multilayer printed circuit board manufacturing method, characterized in that 50% or more. The method of claim 3, And a dielectric material is filled between the remaining metal layer and the pad. The method of claim 1, The metal layer is a multilayer printed circuit board manufacturing method comprising an invar (invar). The method of claim 5, The metal layer is a multilayer printed circuit board manufacturing method, characterized in that the copper is attached. The method of claim 5, And forming fine concavo-convex on one surface of the metal layer, and then laminating the metal layer via an interlayer insulating layer. The method of claim 6, The copper foil is a black copper oxide treatment or Mack's CZ treatment is performed. The method of claim 1, The pad is a solder ball connected to the semiconductor chip is formed, characterized in that the printed circuit board manufacturing method. A core substrate having an outer layer circuit and having a thermal expansion coefficient of -60 to 150 ° C of 10 to 25 ppm / ° C; A metal layer having a thermal expansion coefficient of -5 to 8 ppm / ° C, laminated on both outer sides of the core substrate; And a pad formed by removing a portion of the metal layer, the pad being electrically connected to the outer circuit of the core board. The method of claim 10, The thermal expansion coefficient of the metal layer is a multilayer printed circuit board, characterized in that -3 ~ 5 ppm / ℃. The method of claim 10, The residual ratio of the metal layer is a multilayer printed circuit board, characterized in that 50% or more. The method of claim 12, And a dielectric material is filled between the remaining metal layer and the pad. The method of claim 10, The metal layer is a multilayer printed circuit board, characterized in that it comprises an invar (invar). The method of claim 14, The metal layer is a multilayer printed circuit board, characterized in that copper is attached. The method of claim 14, Layer printed circuit board, characterized in that minute irregularities are formed on one surface of the metal layer. The method of claim 15, The copper foil is a multilayer printed circuit board, characterized in that irregularities are formed by a black copper oxide treatment or Mack's CZ treatment. The method of claim 10, The pad is formed with a solder ball connected to the semiconductor chip, the multilayer printed circuit board.

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