KR100752025B1 - Manufacturing method of printed circuit board - Google Patents

Abstract

A method of manufacturing a printed circuit board is provided to simplify a manufacturing process of the PCB(Printed Circuit Board) by forming a convexo-concave surface on an insulation layer using a release film. An insulation layer(10) is provided. A release film is attached to the insulation layer. The release film includes a convexo-concave forming layer, on which a convexo-concave surface is formed. A convexo-concave plane(12) is formed on the insulation layer. The release film is peeled off. A circuit layer(30) is formed on the convexo-concave plane of the insulation layer. The insulation layer configures a core layer or a build-up layer.

Description

MANUFACTURING METHOD OF PRINTED CIRCUIT BOARD

1A to 1M are cross-sectional views illustrating a method of manufacturing a printed circuit board according to the present invention.

Figure 2 is a cross-sectional view showing another release film that can be applied to the present invention.

3A to 3C are cross-sectional views showing another method of forming a circuit layer in the present invention.

<Description of reference numerals for the main parts of the drawings>

10: insulating layer 12: uneven surface

14: via hole 20, 120: release film

22, 122: uneven surface 24, 124: uneven surface forming layer

26: reinforcement layer 30: circuit layer

32a: electroless copper plating layer 34: electrolytic copper plating layer

36: nickel plated layer 37: gold plated layer

40, 40 ': plating resist 50: solder resist

The present invention relates to a method of manufacturing a printed circuit board, and more particularly, the present invention relates to a method of manufacturing a printed circuit board that can use a variety of materials as an insulating layer by improving the adhesion between the insulating layer and the circuit layer.

Printed circuit boards are the most basic electronic components used in electronic communication devices and the like, and with the rapid development of electronic communication technology, printed circuit board technology is also rapidly developing. In order to improve the characteristics of electronic communication devices, research is being conducted to improve the characteristics of printed circuit boards such as miniaturizing circuit patterns of printed circuit boards.

In order to form a fine circuit pattern, there is a method of etching the copper foil of the copper-clad laminate and forming a copper plating layer, and then patterning them. However, this method is complex and time consuming. And, when the surface irregularities of the copper foil is large, it may be difficult to remove the copper plating layer formed inside the surface irregularities of the copper foil when etching the copper plating layer for patterning. In this case, when overetching is performed in order to effectively remove the copper plating layer, the defect may increase due to the undercut phenomenon, and the yield may decrease. On the other hand, when the surface irregularities of the copper foil is small, the adhesive strength is weak, so that the circuit pattern may be peeled off in a subsequent process.

As another method, there is a method of forming a circuit pattern by a subtractive method on a copper foil laminated plate having a carrier metal foil having a thickness of 3 µm to 5 µm. However, if the copper plating layer is formed after the formation of the via hole, the thickness to be etched is 20 μm or more, and the subtractive method makes it difficult to refine the circuit pattern and has a low yield.

A method of forming a circuit pattern by a semi-additive method is a material in which the material constituting the insulating layer can improve the adhesion with the circuit pattern, that is, a resin composition for semi-additive or a UV selective thermosetting resin composition. There is a problem that should be limited to such. The resin composition may have low heat resistance, chemical resistance, and migration resistance after absorption of the printed circuit board due to an additive added thereto, and may increase transmission loss. In addition, there is a limit to the amount of the inorganic filler to improve the rigidity can not effectively prevent the bending or twisting of the printed circuit board. In addition, there is a difficulty in manufacturing a high frequency printed circuit board.

The present invention was devised to solve the above problems, and an object of the present invention is to improve the adhesion between the insulating layer and the circuit layer by a simple process, and to manufacture a printed circuit board capable of forming the insulating layer from various materials. To provide a way.

In order to achieve the above object, a method of manufacturing a printed circuit board according to the present invention includes: (a) preparing an insulating layer; (b) attaching a release film including an uneven surface on which the uneven surface is formed to the insulating layer, thereby forming the uneven surface on the insulating layer; (c) peeling off the release film; And (d) forming a circuit layer on the uneven surface of the insulating layer.

In the method of manufacturing a printed circuit board of the present invention, the insulating layer constitutes a core layer or a buildup layer.

In the method of manufacturing a printed circuit board of the present invention, the uneven surface of the release film has a ten point average roughness (Rz) of 2 μm to 10 μm. Here, it is more preferable that the uneven surface of the release film has a ten point average roughness of 3 μm to 9 μm.

In the method of manufacturing a printed circuit board of the present invention, the release film is characterized in that it further comprises a reinforcing layer attached to the opposite side of the uneven surface of the release film.

In the method of manufacturing a printed circuit board of the present invention, the reinforcing layer is characterized in that it comprises a material selected from the group consisting of aluminum, iron, copper and alloys thereof. However, the present invention is not limited thereto.

In the method of manufacturing a printed circuit board of the present invention, the uneven layer may include a material selected from the group consisting of a thermosetting resin, a thermoplastic resin, and a mixed resin thereof.

In the method of manufacturing a printed circuit board of the present invention, the insulating layer is characterized in that it comprises a material selected from the group consisting of a thermosetting resin, a thermoplastic resin and a mixed resin thereof.

In the method of manufacturing a printed circuit board of the present invention, after the step (d), the step (c) and the step (d) is repeated at least one or more times.

In the method of manufacturing a printed circuit board of the present invention, the step (d) may include forming an electroless copper plating layer on the insulating layer; Forming a plating resist having a predetermined pattern on the electroless copper plating layer; Forming an electrolytic copper plating layer on the electroless copper plating layer according to the pattern of the plating resist; Removing the plating resist; And removing a portion of the electroless copper plating layer in which the electrolytic copper plating layer is not formed.

In the method of manufacturing a printed circuit board of the present invention, the step (d) may include forming a plating resist having a predetermined pattern on the insulating layer; Forming an electroless copper plating layer on the insulating layer according to the pattern of the plating resist; Forming an electrolytic copper plating layer on the electroless copper plating layer according to the pattern of the plating resist; And removing the plating resist.

Hereinafter, a method of manufacturing a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1M are cross-sectional views illustrating a method of manufacturing a printed circuit board according to the present invention.

First, as shown in FIG. 1A, an insulating layer 10 is prepared. In the present specification, the insulating layer 10 is formed by covering the circuit layer outside the core layer, that is, the core layer, that is, the core layer, that is, the build-up layer, that is, the core layer, as well as the insulating layer that is the basis for manufacturing the multilayer printed circuit board. The concept includes all the insulating layers. In the drawings for the sake of clarity, the insulating layer 10 is illustrated as a core layer, but the present invention is not limited thereto.

In the present invention, the insulating layer 10 includes a thermosetting resin, a thermoplastic resin, and the like, and is preferably in a semi-cured state (B-stage). The insulating layer 10 may be formed using a prepreg or a heat resistant film in which the resin has penetrated the base material. However, the present invention is not limited thereto, and the insulating layer 10 may be formed in various ways.

Thermosetting resins include cyanate ester resins, marimide resins, polyimide resins, functional group addition polyphenylene ether resins, benzocyclobutene resins, epoxy resins, and the like.

Here, as cyanate ester resin, 1, 3- dicyanate benzene, 1, 4- dicyanate benzene, 1, 3, 5- tricyanate benzene, 1, 3- dicyanate naphthalene, 1, 4- dish Anatenaphthalene, 1,6-dicyanatenaphthalene, 1,8-dicyanatenaphthalene, 2,6-dicyanatenaphthalene, 2,7-dicyanatenaphthalene, 1,3,6-tricyanatenaphthalene, 4,4-dicyanatebiphenyl, bis (4-cyanatephenyl) methane, 2,2-bis (4-cyanatephenyl) propane, 2,2-bis (3,5-dibromo-4- Cyanatephenyl) propane, bis (4-cyanatephenyl) ether, bis (4-cyanatephenyl) thioether, bis (4-cyanatephenyl) sulfone, tris (4-cyanatephenyl) phosphite, tris ( And cyanates obtained by the reaction of 4-cyanate fail) phosphate and novolac and cyanide halide.

In addition to this, Japan Commando 41-11712, Japan Commando 43-18468, Japan Commando 44-4791, Japan Commando 45-11712, Japan Commando 46-41112, Japan Commando Cyanic acid esters described in Japanese Patent Application Laid-Open No. 47-26853 and Japanese Patent Laid-Open No. 51-63149 can also be used.

In addition, preporima having a molecular weight of 400 to 6000 having a triazine ring formed by trimerization of the cyanate group of the cyanate ester compound may be used. For example, the preformima can be formed by polymerizing the cyanate ester monomer with a catalyst such as an acid such as an inorganic acid or Lewis acid, bases such as sodium alcohol, tertiary amines, and salts such as sodium carbonate as a catalyst. . However, it is a matter of course that the preformima can be formed by various other methods. Since this preporima also contains an unreacted monomer, it has a form of a mixture of a monomer and preporima, and can be suitably used as the thermosetting resin of the present invention.

Moreover, liquid cyanate esters can be used. In addition, although a fluorine additive and phosphorus containing etc. can also be used, in order to form with non-halogen, a fluorine additive is not used.

Thermoplastic resins include liquid crystal polyester resins. This liquid crystal polyester resin can be applied to printed circuit boards for high frequency and can contribute to improving high frequency characteristics.

Various additives can be added to the thermosetting resin and the thermoplastic resin. For example, organic fillers, inorganic fillers, dyes, pigments, thickeners, lubricants, defoamers, dispersants, leveling agents, photosensitizers, brighteners, polymerization initiators, thixotropic agents, and the like are suitably blended according to the purpose and use. As the thermosetting resin and the thermoplastic resin, those which are not flame retardant may be used, but those which are flame retarded with phosphorus, fluorine, or the like and which have a non-halogen flame retardant added thereto may be used.

In addition, a curing agent, a catalyst, and the like can be added to the thermosetting resin in consideration of workability, economical efficiency, and the like. The addition amount of the curing agent, the catalyst and the like is preferably 0.005 to 10 parts by weight, more preferably 0.01 to 5 parts by weight based on 100 parts by weight of the thermosetting resin. If too much material is added, the cost may be increased and the physical properties may be degraded. In addition, if too little of the above materials are added, the reaction rate may be slow and may not be completely cured. However, the present invention is not limited thereto, and it is also possible not to add a curing agent, a catalyst, or the like, which also belongs to the scope of the present invention.

On the other hand, as a base material for forming the prepreg to be used as the insulating layer 10, a glass cloth, an organic cloth, an inorganic cloth and a mixture of these can be used. As the glass cloth, a glass cloth or a glass nonwoven fabric using fibers such as E, T (S), NE, E, or quartz may be used. As organic foam, liquid crystalline polyester, wholly aromatic, polyoxybenzazole, and these mixtures can be used. In order to improve rigidity, a glass woven fabric can be laminated and used in multiple layers.

As a heat resistant film used as the insulating layer 10, a polyimide film, a wholly aromatic polyamide film, a liquid crystal polyester film, etc. are mentioned.

As described above, in the present invention, various materials may be used as the insulating layer 10, and it is preferable to select and use an appropriate material in consideration of the use of the printed circuit board. For example, when a printed circuit board is used for high frequency, it is preferable to use a cyanate ester resin and a functional group-added polyphenylene ether resin as the insulating layer 10 for low dielectric properties. At high frequency of 20 GHz or more, it is preferable to use cyanate ester resin alone or to use liquid crystal polyester resin cloth instead of glass cloth as the base material in order to reduce transmission loss.

The insulating layer 10 preferably has a melting point of 270 ° C. or higher to withstand heat in the process. However, the present invention is not limited thereto.

In addition, the insulating layer 10 preferably has a thickness of 3 μm to 200 μm, and preferably has a thickness of 20 μm to 70 μm. When the thickness of the insulating layer 10 is too thin, when the via hole is filled with the insulating layer, the via hole may not be sufficiently filled and the circuit layer may not be sufficiently covered with the insulating layer. In addition, if the thickness of the insulating layer 10 is too thick, it is difficult to thin the printed circuit board. That is, the thickness of the insulating layer 10 is appropriately defined in consideration of these points. However, the present invention is not limited thereto, and the thickness of the insulating layer 10 may be changed by the use of the printed circuit board and the development of technology.

Subsequently, as shown in FIG. 1B, a release film 20 is prepared.

In this case, the release film 20 includes an uneven surface forming layer 24 having an uneven surface 22 and a reinforcing layer 26 physically reinforcing the uneven surface forming layer 24.

Here, the concave-convex forming layer 24 may be formed of a resin layer in which a release agent is added to the thermosetting resin. As the thermosetting resin, any one or two or more of the various materials described in the insulating layer 10 may be used. Although the thickness of the concave-convex forming layer 24 is not particularly limited to a certain thickness, it is preferable to have a thickness of 10 μm to 50 μm, more preferably 20 μm to 30 μm in consideration of workability and economical efficiency. .

The concave-convex surface 22 formed on the concave-convex forming layer 24 may be formed using sand blast, chemical treatment, a mold, or the like. At this time, the uneven surface 22 may have a 10-point average roughness of the 10-point average roughness (Rz) of 2㎛ to 10㎛. If the ten-point average roughness of the uneven surface 22 exceeds 10㎛, it is difficult to form a fine circuit, if less than 2㎛ because the adhesive force may be insufficient. In consideration of this, the ten-point average roughness of the uneven surface 22 is more preferably 3 μm to 9 μm.

In addition, the reinforcement layer 26 may be made of aluminum, iron, copper, or the like so as to physically reinforce the concave-convex forming layer 24. At this time, although not particularly limited, the reinforcing layer 26 preferably has a thickness of 10 μm to 35 μm.

In the above, the release film 20 including both the concave-convex forming layer 24 and the metal layer 26 is illustrated and described, but the present invention is not limited thereto. Accordingly, as shown in FIG. 2, the uneven surface may be formed on the insulating layer using the release film 120 having only the uneven surface forming layer 124 having the uneven surface 122 formed therein, which is also the scope of the present invention. Belongs to. In this case, the concave-convex forming layer 124 may include a thermosetting resin such as a release polyester film, a release fluororesin film, or a resin layer in which a release agent is added to the thermosetting resin as described above.

Subsequently, as shown in FIGS. 1C to 1E, the uneven surface 12 is formed in the insulating layer 10. That is, as shown in FIG. 1C, after placing the release film 20 on each side of the insulating layer 10 so that the uneven surface 22 faces the insulating layer 10, as shown in FIG. 1D. After pressing and heating, the release film 20 is attached to the insulating layer 10, and as shown in FIG. 1E, the release film 20 is peeled off. The uneven surface 12 is formed on the insulating layer 10 in a semi-cured state by the uneven surface 22 of the release film 20.

When the release film 20 is attached to the insulating layer 10, it is preferable to cure the insulating layer 10 to about 50% to 90%. However, the present invention is not limited thereto, and the degree of curing of the insulating layer 10 at this stage may vary.

Here, when the insulating layer 10 consists of a thermosetting resin, it is preferable that the temperature at the time of lamination | stacking is 100 degreeC-300 degreeC, and it is more preferable that it is 110 degreeC-250 degreeC. The pressure applied to the insulating layer 10 and the release film 20 is preferably 1 kgf / cm ² to 50 kgf / cm ² . It is preferable that heating and pressurization time are 5 minutes-120 minutes, and a degree of vacuum is 30 mmHg or less, More preferably, it is 10 mmHg or less. However, the present invention is not limited to these process conditions and may be changed according to the type of thermosetting resin.

When the insulating layer 10 consists of liquid crystalline polyester resin, it is preferable that the temperature at the time of lamination | stacking is more than melting | fusing point of liquid crystalline polyester resin, and it is preferable that it is temperature which is about 10 degreeC-about 50 degreeC higher than melting | fusing point. The insulating layer 10 and the release film 20 are preferably pressed at 1 kgf / cm ² to 50 kgf / cm ² , and more preferably at about 5 kgf / cm ² to 30 kgf / cm ² . It is preferable that heating and pressurization time are 2 minutes-40 minutes, and it is preferable that lamination is performed in a vacuum state.

Subsequently, as shown in FIG. 1F, a via hole 14 penetrating the insulating layer 10 is formed and a desmear process is performed. Although the via hole 14 is a through hole penetrating the insulating layer 10 in the drawing, the insulating layer 10 covers an insulating layer other than the core layer, that is, a circuit layer (not shown) in a multilayer printed circuit board. In the case of the insulating layer formed, blind via holes and through holes may be formed through the via holes 14, which are also within the scope of the present invention.

In order to form the through-hole, a computer numerical control (CNC) drill may be used, or a carbon dioxide (CO ₂ ) laser, a UV-YAG laser, a UV-vanadate laser, or the like may be used. In the case of using a CNC drill, the rotational speed is preferably 80,000 rpm to 300,000 rpm, and the diameter of the through hole is about 70 μm to 1.0 mm. When using a carbon dioxide laser, the through hole has a diameter of about 80 μm to 150 μm, and when using a UV-YAG laser or a UV-vanadate laser, the diameter is about 20 μm to 100 μm.

In order to form a blind via hole, a carbon dioxide laser, a UV-YAG laser, a UV-vanadate laser, or the like can be used. When using a carbon dioxide laser, the diameter of the blind via hole is about 60 µm to 150 µm, and when using a UV-YAG laser or a UV-vanadate laser, the diameter of the blind via hole is about 20 µm to 100 µm.

It is also possible to use the above apparatus and methods in combination to form through holes and blind via holes, and further suitable auxiliary materials may be used.

Subsequently, as illustrated in FIGS. 1G to 1K, the circuit layer 30 is formed on the uneven surface 12 of the insulating layer 10. This is explained in more detail.

As shown in FIG. 1G, electroless copper plating is performed to form the electroless copper plating layer 32a on the uneven surface 12 of the insulating layer 10 and on the inner surface of the via hole 14. Here, the thickness of the electroless copper plating layer 32a is preferably 0.3 µm to 1.5 µm, and preferably 0.7 µm to 1.0 µm. If the thickness of the electroless copper plating layer 32a is too thin, a defect may occur, and if too thick, it may be disadvantageous in terms of time. However, the present invention is not limited to this thickness.

As shown in FIG. 1H, the plating resist 40 of a predetermined pattern is formed. The plating resist 40 has a pattern for exposing a circuit pattern, and the plating resist 40 may be formed by a photolithography method using a photosensitive material.

As shown in FIG. 1I, electrolytic copper plating is performed to form an electrolytic copper plating layer 34 on the exposed portion of the plating resist 40. In consideration of productivity and electrical properties, the thickness of the electrolytic copper plating layer 34 is preferably 15 μm to 25 μm. However, the present invention is not limited to this thickness.

Filling the via holes 14 together in this electrolytic copper plating step is preferable in terms of productivity. However, the present invention is not limited thereto, and the via hole 14 may be filled with a resin or the like by a separate process.

As shown in FIG. 1J, the plating resist 40 is removed.

As shown in FIG. 1K, a portion of the electroless copper plating layer 32a in which the electrolytic copper plating layer 34 is not formed is removed by flash etching or the like to constitute the electroless copper plating layer 32 and the electrolytic copper plating layer 34. The circuit layer 30 is formed. It is preferable to perform black copper oxide treatment, CZ treatment, or the like on the circuit layer 30 by surface treatment.

A separate insulating layer (not shown) is formed over the circuit layer 30, and a via hole (not shown) such as a through hole or a blind via hole is formed in the separate insulating layer (not shown), and then separately The desired number of circuit layers can be formed by repeating the process of forming the circuit layers (not shown).

Subsequently, as shown in FIG. 1L, the solder resist 50 is formed while covering the circuit layer 30. Solder resist 50 has only an opening to be connected to the outside for power supply and signal exchange.

Subsequently, as shown in FIG. 1M, the nickel plating layer 36 and the gold plating layer 37 are sequentially formed in the opened portion of the solder resist 50.

A semiconductor chip or the like is mounted on the printed circuit board manufactured using wire bonding or flip chip bonding. In wire bonding, a mold resin or potting is used, and in flip chip bonding, an underfill resin is injected between a flip chip and a printed circuit board to be cured.

According to the method of manufacturing a printed circuit board according to the present invention, since the uneven surface 12 is formed on the insulating layer 10, the adhesion between the insulating layer 10 and the circuit layer 30 can be improved. Thereby, peeling of the circuit layer 30 can be prevented. In addition, since the constituent material of the insulating layer 10 is not limited to a material capable of improving adhesion to the circuit layer 30, the insulating layer 10 may be formed of various materials. Therefore, by using various thermosetting resins, which cannot be used for adhesion between the insulating layer 10 and the circuit layer 30, heat resistance, chemical resistance, and migration resistance after moisture absorption can be improved and transmission loss can be reduced. . In addition, it is possible to add a sufficient inorganic filler to improve the rigidity can minimize the bending or twisting of the printed circuit board. The manufacture of high frequency printed circuit boards is also easy.

In this case, since the uneven surface 12 is formed on the insulating layer 10 by using the release film 20, the process can be simplified, and since the etching process is not used, the stability is very excellent.

In addition, since the circuit layer 30 is formed in a state in which no copper foil other than the copper plating layer is present, the thickness can be reduced during etching, and since the semi-additive method is used, it is advantageous for miniaturizing the circuit pattern of the circuit layer 30. Do.

Hereinafter, another method of forming the circuit layer 30 will be described in detail with reference to FIGS. 3A to 3C. 3A to 3C are cross-sectional views showing another method of forming a circuit layer in the present invention.

In the method shown in Figs. 3A to 3C, detailed descriptions of parts identical or similar to those shown in Figs. 1G to 1K will be omitted.

As shown in FIG. 3A, a plating resist 40 ′ of a predetermined pattern is formed.

As shown in FIG. 3B, an electroless copper plating layer 32 'and an electrolytic copper plating layer 34' are sequentially formed on the exposed portions of the plating resist 40 '. In this case, the via hole 14 may be filled together when the electrolytic copper plating layer 34 ′ is formed.

As shown in FIG. 3C, the plating resist 40 ′ is removed to complete the manufacture of the circuit layer 30 composed of the electroless copper plating layer 32 ′ and the electrolytic copper plating layer 34 ′.

Hereinafter, embodiments of the present invention will be described in more detail the present invention. However, the following examples are intended to illustrate the invention, the present invention is not limited to these embodiments.

Example 1

First, a core layer was formed as follows and an uneven surface was formed in this core layer.

Four prepregs (0.1 mm thick and 300 mm x 300 mm) are laminated (trade name: GHPL-832LD, manufacturer: Mitsubishi Gas Chemical Co. Ltd.), and the first release film is provided with the uneven surface facing the prepreg on both sides thereof. (Trade name: Sepanium, manufacturer: Sun Aluminum Ind. Ltd.) was placed. At this time, the 10-point average roughness of the uneven surface was 8.9 µm.

Then, the four prepregs and the first release film were pressed at 25 kgf / cm ² for 90 minutes at 5 ° C. or less and 190 ° C., and the first release film was attached to a core layer made of four prepregs. As a result, an uneven surface was formed in the core layer.

Next, the first release film was peeled off.

Subsequently, the core layer was irradiated with a carbon dioxide laser to form a via hole penetrating the core layer while having a diameter of 100 μm, followed by a desmear process.

Subsequently, a first circuit layer having a width of a circuit pattern of 35 mu m and a circuit pattern of 15 mu m was formed on the core layer, and the first circuit layer was subjected to CZ treatment. At this time, an electroless copper plating layer having a thickness of 0.7 µm was formed, a plating resist was formed, and an electrolytic copper plating layer having a thickness of 21 µm was formed according to the pattern of the plating resist, and then the plating resist was removed and the pattern of the electrolytic copper plating layer was removed. The electroless copper plating was flash etched accordingly to form a first circuit layer.

On the other hand, a buildup layer was formed as follows.

900 parts by weight of 2,2-bis (4-cyanatephenyl) propane and 100 parts by weight of bis (4-maleimidephenyl) methane were dissolved and stirred at 150 ° C to obtain a mixture of preformima and monomers. This mixture was dissolved in a mixed solvent of methyl ethyl ketone and N, N'-dimethylformamide, and 500 parts by weight of a bisphenol A epoxy resin (trade name: Epicoat 1001, manufacturer: Japan Epoxy Resin Co., Ltd.) and cresol novolac epoxy 500 parts by weight of a resin (trade name: ESCN-220 F, manufacturer: Sumitomo Chemical Ind. Ltd.) was added and mixed, and then 1300 parts by weight of a spherical silicate having an average particle size of 0.9 μm was added to the inorganic filler to form a varnish. The varnish was impregnated into a glass woven fabric having a thickness of 20 μm and then dried at 170 ° C. for 160 seconds to form a build up layer having a thickness of 50 μm.

Subsequently, on the both sides of the core layer and the first circuit layer, a second release film having a ten-point average roughness of 3.8 μm of the uneven surface was laminated together with the build-up layer, and 25 kgf / cm ² for 10 minutes at 190 ° C. or less. It pressurized by, and the buildup layer and the 2nd release film were affixed on the core layer and the 1st circuit layer. As a result, an uneven surface was formed in the buildup layer.

Next, the second release film was peeled off.

Subsequently, the build-up layer was irradiated with a UV-vanadate laser to form a blind via hole having a diameter of 50 μm, followed by a desmear process.

Subsequently, a second circuit layer having a width of a circuit pattern of 15 µm and a circuit pattern of 15 µm was formed on the buildup layer, and the second circuit layer was subjected to CZ treatment. At this time, an electroless copper plating layer having a thickness of 0.7 µm was formed, a plating resist was formed, and an electrolytic copper plating layer having a thickness of 21 µm was formed according to the pattern of the plating resist, and then the plating resist was removed and the pattern of the electrolytic copper plating layer was removed. The electroless copper plating was flash etched accordingly to form a second circuit layer.

 Subsequently, the formation process of the said buildup layer and the 2nd circuit layer was repeated, and 6 circuit layers were made in total.

Subsequently, the buildup layer and the release fluorine resin film having a thickness of 25 μm were laminated together on both outer surfaces thereof, and then the release fluorine resin film was peeled off to form a solder resist. A blind via hole was formed in the solder resist so as to correspond to the flip chip connection pad and the hand ball pad using a carbon dioxide laser, and desmearing was performed. A nickel plated layer and a gold plated layer were sequentially formed in the blind via hole to manufacture a printed circuit board. The size of this printed circuit board was 40 mm x 40 mm.

After connecting a 10mm by 10mm flip chip with Pb-free hand reflow at the center of the surface of the printed circuit board, the underfill resin (trade name: CRP4152-D-1, manufacturer: Sumitomo-Bakelite Co. Ltd.). Ltd.) was poured between the printed circuit board and the semiconductor chip to cure to manufacture a semiconductor package.

Example 2

In the same manner as in Example 1, the core layer having the uneven surface and the build-up were separately formed.

The core layer was irradiated with UV-YAG laser to form via holes penetrating the core layer while having a diameter of 50 μm.

Subsequently, a first circuit layer having a width of a circuit pattern of 15 µm and a circuit pattern of 15 µm was formed on the core layer, and the first circuit layer was subjected to CZ treatment. At this time, a plating resist was formed, an electroless copper plating layer having a thickness of 0.8 mu m and an electrolytic copper plating layer having a thickness of 20 mu m was formed according to the pattern of the plating resist, and then the plating resist was removed to form a first circuit layer. .

Subsequently, a second release film having a ten-point average roughness of 6.0 µm on an uneven surface was laminated on both sides of the core layer and the first circuit layer at 25 kgf / cm ² for 90 minutes at 190 ° C. or less at 10 mmHg or less. Pressurized, the buildup layer and the second release film were attached to the core layer and the first circuit layer. As a result, an uneven surface was formed in the buildup layer.

Next, the second release film was peeled off.

Subsequently, the build-up layer was irradiated with UV-YAG laser to form a blind via hole having a diameter of 50 μm, and then desmearing was performed.

Subsequently, a second circuit layer having a width of 12 占 퐉 and a circuit pattern of 12 占 퐉 was formed on the buildup layer, and the second circuit layer was subjected to CZ treatment. At this time, a plating resist was formed, and an electroless copper plating layer having a thickness of 0.7 µm and an electrolytic copper plating layer having a thickness of 20 µm were formed according to the pattern of the plating resist, and then the plating resist was removed to form a second circuit layer. .

Subsequently, the formation process of the said buildup layer and the 2nd circuit layer was repeated, and 6 circuit layers were made in total.

Subsequently, after laminating together a liquid crystalline polyester resin layer having a melting point of 275 ° C. and a thickness of 30 μm and a release fluorine resin film having a thickness of 25 μm on both outer surfaces thereof, the substrate was pressurized at 15 kgf / cm ² for 20 minutes at 283 ° C. or less. The solder resist was formed. A blind via hole was formed in the solder resist so as to correspond to the flip chip connection pad and the hand ball pad using a carbon dioxide laser, and desmearing was performed. A nickel plated layer and a gold plated layer were sequentially formed in the blind via hole to manufacture a printed circuit board. The prepared printed circuit board was cut into unit objects having a size of 40 mm x 40 mm.

Using this printed circuit board, a semiconductor package was manufactured in the same manner as in Example 1.

Comparative Example 1

The copper foil of the 0.4 mm double-sided companion laminate (trade name: CCL-HL832HS, manufacturer: Mitsubishi Gas Chemical Co. Ltd.) having a 12 μm thick copper foil on both sides was etched to a thickness of 2 μm.

The copper foil laminated plate was irradiated with a carbon dioxide laser to form a via hole penetrating the copper laminated sheet having a diameter of 100 μm, and then desmearing was performed.

Subsequently, a first circuit layer having a width of a circuit pattern of 30 탆 and a circuit pattern of 30 탆 was formed on the core layer, and the first circuit layer was subjected to CZ treatment. In this comparative example, an electroless copper plating layer having a thickness of 0.7 μm and an electrolytic copper plating layer having a thickness of 15 μm were formed, and then a first circuit layer was formed by using a subtractive method.

Subsequently, a buildup layer was formed on the first circuit layer. In this embodiment, the trade name is ABF GX-3 and the manufacturer is Ajinomoto Co. Ltd. Inc., the resin sheet for the semi-additive was laminated on the first circuit layer, pressurized at 5kgf / cm ² for 1 minute at 100 ° C or less, 5 mmHg, peeled off the polyethylene terephthalate film and then 30 minutes at 100 ° C, Curing in an oven at 170 ° C. for 30 minutes yielded a buildup layer.

Subsequently, the build-up layer was irradiated with UV-YAG laser to form a blind via hole having a diameter of 50 μm, and then desmearing was performed.

Subsequently, a second circuit layer having a width of a circuit pattern of 15 µm and a circuit pattern of 15 µm was formed on the buildup layer, and the second circuit layer was subjected to CZ treatment. At this time, an electroless copper plating layer having a thickness of 0.7 µm was formed, a plating resist was formed, and an electrolytic copper plating layer having a thickness of 21 µm was formed according to the pattern of the plating resist, and then the plating resist was removed and the pattern of the electrolytic copper plating layer was removed. The electroless copper plating was flash etched accordingly to form a second circuit layer. When forming the electrolytic copper plating layer, blind via holes were filled with electrolytic copper plating.

Subsequently, the formation process of the said buildup layer and the 2nd circuit layer was repeated, and 6 circuit layers were made in total.

Subsequently, a liquid UV selective thermosetting solder resist (trade name: PSR4000AUS5, manufactured by Taiyo Ink MFG Co. Ltd.) was applied to the outer surfaces of both sides thereof to a thickness of 20 μm, and then dried, exposed, developed and cured to form a solder resist. It was. A blind via hole was formed in the solder resist so as to correspond to the flip chip connection pad and the hand ball pad using a carbon dioxide laser, and desmearing was performed. A nickel plated layer and a gold plated layer were sequentially formed in the blind via hole to manufacture a printed circuit board. The prepared printed circuit board was cut into unit objects having a size of 40 mm x 40 mm.

Using this printed circuit board, a semiconductor package was manufactured in the same manner as in Example 1.

Comparative Example 2

The brand name is IDL-322, and the manufacturer is JSR Co. Ltd. was used as a semi-additive resin and a printed circuit board and a semiconductor package were manufactured in the same manner as in Comparative Example 1 except that the build-up layer was formed to a thickness of 25 μm.

Comparative Example 3

A core layer was formed in the same manner as in Example 2 except that the 10-point average roughness of the uneven surface of the first release film was 1 μm when forming the uneven surface. Then, a first circuit layer was manufactured in this core layer in the same manner as in Example 2.

Subsequently, on the core layer and the first circuit layer, a second release film having a 10-micron average roughness of 1 μm on the uneven surface was laminated together with a build-up layer having a thickness of 50 μm made of FR-5 flame retarded. And cured under vacuum for 90 minutes to form an uneven surface in the buildup layer.

Next, the second release film was peeled off.

Subsequently, the build-up layer was irradiated with UV-YAG laser to form a blind via hole having a diameter of 50 μm, and then desmearing was performed.

Subsequently, a second circuit layer having a width of a circuit pattern of 15 µm and a circuit pattern of 15 µm was formed on the buildup layer, and the second circuit layer was subjected to CZ treatment. At this time, a plating resist was formed, and an electroless copper plating layer having a thickness of 0.7 µm and an electrolytic copper plating layer having a thickness of 21 µm were formed according to the pattern of the plating resist, and then the plating resist was removed to form a second circuit layer. . At this time, part of peeling of the second circuit layer occurred.

Subsequently, the formation process of the said buildup layer and the 2nd circuit layer was repeated, and 6 circuit layers were made in total.

Subsequently, a solder resist, a blind via hole, a nickel plating layer, and a gold plating layer were formed in the same manner as in Comparative Example 1 to manufacture a printed circuit board. A semiconductor package was manufactured in the same manner as in Comparative Example 1 using the printed circuit board. It was.

Comparative Example 4

When forming the concave-convex surface on the core layer, a printed circuit board and a semiconductor package were manufactured in the same manner as in Example 1, except that a release film having a ten-point average roughness of the concave-convex surface was used.

In this case, undercut occurred in the circuit pattern, and a circuit pattern of uniform shape could not be obtained. In addition, a phenomenon in which the plating resist was partially removed in the uneven portion without being completely removed, and a part of the circuit pattern was peeled off.

In the above examples and comparative examples, the following items were examined and measured.

(1) Whether the first circuit layer is peeled off

After the formation of the second insulating layer, whether the first circuit layer was peeled off was examined, and the results are shown in Table 1 (1).

 (2) Whether the circuit layer is peeled off during the process

After carrying out the entire process, it was examined whether the circuit layer was peeled off, and the results are shown in Table 1 (2).

(3) Whether the circuit layer is defective

After forming a first circuit layer having a width of a circuit pattern of 15 µm and a gap of 15 µm between circuit patterns, the defects of the first circuit layer were examined, and the results are shown in Table 1 (3). However, as described above, in Comparative Example 1, the first circuit layer was manufactured to have a width of a circuit pattern of 30 μm and a space between circuit patterns of 30 μm. For comparison, for Comparative Example 1, a first circuit layer having a width of 15 μm and a distance between circuit patterns 15 μm was manufactured in the same manner as in Comparative Example 1, and then inspected for defects. This is shown in the corresponding part of Table 1.

(4) degree of warping and twisting

After the manufacturing of the printed circuit board is completed (a), the flip chip is connected to the printed circuit board (b), and the underfill resin is filled and cured to complete the semiconductor package manufacturing. Each measurement was carried out in c) and the results are shown in Table 1 (4).

(5) heat resistance after moisture absorption

The printed circuit board was treated at 2.1 atm and 121 ° C. for 2 hours, taken out, and immersed in a 260 ° C. hand bath for 30 seconds to see if it swelled. The number of printed circuit boards that swelled in each of the 100 printed circuit boards is shown in Table 1 (5).

(6) chemical resistance

The circuit layer was immersed in 20% HCl solution in a state where no solder resist was formed on the surface, washed with water, dried at 125 ° C. for 24 hours, and weighed, and the weight change is shown in Table 1 below. The same experiment was carried out in 20% NaOH solution, and the change in weight is shown in Table 6 (6).

(7) transmission loss

Using a microstrip line at the outermost layer, an insulation layer having a thickness of 50 ± 7 μm, a line having a width of 25 ± 5 μm and a thickness of 20 ± 4 μm was measured, and the transmission loss at 25 GHz was measured. It is shown in (7).

(8) migration resistance

The migration resistance between the inner circuit layers and the migration resistance between the outermost circuit layers were examined while applying a DC voltage of 70V. For this purpose, the insulation resistance value after the first, 200 hours and 600 hours was measured, and the results are shown in Table 1 (8).

Referring to Table 1 (1) to (3), the embodiments can prevent the problem of peeling the circuit layer and excellent characteristics compared to the comparative examples in that no defect occurs in the circuit layer even if the circuit pattern is miniaturized It can be seen that it has. In particular, in Comparative Example 4, since it was not possible to obtain a uniform circuit pattern, it was found that even measurement of each value was impossible.

Referring to Table 1 (4), it can be seen that the degree of warpage and twist are significantly smaller than those of the comparative examples.

Referring to Table 1 (5), it can be seen that the Examples did not occur swelling at all, but the swelling phenomenon occurs in a very large number in the comparative examples. That is, the examples can be seen that the heat resistance after the moisture absorption is superior to the comparative examples.

Referring to Table 1 (6), it can be seen that the examples have a weight change rate of only 0.2% to 0.6% while the comparative examples have a very large weight change rate of 3.0% to 7.3%. That is, it can be seen that the chemical resistance of the embodiments is better.

Referring to (1) of Table 1, it can be seen that the embodiments have very large values of transmission loss of 21 to 39 while the transmission examples have only 4 to 9 transmission loss. As described above, it can be seen that the transmission loss can be greatly reduced in this embodiment.

Referring to Table 1 (8), it can be seen that the Examples do not significantly change the insulation resistance value over time, while the Comparative Examples are lowered to 10 ⁸ kPa or less, and the insulation resistance value is greatly changed. From these results, it can be seen that the examples have better migration resistance than the comparative examples.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and the present invention may be modified or modified in various ways within the scope of the claims and the detailed description of the invention and the accompanying drawings. Naturally, it is within the scope of the present invention.

As described above, according to the method of manufacturing a printed circuit board according to the present invention, an uneven surface may be formed on the insulating layer to improve adhesion between the insulating layer and the circuit layer. Thereby, peeling of a circuit layer can be prevented. In addition, since the insulating layer may be formed of various materials, heat resistance, chemical resistance, and migration resistance after moisture absorption may be improved, and transmission loss, bending of the printed circuit board, and twisting may be effectively prevented. It can also be applied to the manufacture of high frequency printed circuit boards. That is, a printed circuit board having excellent characteristics can be manufactured.

In addition, by using the release film, the uneven surface may be formed on the insulating layer by a simple process of attaching and peeling off the release film, thereby simplifying the process. In addition, it is also very excellent in terms of stability compared to the case of using an etching method. That is, it is possible to manufacture a printed circuit board of excellent stability in a simple process.

Moreover, since a circuit layer is formed in the state in which no copper foil other than a copper plating layer exists, the circuit pattern of a circuit layer can be refined.

Claims (11)

(a) preparing an insulating layer; (b) attaching a release film including an uneven surface on which the uneven surface is formed to the insulating layer, thereby forming the uneven surface on the insulating layer; (c) peeling off the release film; And (d) forming a circuit layer on the uneven surface of the insulating layer Method of manufacturing a printed circuit board comprising a. The method of claim 1, wherein the insulating layer constitutes a core layer or a build-up layer. The method of claim 1, wherein the uneven surface of the release film has a ten point average roughness (Rz) of 2 μm to 10 μm. The method of claim 3, wherein the uneven surface of the release film has a ten point average roughness of 3 μm to 9 μm. The method of claim 1, wherein the release film, The method of manufacturing a printed circuit board further comprising a reinforcing layer attached to the opposite side of the uneven surface of the release film. The method of claim 5, wherein the reinforcement layer comprises a material selected from the group consisting of aluminum, iron, copper, and alloys thereof. The method of claim 1, wherein the unevenness forming layer comprises a material selected from the group consisting of a thermosetting resin, a thermoplastic resin, and a mixed resin thereof. The method of claim 1, wherein the insulating layer comprises a material selected from the group consisting of a thermosetting resin, a thermoplastic resin, and a mixed resin thereof. The method of claim 1, wherein after step (d), A method of manufacturing a printed circuit board, comprising repeating steps (c) and (d) at least once. The method of claim 1, wherein step (d) Forming an electroless copper plating layer on the insulating layer; Forming a plating resist having a predetermined pattern on the electroless copper plating layer; Forming an electrolytic copper plating layer on the electroless copper plating layer according to the pattern of the plating resist; Removing the plating resist; And Removing a portion of the electroless copper plating layer in which the electrolytic copper plating layer is not formed Method of manufacturing a printed circuit board comprising a. The method of claim 1, wherein step (d) Forming a plating resist having a predetermined pattern on the insulating layer; Forming an electroless copper plating layer on the insulating layer according to the pattern of the plating resist; Forming an electrolytic copper plating layer on the electroless copper plating layer according to the pattern of the plating resist; And Removing the plating resist Method of manufacturing a printed circuit board comprising a.

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