KR20090080696A - Multi chip module and manufacturing method thereof - Google Patents

Multi chip module and manufacturing method thereof Download PDF

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KR20090080696A
KR20090080696A KR1020080006599A KR20080006599A KR20090080696A KR 20090080696 A KR20090080696 A KR 20090080696A KR 1020080006599 A KR1020080006599 A KR 1020080006599A KR 20080006599 A KR20080006599 A KR 20080006599A KR 20090080696 A KR20090080696 A KR 20090080696A
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South Korea
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chip
chips
wire
leads
chip module
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KR1020080006599A
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Korean (ko)
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KR101469975B1 (en
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김대훈
양용석
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엘지이노텍 주식회사
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Priority to KR1020080006599A priority Critical patent/KR101469975B1/en
Priority to PCT/KR2009/000223 priority patent/WO2009093825A2/en
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A multi chip module and a manufacturing method thereof are provided to reduce a manufacturing cost of a multi chip module by bonding one or more chips with a lead through a wire. A multi chip module includes a lead frame(100), one or more chips(114,116), at least one or more passive devices(110a,110b,112a,112b), and a wire(118). The lead frame includes a pad and a plurality of leads(106). The chips are positioned on a top surface of the pad. The passive devices are positioned on a top surface of a plurality of leads. The wire electrically connects one or more chips to the lead.

Description

멀티 칩 모듈 및 그 제조방법{Multi chip module and manufacturing method thereof} Multi chip module and manufacturing method thereof

본 발명은 멀티 칩 모듈 및 그 제조방법에 관한 것이다.The present invention relates to a multi-chip module and a method of manufacturing the same.

일반적으로, 멀티 칩 모듈(MCM)은 사용하는 베이스 기판의 종류에 따라 MCM-L, MCM-C 및 MCM-D로 구분된다.In general, the multi-chip module (MCM) is divided into MCM-L, MCM-C and MCM-D according to the type of base substrate used.

MCM-L은 일반 인쇄회로기판(PCB)의 재료인 FR4를 베이스 기판 재료로 사용하며, 고속을 필요로 하지 않고 가격이 비싸지 않으면서 열 방출이 크지 않는 100MHz 이하의 시스템에 활용되고, MCM-D는 베이스 기판으로 실리콘이나 세라믹을 사용하며, 반도체 공정을 적용하므로 배선 밀도가 높으면서 고속, 고열 및 고성능을 필요로 하는 전자 장비에 활용된다.MCM-L uses FR4, which is a material of general printed circuit board (PCB), as a base substrate material, and is used for systems of 100MHz or less, which do not require high speed, inexpensive, and do not have high heat dissipation, and MCM-D Since silicon or ceramic is used as the base substrate and semiconductor process is applied, it is used for electronic equipment requiring high speed, high temperature, and high performance with high wiring density.

그리고, MCM-C는 배선 밀도가 MCM-L 수준이나 세라믹을 베이스 기판으로 사용하므로 방열 특성이 좋다.In addition, MCM-C has good heat dissipation characteristics because the wiring density is MCM-L level or ceramic is used as the base substrate.

한편, 멀티 칩 모듈은 내부에 반도체 웨이퍼(Wafer) 이외에도 수동 소자(저항, 커패시터, 인덕터) 등이 포함되어 하나의 시스템(System)을 갖추게 되고, 이러한, 멀티 칩 모듈(MCM)은 반도체 패키지(package) 전용 기판(Substrate) 위에 회로 연결을 위한 각종 전기적 결선과 부품실장용 패드(Pad) 등이 구현되고 그 위에 SMT(Surface Mount Technology) 공정을 통하여 부품실장 후 각종 반도체 패키징(packageing) 공정을 통하여 완성된다.On the other hand, the multi-chip module includes a passive element (resistance, capacitor, inductor) in addition to the semiconductor wafer (Wafer) to have a system (System), such a multi-chip module (MCM) is a semiconductor package (package) ) Various electrical connections for circuit connection and pads for component mounting are implemented on a dedicated substrate and completed through various semiconductor packaging processes after component mounting through SMT (Surface Mount Technology) process. do.

이러한, 멀티 칩 모듈은 소형화, 고속화 및 고신뢰성의 장점을 갖고 있어 중대형 컴퓨터, 위크스테이션, 통신 시스템, 휴대용 단말기, 자동차, 군수 장비 등의 전자 장비에 널리 활용되고 있는 패키지 기술이다.The multi-chip module is a package technology that is widely used in electronic equipment such as medium and large computers, weak stations, communication systems, portable terminals, automobiles, military equipment, etc. because of the advantages of miniaturization, high speed, and high reliability.

그러나, 종래 기술의 멀티 칩 모듈은 고가의 기판(substrate)과 BGA(Ball Grid Array) 나 LGA(Land Grid Array) 타입(type)의 반도체 패키지로 구현해야 하는 한계점과 이에 따라 멀티 칩 모듈의 제조원가가 상승하는 문제가 있다.However, the conventional multi-chip module has a limitation in that it must be implemented in an expensive substrate, a ball grid array (BGA) or a land grid array (LGA) type semiconductor package, and accordingly, the manufacturing cost of the multi-chip module There is a rising problem.

본 발명의 실시예는 멀티 칩 모듈의 제조단가를 낮춘다.Embodiment of the present invention lowers the manufacturing cost of the multi-chip module.

본 발명의 실시예는 리드 프레임의 다수의 리드 상면에 상기 다수의 리드를 전기적으로 연결되도록 적어도 하나 이상의 수동 소자가 실장되는 단계와, 상기 리드 프레임의 패드에 제1 칩 또는 제2 칩을 실장하는 단계와, 상기 제1 칩 또는 상기 제2 칩과 상기 리드를 와이어로 와이어 본딩하는 단계를 포함한다.According to an embodiment of the present invention, at least one passive element is mounted on a plurality of lead upper surfaces of a lead frame to electrically connect the plurality of leads, and a first chip or a second chip is mounted on a pad of the lead frame. And wire bonding the first chip or the second chip and the lead with a wire.

본 발명은 멀티 칩 모듈 제조 단가를 낮출 수 있다.The present invention can lower the manufacturing cost of the multi-chip module.

본 발명의 실시예는 패드 및 다수의 리드를 포함하는 리드 프레임와, 상기 패드 상면에 위치한 하나 또는 그 이상의 칩과, 상기 다수의 리드 상면에 위치한 적어도 하나 이상의 수동소자들과, 상기 하나 또는 그 이상의 칩과 상기 리드를 전기적으로 연결시키는 와이어를 포함한다.An embodiment of the present invention provides a lead frame including a pad and a plurality of leads, one or more chips located on an upper surface of the pad, at least one passive element located on an upper surface of the plurality of leads, and the one or more chips. And a wire for electrically connecting the lead.

본 발명의 실시예에서 상기 패드, 상기 하나 또는 그 이상의 칩, 상기 와이어 및 상기 수동소자들을 내부에 포함시키고 아울러, 상기 리드의 일부를 내부에 포함시킨다.In an embodiment of the present invention, the pad, the one or more chips, the wire and the passive elements are included therein, and a part of the lead is included therein.

또한, 본 발명의 실시예에서 상기 와이어는 금으로 이루어지고, 상기 수동소자는 은 에폭시(Ag epoxy)를 이용하여 상기 다수의 리드 상면에 실장된다.In addition, in the embodiment of the present invention, the wire is made of gold, and the passive element is mounted on the upper surface of the plurality of leads using silver epoxy (Ag epoxy).

또한, 본 발명의 실시예에서 상기 하나 또는 그 이상의 칩은 제1 칩 및 상기 제1 칩보다 작고 상기 제1 칩의 상면에 부착되는 제2 칩을 포함한다.Further, in one embodiment of the present invention, the one or more chips include a first chip and a second chip smaller than the first chip and attached to an upper surface of the first chip.

또한, 본 발명의 실시예는 리드 프레임의 다수의 리드 상면에 상기 다수의 리드를 전기적으로 연결되도록 적어도 하나 이상의 수동 소자를 실장하는 단계와, 상기 리드 프레임의 패드에 하나 또는 그 이상의 칩을 실장하는 단계와, 상기 하나 또는 그 이상의 칩과 상기 리드를 와이어로 와이어 본딩하는 단계를 포함한다.In addition, an embodiment of the present invention comprises the steps of mounting at least one passive element to electrically connect the plurality of leads on the upper surface of the plurality of leads of the lead frame, and mounting one or more chips on the pad of the lead frame And wire bonding the one or more chips and the leads with wires.

본 발명의 실시예에서 상기 패드, 상기 하나 또는 그 이상의 칩, 상기 와이어 및 상기 수동소자들을 내부에 포함시키고 아울러, 상기 리드의 일부를 내부에 포함시키는 몰딩부를 형성하는 단계를 더 포함한다.In an embodiment of the present invention, the method may further include forming a molding part including the pad, the one or more chips, the wire, and the passive elements therein, and including a portion of the lead therein.

또한, 본 발명의 실시예에서 상기 리드 프레임의 프레임 몸체를 절단하는 공정을 수행하는 단계를 포함한다.In addition, the embodiment of the present invention includes the step of performing a process of cutting the frame body of the lead frame.

이하, 본 발명의 바람직한 실시예를 첨부된 도면들을 참조하여 상세히 설명한다. 또한, 본 발명을 설명함에 있어, 관련된 공지 구성 또는 기능에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명은 생략한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

실시예Example

도 1은 본 발명의 실시예에 따른 멀티 칩 모듈의 회로도이다.1 is a circuit diagram of a multi-chip module according to an embodiment of the present invention.

도 1에서 나타낸 바와 같이, 멀티 칩 모듈은 제1 칩(116), 제2 칩(114) 및 수동소자들(110a)(110b)(112a)(112b)로 이루어진다.As shown in FIG. 1, the multi-chip module includes a first chip 116, a second chip 114, and passive elements 110a, 110b, 112a and 112b.

제1 칩(116)의 전원단자(Vcc)는 전원부(Vcc)와 연결되고, 입출력 단 자(DA2)(DA1)들은 일측의 제1 수동소자(R1)(110a) 및 제2 수동소자(R2)(110b)와 각각 연결되며, 다른 입출력 단자(ADD3 내지 ADD1)들은 제2 칩(114)의 입출력단자(ADD1 내지 ADD3)들과 각각 연결된다.The power supply terminal Vcc of the first chip 116 is connected to the power supply unit Vcc, and the input / output terminals DA2 and DA1 are connected to the first passive element R1 110a and the second passive element R2 on one side. ) 110b, respectively, and the other input / output terminals ADD3 to ADD1 are connected to the input / output terminals ADD1 to ADD3 of the second chip 114, respectively.

제2 칩(114)의 입출력 단자(ADD1 내지 ADD3)들은 제1 칩(116)의 입출력 단자(ADD3 내지 ADD1)들과 각각 연결되고, 다른 입출력 단자(DQ1)(DQ2)들은 다른 일측의 제1 수동소자(R1)(110a) 및 제2 수동소자(R2)(110b)와 각각 연결되며, 전원단자(Vcc)는 전원부(Vcc)와 연결되고 아울러, 제3 수동소자(C2)(112a) 및 제4 수동 소자(C1)(112b)와 병렬로 연결된다.The input / output terminals ADD1 to ADD3 of the second chip 114 are connected to the input / output terminals ADD3 to ADD1 of the first chip 116, respectively, and the other input / output terminals DQ1 and DQ2 are the first on the other side. It is connected to the passive element (R1) (110a) and the second passive element (R2) (110b), respectively, the power supply terminal (Vcc) is connected to the power supply (Vcc), and the third passive element (C2) 112a and It is connected in parallel with the fourth passive element (C1) 112b.

여기서, 제2 칩(114)은 제1 칩(116)보다 작게 형성되는 것이 바람직하고, 제3 수동소자(C2)(112a) 및 제4 수동소자(C1)(112b)의 다른 일측은 기준단자와 연결된다.Here, the second chip 114 is preferably formed smaller than the first chip 116, the other side of the third passive element (C2) 112a and the fourth passive element (C1) 112b is a reference terminal. Connected with

여기서, 수동소자(110a)(110b)(112a)(112b)는 저항, 인덕터, 커패시터들 중에서 적어도 하나 이상일 수 있다.Here, the passive elements 110a, 110b, 112a, and 112b may be at least one of resistors, inductors, and capacitors.

도 2a 내지 도 4b는 본 발명의 실시예에 따른 멀티 칩 모듈에 대한 제조공정을 설명하기 위한 상면도 및 단면도이다.2A to 4B are top and cross-sectional views illustrating a manufacturing process of a multichip module according to an exemplary embodiment of the present invention.

도 2a 및 도 2b에서 나타낸 바와 같이, 프레임 몸체(108), 프레임 몸체(108) 중앙에 형성된 패드(102), 패드(102) 외측을 둘러싸도록 형성된 다수의 리드(106) 및 패드(102)와 프레임 몸체(108)를 연결시켜 패드(102)를 지지해 주는 타이바(Tie bar)(104)로 이루어진 리프 프레임(100)의 한 쌍의 리드(106) 상면에 수동소자(110a)(110b)(112a)(112b)들을 실장하여 한 쌍의 리드(106)들을 전기적으로 연결 시킨다.As shown in FIGS. 2A and 2B, the frame body 108, the pads 102 formed at the center of the frame body 108, a plurality of leads 106 and the pads 102 formed to surround the outside of the pads 102, and Passive elements 110a and 110b on the upper surface of the pair of leads 106 of the leaf frame 100 formed of tie bars 104 that connect the frame body 108 to support the pads 102. The pair of leads 106 may be electrically connected by mounting the 112a and 112b.

여기서, 수동소자(110a)(110b)(112a)(112b)들은 배어 다이(Bare Die)를 스택(Stack)하기 위한 다이 어태치(die attach) 기법과 동일하게 은 에폭시(Ag epoxy)를 이용하여 다수의 리드(106) 상면에 실장된다.Here, the passive elements 110a, 110b, 112a, and 112b are made of silver epoxy in the same manner as a die attach technique for stacking bare dies. The plurality of leads 106 are mounted on the upper surface.

그리고, 은 에폭시(Ag epoxy)를 이용하여 수동소자(110a)(110b)(112a)(112b)를 다수의 리드(106) 상면에 실장함으로써, 리드 프레임(100)에 대하여 별도의 플럭스(Flux) 세척 공정을 수행하지 않을 수 있다.The passive elements 110a, 110b, 112a, and 112b are mounted on the upper surface of the plurality of leads 106 by using silver epoxy, thereby providing a separate flux to the lead frame 100. The washing process may not be performed.

다음, 도 3a 및 도 3b에서 나타낸 바와 같이, 패드(102) 상면에 제1 칩(114)을 실장하고, 제1 칩(114) 상면에 제1 칩(114)보다 작은 제2 칩(116)을 순차적으로 실장한 후, 와이어 본딩 공정을 통해 와이어(118)로 제1 칩(114) 또는 제2 칩(116)들과 리드(106)를 전기적으로 연결시킨다.Next, as shown in FIGS. 3A and 3B, the first chip 114 is mounted on the pad 102, and the second chip 116 smaller than the first chip 114 is disposed on the top surface of the first chip 114. After sequentially mounting, the first chip 114 or the second chip 116 and the lead 106 are electrically connected to the wire 118 through a wire bonding process.

여기서, 와이어(118)는 전도성 도체들 중에서 금으로 이루어질 수 있다.Here, the wire 118 may be made of gold among the conductive conductors.

이 후, 도 4a 및 도 4b에서 나타낸 바와 같이, 와이어 공정이 수행된 리드 프레임(100)에 대하여 패드(102), 제1 칩(114), 제2 칩(116), 와이어(118)를 내부에 포함시키고 아울러, 리드(106)의 일부가 내부에 포함되도록 하는 몰딩 공정으로 몰딩부(120)를 형성한 후, 리드 프레임(100)의 프레임 몸체(108)에 대하여 절단 공정을 수행하여 멀티 칩 모듈을 완성한다.Thereafter, as shown in FIGS. 4A and 4B, the pad 102, the first chip 114, the second chip 116, and the wire 118 are formed inside the lead frame 100 on which the wire process is performed. After forming the molding unit 120 by a molding process to include in the, and part of the lead 106 is included therein, the cutting process is performed on the frame body 108 of the lead frame 100 to multi-chip Complete the module.

여기서, 멀티 칩 모듈은 상기한 도 1의 몰디 칩 모듈 회로도를 기반으로 형성되는 것이 바람직하다.Here, the multi chip module is preferably formed based on the Maldi chip module circuit diagram of FIG. 1.

이상의 설명은 본 발명의 기술 사상을 예시적으로 설명한 것에 불과한 것으 로서, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자라면 본 발명의 본질적인 특성에서 벗어나지 않는 범위에서 다양한 수정 및 변형이 가능할 것이다. 따라서, 본 발명에 개시된 실시예들은 본 발명의 기술 사상을 한정하기 위한 것이 아니라 설명하기 위한 것이고, 이러한 실시예에 의하여 본 발명의 기술 사상의 범위가 한정되는 것은 아니다. 본 발명의 보호 범위는 아래의 청구범위에 의하여 해석되어야 하며, 그와 동등한 범위 내에 있는 모든 기술 사상은 본 발명의 권리범위에 포함되는 것으로 해석되어야 할 것이다.The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and changes without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the present invention.

도 1은 본 발명의 실시예에 따른 멀티 칩 모듈의 회로도.1 is a circuit diagram of a multi-chip module according to an embodiment of the present invention.

도 2a 내지 도 4b는 본 발명의 실시예에 따른 멀티 칩 모듈에 대한 제조공정을 설명하기 위한 상면도 및 단면도.2A to 4B are top and cross-sectional views illustrating a manufacturing process for a multi-chip module according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

100 : 리드 프레임 104 : 타이바100: lead frame 104: tie bar

106 : 리드 108 : 리드 프레임 몸체106: lead 108: lead frame body

110a : 제1 수동 소자 110b ; 제2 수동소자110a: first passive element 110b; Second passive element

112a : 제3 수동소자 112b : 제4 수동소자112a: third passive element 112b: fourth passive element

114 : 제1 칩 116 : 제2 칩114: first chip 116: second chip

118 : 와이어118: wire

Claims (11)

패드 및 다수의 리드를 포함하는 리드 프레임와,A lead frame comprising a pad and a plurality of leads, 상기 패드 상면에 위치한 하나 또는 그 이상의 칩과,One or more chips on the pad, 상기 다수의 리드 상면에 위치한 적어도 하나 이상의 수동소자들과,At least one passive element located on the plurality of leads; 상기 하나 또는 그 이상의 칩과 상기 리드를 전기적으로 연결시키는 와이어를 포함하는 멀티 칩 모듈.And a wire for electrically connecting the one or more chips and the lead. 제1항에 있어서,The method of claim 1, 상기 패드, 상기 하나 또는 그 이상의 칩, 상기 와이어 및 상기 수동소자들을 내부에 포함시키고 아울러, 상기 리드의 일부를 내부에 포함시키는 몰딩부를 더 포함하는 멀티 칩 모듈.And a molding part including the pad, the one or more chips, the wire, and the passive elements therein, and including a portion of the lead therein. 제1항에 있어서,The method of claim 1, 상기 와이어는 금으로 이루어지는 멀티 칩 모듈.The wire is a multi-chip module made of gold. 제1항에 있어서,The method of claim 1, 상기 수동소자는 은 에폭시(Ag epoxy)를 이용하여 상기 다수의 리드 상면에 실장되는 멀티 칩 모듈.The passive element is a multi-chip module is mounted on the upper surface of the plurality of leads using a silver epoxy (Ag epoxy). 제1항에 있어서,The method of claim 1, 상기 하나 또는 그 이상의 칩은The one or more chips 제1 칩 및 상기 제1 칩보다 작고 상기 제1 칩의 상면에 부착되는 제2 칩을 포함하는 멀티 칩 모듈.And a first chip and a second chip smaller than the first chip and attached to an upper surface of the first chip. 리드 프레임의 다수의 리드 상면에 상기 다수의 리드를 전기적으로 연결되도록 적어도 하나 이상의 수동 소자를 실장하는 단계와,Mounting at least one passive element on the plurality of leads on the lead frame to electrically connect the plurality of leads; 상기 리드 프레임의 패드에 하나 또는 그 이상의 칩을 실장하는 단계와,Mounting one or more chips on a pad of the lead frame; 상기 하나 또는 그 이상의 칩과 상기 리드를 와이어로 와이어 본딩하는 단계를 포함하는 멀티 칩 모듈 제조방법.And wire-bonding the one or more chips and the lead with a wire. 제6항에 있어서,The method of claim 6, 상기 패드, 상기 하나 또는 그 이상의 칩, 상기 와이어 및 상기 수동소자들을 내부에 포함시키고 아울러, 상기 리드의 일부를 내부에 포함시키는 몰딩부를 형성하는 단계를 더 포함하는 멀티 칩 모듈 제조방법.And forming a molding part including the pad, the one or more chips, the wire, and the passive elements therein, and including a part of the lead therein. 제7항에 있어서,The method of claim 7, wherein 상기 리드 프레임의 프레임 몸체를 절단하는 공정을 수행하는 단계를 포함하는 멀티 칩 모듈 제조방법.Multi-chip module manufacturing method comprising the step of cutting the frame body of the lead frame. 제6항에 있어서,The method of claim 6, 상기 수동소자는 은 에폭시(Ag epoxy)를 이용하여 상기 다수의 리드 상면에 실장되는멀티 칩 모듈 제조방법.The passive device is a multi-chip module manufacturing method is mounted on the upper surface of the plurality of leads using silver epoxy (Ag epoxy). 제6항에 있어서,The method of claim 6, 상기 와이어는 금으로 이루어지는 멀티 칩 모듈 제조방법.The wire is a multi-chip module manufacturing method made of gold. 제6항에 있어서,The method of claim 6, 상기 하나 또는 그 이상의 칩은The one or more chips 제1 칩 및 상기 제1 칩보다 작고 상기 제1 칩의 상면에 부착되는 제2 칩을 포함하는 멀티 칩 모듈 제조방법.And a first chip and a second chip smaller than the first chip and attached to an upper surface of the first chip.
KR1020080006599A 2008-01-22 2008-01-22 Multi chip module and manufacturing method thereof KR101469975B1 (en)

Priority Applications (2)

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KR1020080006599A KR101469975B1 (en) 2008-01-22 2008-01-22 Multi chip module and manufacturing method thereof
PCT/KR2009/000223 WO2009093825A2 (en) 2008-01-22 2009-01-15 Semiconductor package and fabricating method thereof

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