JP2001024139A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shrink a package without decreasing the number of grounding of the land of a substrate. SOLUTION: A plurality of leads 8 are connected electrically to a semiconductor pellet 12 in an SOP.IC (a small-outline-package) 18 with wires 14, and the inner section groups and wire 14 groups of each lead 8 are sealed with a resin sealing body 16. A plurality of the leads 8 are combined at every pair of an upper-side lead 8A and a lower-side lead 8B and bonded with insulating films 11, and each upper-lower lead 8A, 8B is bent in a gull-wing shape on the outside of the resin sealing body 16. The first grounding sections (a) formed at the front ends of the upper-side leads 8A on the outside of the resin sealing body 16, and the second grounding sections (b) formed at the front ends of the lower- side leads 8B, are arranged next to one another at the same positions, and insulated electrically, holding isolating sections 11A. Since the area of the plane of the SOP can be reduced without decreasing the number of connection to a printed wiring board, a mounting area on the printed wiring board can be lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor device, and more particularly to a technology for reducing the size of a package without reducing the number of grounding portions between lands of a printed wiring board. , IC).

[0002]

2. Description of the Related Art Small outline packages (hereinafter, referred to as SOPs) and dual SOPs are generally used as packages for standard logic ICs generally used in small electronic devices such as portable personal computers and mobile phones. Inline package (hereinafter referred to as DIP)
Is generally adopted. IC with SOP
(Hereinafter referred to as an SOP IC) includes a semiconductor pellet in which an integrated circuit including a semiconductor element is built, a plurality of leads electrically connected to the semiconductor pellet, an inner portion of the semiconductor pellet and each lead ( (Hereinafter referred to as an inner lead). The outer part of each lead (hereinafter referred to as an outer lead) is bent into a gull-wing shape and surface-mounted on a printed wiring board. It is configured as follows.

[0003] Examples of SOP ICs are described in "VLSI Packaging Technology (Lower)" P82 to P8 issued on May 31, 1993 by Nikkei BP Co., Ltd.
There are four.

[0004]

Recently, small electronic devices such as portable personal computers and portable telephones have been required to be further miniaturized, and accordingly, they have been mounted on these printed circuit boards. It is required to reduce the size of standard logic IC packages. But,
In a conventional SOP IC, the thickness is 0.1 to 0.2.
Since lead groups are formed using lead frames manufactured by pressing or etching metal plates of about mm, there is a limit to the reduction in the size between adjacent leads depending on conditions such as processing accuracy. As a result, there is a limit in reducing the planar area of the resin sealing body.

An object of the present invention is to provide a semiconductor device manufacturing technique capable of reducing the size of a package without reducing the number of grounds to a land of a printed wiring board.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in a semiconductor device, a pair of leads electrically connected to a semiconductor pellet sandwich an insulating film, and a grounding portion of one lead and a grounding portion of the other lead are arranged at the same position. It is characterized by being isolated.

According to the above-mentioned means, since the pair of leads sandwiches the insulating film and the grounding portions of both leads are arranged at the same position, the number of lead outs in the package can be reduced. The planar area of the package can be reduced. On the other hand, since the grounding portions of the pair of leads are both secured, the total number of grounding portions to the printed wiring board, that is, the total number of connections of the semiconductor device does not decrease, and the same total number of connections as before can be secured. .

[0010]

1A and 1B show a mounting state of an SOP IC according to an embodiment of the present invention. FIG. 1A is a plan sectional view of a left half, a bottom view is a right half, and FIG. It is a front sectional view. FIG. 2 et seq. Show an embodiment of the present invention, SOP.I.
It is each explanatory drawing for demonstrating the manufacturing method of C.

As shown in FIG. 1, in the present embodiment, the semiconductor device according to the present invention is configured as an SOP IC. In FIG. 1, an SOP / IC 18 is a semiconductor pellet (hereinafter, referred to as a semiconductor pellet) in which a standard logic circuit is built.
It is called a pellet. ) 12, a plurality of leads 8 are electrically connected to the pellet 12 by wires 14, and the pellet 12, the inner group of the leads 8 and the group of wires 14 are resin-sealed by a resin sealing body 16. Have been. The plurality of leads 8 include an upper lead 8A and a lower lead 8
b and a pair of the upper and lower leads 8A and 8B are bonded to each other by the insulating film 11.
6 and is integrally bent to the gull wing shape outside. The first ground portion a formed at the tip of the upper lead 8A outside the resin sealing body 16 and the second ground portion b formed at the tip of the lower lead 8B are arranged next to each other at the same position. And are electrically insulated from each other with the isolation portion 11A interposed therebetween. And SOP ・ IC
18 is manufactured by the following SOP / IC manufacturing method.

Hereinafter, an embodiment of the present invention will be described.
A method for manufacturing an IC will be described. With this description, the details of the configuration of the SOP IC will be clarified.

The multiple lead frame 1 shown in FIG. 2 is used in the SOP / IC manufacturing method according to the present embodiment. The multiple lead frame 1 is manufactured and prepared in advance in a multiple lead frame manufacturing process.

The multiple lead frame 1 is a thin plate made of a copper (copper or alloy thereof) material such as phosphor bronze or oxygen-free copper, or a thin plate made of an iron (iron or alloy thereof) material such as 42 alloy or Kovar. Is integrally formed by a suitable means such as a punching press process or an etching process. In the multiple lead frame 1, a plurality of unit lead frames 2 are arranged in a line in one direction. However,
The following description and illustration are made for one unit.

The unit lead frame 2 has a pair of outer frames 3 having positioning holes 3a formed therein, and the outer frames 3, 3 extend in parallel at predetermined intervals. A pair of section frames 4 between adjacent unit lead frames 2, 2;
4 are arranged in parallel with each other between the outer frames 3 and 3 and are integrally bridged. The thickness of the section frames 4 and 4 is formed larger than the thickness of the outer frame 3. The unit lead frame 2 is formed in a rectangular frame (frame) formed by the outer frames 3 and 3 and the section frames 4 and 4.

In each unit lead frame 2, a pair of tab suspension leads 5, 5 are arranged on the outer frames 3, 3 at right angles to each other, and are integrally protruded. A tab 6 formed in a rectangular flat plate shape is suspended between the tips of 5. Since the tab suspension lead 5 is bent at the intermediate portion, the tab 6 is lowered in one direction in a state parallel to a lead group described later (so-called tab lowering).

A pair of dam members 7, 7 are provided between the outer frames 3, 3.
Are arranged symmetrically on both sides of the tab 6 and are erected at right angles. A plurality of leads 8 are arranged on both dam members 7 and 7 at equal intervals in the longitudinal direction so as to be orthogonal to the dam member 7. It is projected. The tip of an inner portion (hereinafter, referred to as an inner lead) 9 which is a tab-side end of each lead 8 is close to the tab 6. On the other hand, the tip of an outer portion (hereinafter, referred to as an outer lead) 10 which is an end of the lead 8 on the side opposite to the tab is integrally connected to the section frame 4. Then, the adjacent outer leads 10, 1 in the dam member 7 are formed.
The portion between 0 constitutes a dam 7a for damping the flow of the resin during molding of the resin sealing body.

On the lower surface of each lead 8, a lead (hereinafter, referred to as a lower lead) 8B for constituting a lower lead is provided.
Are adhered by an adhesive for forming the insulating film 11. That is, a lower lead 8B is adhered to the lower surface of each lead (hereinafter, referred to as an upper lead 8A) connected to the section frame 4 by an adhesive film on which the insulating film 11 is formed. Upper lead 8
The portion of A corresponding to the inner lead 9A and the outer lead 10A forms a lower inner lead 9B and a lower outer lead 10B. Adjacent upper leads 8A and 8
A lower dam 7b is bonded to the lower surface of the dam A (hereinafter referred to as an upper dam 7a) by an insulating film 11, and each lower dam 7b is connected to the adjacent lower leads 8B and 8B, respectively. ing.

The tip of the lower inner lead 9B protrudes inward from the tip of the upper inner lead 9A, and the tip of the lower outer lead 10B is the upper outer lead 10A.
Is retracted inward from the tip. In a portion of the insulating film 11 where the lower outer lead 10B is recessed from the upper outer lead 10A, there are formed isolation portions 11A flush with the lower surface of the upper outer lead 10A, and both sides in the radial direction of the isolation portion 11A. An upper grounding portion a and a lower grounding portion b are formed at the distal ends of the upper outer lead 10A and the lower outer lead 10B, respectively.

For bonding the lower lead 8B to the upper lead 8A, for example, an adhesive is applied to the upper surface of an assembly of the lower dam 7b group and the lower lead 8B group connected by each lower dam 7b. It can be implemented by stacking the unit lead frames 2 in the state. Then, the insulating film 11 for insulating the upper lead 8A and the lower lead 8B is formed by the adhesive film.

Each unit lead frame in the multiple lead frame configured as described above is subjected to pellet bonding in a pellet bonding step, and subsequently to wire bonding in a wire bonding step, as shown in FIG. Assembly 15 is manufactured.

In FIG. 3, the pellet 1 is placed on the tub 6.
2 are bonded by a bonding layer 13 formed of a solder material, a silver paste, or the like. An electrode pad of the pellet 12 bonded on the tab 6;
Each upper inner lead 9A and each lower inner lead 9B
And each wire 14 is bridged between them. In this state, the standard logic circuit built in the pellet 12 includes the electrode pad, the wire 14 and each inner lead 9.
A, 9B and the outer leads 10A, 10B are electrically drawn to the outside via the outer leads 10A, 10B.

The assembly 15 assembled as described above is subjected to transfer molding in a resin sealing body forming step, and as shown in FIG. 4, a resin sealing body 16 is attached to each unit lead frame 2. Molded products 17 each molded
Are molded at once.

In FIG. 4, the resin sealing body 16 is made of a resin containing an epoxy resin as a main component, and is integrally formed into a substantially square flat plate shape by a transfer molding apparatus. Upper and lower inner leads 9
Groups A and 9B, pellets 12, wires 14 and tabs 6 are sealed with resin. In this state, the upper and lower outer leads 10 </ b> A and 10 </ b> B are in a state of protruding from one opposite side of the resin sealing body 16, respectively.

The molded article 17 on which the resin sealing body 16 has been formed as described above is then subjected to a projecting portion of the tab suspension lead 5 from the resin sealing body 16 in a lead cutting step.
The section frame 4 and the dam 7a are respectively cut, and the upper and lower outer leads 10A and 10B are bent outside the resin sealing body 16 into a gull-wing shape. In this state, the SOP IC 18 shown in FIG. 1 has been manufactured.

The SO manufactured and constructed as described above
The P-IC 18 is, for example, surface-mounted on a printed wiring board 20 shown in FIG.

In FIG. 5, the printed wiring board 20 on which the SOP / IC 18 is mounted has a board body 21. The board body 21 is formed in a rectangular flat plate shape using an insulating material such as glass epoxy resin. ing. A plurality of lands 22 respectively connected to electric wiring (not shown) are formed on the upper surface of the substrate main body 21. Each land 22 is made of a conductive material such as a copper foil and is formed of a suitable material such as a lithography process. By means, it is formed in a small rectangular thin plate shape slightly larger than the grounding portions a and b of the upper and lower outer leads 10A and 10B of the SOP IC 18.

The plurality of lands 22 correspond to the first grounding portion a of the pair of upper outer leads 10A of the SOP IC 18 and the second grounding portion b of the lower outer lead 10B, and are combined to a pair. A land (hereinafter, referred to as a first land) 22A corresponding to the ground portion a, and a second ground portion b
(Hereinafter referred to as a second land) 22B
Are arranged next to each other with the insulating portion 23 interposed therebetween and arranged in four rows. That is, the two rows of the first land 22A group row and the two rows of the second land 22B group row are arranged so as to be aligned with each other on the outside and inside. In FIG.
The row of the first lands 22A is composed of five first lands 22A, and the row of the second lands 22B is also composed of five second lands 22B.

The SOP IC 18 is a printed circuit board 20
When surface mounting is performed, a solder paste is applied on each land 22, and the first ground portion a and the second ground portion b of the SOP IC 18 are aligned and bonded. Thus SOP
-With the IC 18 set, the printed wiring board 2
When the reflow soldering process is performed on 0, soldering portions 24 are formed between the lands 22 and the grounding portions a and b, as shown in FIG. Since the insulating portion 23 is formed between the first land 22A and the second land 22B, there is no short circuit between the adjacent solder portions 24. In this way, the SOP IC 18 is electrically and mechanically connected to the printed wiring board 20, and is in a state of being surface-mounted as shown in FIG.

Next, an example of the method of use and the operation thereof will be described.

FIG. 6 shows a conventional standard logic SOP IC.
In the case of the pin arrangement shown in FIG. 6A, the SOP IC 18 of the standard logic according to the present embodiment is
The pin arrangement shown in FIG. That is, in the case where the upper left corner of the conventional SOP / IC is defined as the first pin and the second pin, the third pin, and so on in the counterclockwise direction and the upper right corner is the twenty pin, the present embodiment SOPs related to
The first ground portion a at the upper left corner of the IC 18 becomes the first pin, the second ground portion b paired with the first ground portion a of the first pin becomes the second pin, and thereafter, the second ground portion b is rotated counterclockwise. One grounding portion a is a third pin, and a second grounding portion b paired with the first grounding portion a of the third pin
Are defined as the fourth pin..., And the second ground portion b in the upper right corner becomes the twenty-second pin.

When the tenth pin in the conventional SOP / IC is the VSS terminal and the twenty-third pin is the VCC terminal, the tenth pin (the second pin) is also used in the SOP / IC 18 according to the present embodiment. The grounding part b) becomes the VSS terminal,
The 20th pin (second grounding section b) becomes the VCC terminal.

As is clear from the comparison between FIGS. 6 (a) and 6 (b), although the number of pins is the same as that of the conventional SOP / IC, the resin sealing body 1 of the SOP / IC 18 according to the present embodiment is provided.
6 is half the length of the conventional resin-sealed body of the SOP / IC. That is, the SOP IC 1 according to the present embodiment
8 has been reduced to half that of the conventional SOP IC.

According to the above embodiment, the following effects can be obtained.

1) The lower outer lead is adhered to the upper outer lead with an insulating film, and the first ground portion formed at the tip of the upper outer lead and the second ground portion formed at the tip of the lower outer lead are separated at the same position. By arranging the portions adjacent to each other with the portion interposed therebetween, the area of the package can be reduced without reducing the number of connections to the printed wiring board, so that the mounting area on the printed wiring board can be significantly reduced.

2) Although the size of the package is reduced, the area of the pellet, the layout of the electrode pads, and other specifications do not need to be changed, so that the existing pellet can be used as it is.

3) Since the numbers of the pin arrangement of the IC and the printed wiring board can be applied mutatis mutandis, the specification change of the printed wiring board can be suppressed to the minimum in the shape and arrangement of the lands.

FIG. 7 shows a second embodiment of the present invention.
3A and 3B show a mounted state of an IC, wherein FIG. 3A is a partially cutaway front view, and FIG. 3B is a partially omitted perspective view of a main part.

This embodiment is different from the above embodiment in that
That is, it is configured in the DIP. That is, the first grounding portion a and the second grounding portion b are inserted into the through-hole 26 of the printed wiring board 20, and the first through-hole conductor portion 27A formed on a pair of side surfaces of the through-hole 26 and the second through-hole are formed. It is configured to be connected to each of the hole conductors 27B.

FIG. 8 shows a third embodiment of the present invention.
3A and 3B show a mounted state of an IC, wherein FIG. 3A is a partially cutaway front view, and FIG. 3B is a partially omitted perspective view of a main part.

This embodiment is different from the above embodiment in that
The point is that a pair of leads are formed in an inner / outer double structure with an insulating film interposed therebetween, and a pair of outer leads are formed in a DIP. That is, the inner lead 80A is covered with the outer lead 80B with the insulating film 11 interposed therebetween, and the first ground portion a of the inner lead 80A and the second ground portion b of the outer lead 80B are formed in the through hole 26 of the printed wiring board 20. And is connected to a first through-hole conductor portion 28A formed below the through-hole 26 and a second through-hole conductor portion 27B formed above the through-hole 26, respectively.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, a pair of leads is not limited to being used for a signal line, but one lead may be used for a signal line, and the other lead may be used as a ground or a power supply (most negative potential) line. Particularly, in a lead in which a pair of leads are formed in an inner / outer double structure with an insulating film interposed therebetween, a high noise reduction effect can be obtained by using the inner lead as a signal line and the outer lead as a ground line. .

The package is not limited to SOP and DIP, but may be SOI (Small Outline I-Lead Package), QFP (Quad Flat Package) and QFI (Quad Flat I-Lead Package). May be.

The sealing body is not limited to the resin sealing, but may be a hermetic sealing body.

In the above description, the invention made by the present inventor has been mainly described with reference to the standard logic IC which is the application field as the background, but the invention is not limited to this, and the logic IC used for other applications is not limited thereto. And semiconductor ICs such as memory ICs.

[0047]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

The grounding portion of one lead and the grounding portion of the other lead are disposed at the same position with the insulating film interposed between the pair of leads and are electrically isolated from each other, so that the number of connections to the printed wiring board is not reduced. Since the area of the package can be reduced, the mounting area on the printed wiring board can be significantly reduced.

[Brief description of the drawings]

1A and 1B show an SOP IC according to an embodiment of the present invention, in which FIG. 1A is a plan sectional view of a left half, a bottom view of a right half, and FIG.

FIG. 2 shows a multiple lead frame used in a method for manufacturing an SOP / IC according to an embodiment of the present invention;
(A) is a partially omitted plan view, and (b) is a front sectional view.

3A and 3B show a state after a pellet wire bonding step, in which FIG. 3A is a partially omitted plan view, and FIG. 3B is a front sectional view.

4A and 4B show a state after a resin sealing body forming step, in which FIG. 4A is a partially omitted plan view and FIG. 4B is a front sectional view.

FIGS. 5A and 5B show a mounted state of an SOP / IC according to an embodiment of the present invention, wherein FIG. 5A is a plan view, and FIG. 5B is a partially omitted perspective view of a main part.

FIGS. 6A and 6B are bottom views for explaining the operation, and FIG.
Shows the case of the related art, and (b) shows the case of the present embodiment.

7A and 7B show a mounted state of a DIP IC according to a second embodiment of the present invention, wherein FIG. 7A is a partially cutaway front view, and FIG. 7B is a partially omitted perspective view of a main part.

8A and 8B show a mounted state of a DIP IC according to a third embodiment of the present invention, wherein FIG. 8A is a partially cutaway front view, and FIG. 8B is a partially omitted perspective view of a main part.

[Explanation of symbols]

1 ... multiple lead frame, 2 ... unit lead frame, 3
... Outer frame, 3a ... positioning hole, 4 ... section frame, 5 ... tab suspension lead, 6 ... tab, 7 ... dam member, 7a ... upper dam, 7b ... lower dam, 8 ... lead, 8A ... upper lead,
8B: lower lead, 9: inner lead, 9A: upper inner lead, 9B: lower inner lead, 10: outer lead, 10A: upper outer lead, 10B: lower outer lead, 11: insulating film, 11A: isolation part, 12 ... Pellets, 13 ... Bonding layer, 14 ... Wire, 15 ... Assembly, 16 ... Resin sealing body, 17 ... Molded product, 18 ... SOP
IC (semiconductor device), 20: printed wiring board (mounting board), 21: board body, 22: land, 23: insulating section,
24: soldering part, 26: through hole, 27A, 27
B: through-hole conductor, 28A, 28B: through-hole conductor, 80A: inner lead, 80B: outer lead.

Claims (10)

[Claims] A pair of leads electrically connected to a semiconductor pellet sandwich an insulating film, and a ground part of one lead and a ground part of the other lead are arranged at the same position and are electrically isolated from each other. A semiconductor device characterized in that: 2. The pair of leads are vertically stacked with the insulating film interposed therebetween, and the ground portion of the upper lead and the ground portion of the lower lead are arranged at the same position and are electrically isolated. A semiconductor device characterized by the above-mentioned. 3. The pair of leads are formed in an inner / outer double structure with the insulating film interposed therebetween, and the grounding portion of the inner lead and the grounding portion of the outer lead are electrically isolated at the same position. A semiconductor device characterized by the above-mentioned. 4. The semiconductor device according to claim 1, wherein the ground portion of the one lead and the ground portion of the other lead are surface-mounted. 5. The semiconductor device according to claim 1, wherein the ground portion of the one lead and the ground portion of the other lead are inserted and mounted. 6. The semiconductor device according to claim 1, wherein said pair of leads form different signal lines. 7. The semiconductor device according to claim 1, wherein one of the pair of leads is set to have a most negative potential. 8. The method for manufacturing a semiconductor device according to claim 1, wherein a lead frame for forming the one lead is provided with the insulating film interposed between lead frames for forming the other lead. A method for manufacturing a semiconductor device, comprising a step of bonding. 9. The method according to claim 8, further comprising the step of bending the outer portions of the pair of leads into a gull-wing shape at the same time. 10. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of covering said one lead with another lead via an insulating film. Production method.