KR20030049577A - method for stacking semiconductor package - Google Patents

Abstract

PURPOSE: A stacking method of a semiconductor package is provided to be capable of reducing the size of a ball grid array package by folding the lateral and upper portion using a conductive tape. CONSTITUTION: The first and second package(100,200) are provided with the first and second molding parts(104,204) formed on the upper portions, the first and second conductive balls(106) attached on the lower portions, the first and second circuit boards(102,202), and the first and second connecting parts(103,203) prolonged from the first and second circuit boards, respectively. The first and the second molding parts are enclosed by folding the first and the second connecting parts. After removing the second conductive balls, the rear surface of the second circuit board is attached on the upper surface of the first circuit board.

Description

Method for stacking semiconductor package

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacking method of a semiconductor package, and more particularly, to a stacking method of a semiconductor package capable of stacking a plurality of ball grid array package (BGA) type semiconductor packages.

With the trend toward thinner and shorter electronic devices, high-density and high-mounted packages are becoming an important factor.In the case of computers, a large amount of random access memory (RAM) and fresh memory as the storage capacity increases. Like the Flash Memory, the size of the chip grows naturally, but the package is being studied to be smaller in accordance with the above requirements.

On the other hand, one of several types of packages that can reduce the size of the package is a ball grid array package for attaching a conductive ball to the bottom of the package, the ball grid array package is a spherical solder ball (solder) on the back of the substrate Conductive balls such as balls are arranged in a predetermined state to be used instead of the outer lead, and the package body area can be made smaller than the QFP (Quad Flat Package) type, and unlike QFP, there is no deformation of the lead. There is an advantage.

Looking at the manufacturing process of the ball grid array package having the above advantages are as follows. First, sawing is performed to individually separate semiconductor chips formed on a wafer in a state where an FAB (fabrication) process for forming an integrated circuit on the upper surface of the wafer is completed.

Then, as the circuit board having the wiring formed therein is put into the process, an adhesive is applied to the upper surface of the circuit board to bond the cut semiconductor chip. After chip bonding is completed, the bonding pad formed on the semiconductor chip and a predetermined portion on the circuit board are bonded. Wire bonding is performed to electrically connect the wires between the wires.

After the wire bonding is completed, a molding process of encapsulating the semiconductor chip with an epoxy molding compound (EMC) is performed. After the molding is completed, the solder ball is attached to the bottom surface of the circuit board, and then a reflow (heat treatment) process is performed. Reflow) is used to securely solder the solder ball to the package body and then test to complete the ball grid array package fabrication.

1 is a cross-sectional view of a stacked ball grid array package according to the prior art.

In order to increase the capacity of the completed ball grid array package 10, another package single piece 20 and single piece 30 completed through the process are stacked on the package 10, as shown in FIG. And can be used in connection. At this time, the connection process is designed to make the length of the circuit board longer than the package body when the solder ball array package unit 10, 20, 30, the solder ball 40 by attaching the solder ball 40 to the extra circuit board area The array package unit 10, 20, 30 is fixed.

However, according to the related art, the circuit board length is designed to extend longer than the molding, and thus has a problem of occupying a lot of space on the side surface.

Accordingly, an object of the present invention is to provide a method of stacking a semiconductor package that can be stacked in a plurality by miniaturizing a ball grid array package.

1 is a cross-sectional view of a stacked ball grid array package according to the prior art.

2A to 2C are stacking flowcharts for manufacturing a semiconductor package according to the first embodiment of the present invention.

3A to 3C are stacking flowcharts for manufacturing a semiconductor package according to a second embodiment of the present invention.

In the stacking method of the semiconductor package of the present invention for achieving the above object, the first and second molding bodies are formed on the upper surface, and the first and second conductive balls are attached to the lower surface, and the first and second sides are extended to the side. Providing first and second packages including first and second circuit boards having second connections, folding the first and second connections to cover the first and second moldings, and folding the first and second packages. And attaching a bottom surface of the second circuit board on which the second conductive ball is removed to the first connection part.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are stacking flowcharts for manufacturing a semiconductor package according to a first embodiment of the present invention.

In the stacking method of the semiconductor package according to the first embodiment of the present invention, as shown in FIG. 2A, first, a first ball grid array package 100 is provided. In this case, the first ball grid array package 100 has a first molding body 104 formed with a semiconductor chip (not shown) formed on the upper surface thereof, and a first conductive ball 106 attached to the bottom thereof and extended on one side thereof. It has a structure including a first circuit board 102 having a first connecting portion 103 in the form.

Subsequently, as illustrated in FIG. 2B, the first connection part 103 is folded to cover the entire one side and the top surface of the first molding body 104, and then the first ball grid array package having the structure ( 100). At this time, an epoxy (not shown) is interposed between the first molding member 104 and the folded first connector 103 to improve adhesion.

Next, as shown in FIG. 2C, the second and third connectors 203 and 303 of the second ball grid array package 200 and the third ball grid array package 300 are folded to form the second and third connections. After wrapping one side and the entire upper surface of the third molding bodies 204 and 304, the second and third ball grid array packages 200 and 300 of the structure are tested. In this case, the second and third ball grid array packages 200 and 300 have the same structure as the first ball grid array package, and the second and third molding bodies 204 in which semiconductor chips (not shown) are molded. The second and third conductive balls 206 and 306 are formed on the bottom, and the second and third conductive balls 206 and 306 are attached to one side thereof, and the second and third connecting parts 203 and 303 of the extended shape are formed on one side thereof. It has a structure including a circuit board 202, 302. In addition, a conductive tape is used as a material of the first, second and third connection portions.

Thereafter, the second and third conductive balls 206 and 306 of the second and third ball grid array packages 200 and 300 are completed.

Subsequently, after stacking the second circuit board 202 of the second ball grid array package 200 on the folded first connector 103 of the first ball grid array package 100, The third circuit board 302 of the third ball grid array package 300 is stacked on the folded second connector 203 of the second ball grid array package 200. At this time, a solder paste, an isotropic conductive film (ACF), or an ACP is formed between the folded first and second connectors 103 and 203 and the bottom of the second and third circuit boards 202 and 302. By interposing the adhesive 400 of any one of (Anisotropic Conductive Paste) to improve the adhesion between the first, second and third ball grid array package 100, 200, 300.

3A to 3C are stacking flowcharts for manufacturing a semiconductor package according to a second embodiment of the present invention.

The stacking method of the semiconductor package according to the second embodiment of the present invention is the same as the first embodiment of the present invention, but as shown in FIG. 3A, the first connection part 103a of the first ball grid array package 100 is provided. 103b has a form extended to both sides. Accordingly, as shown in FIG. 3B, the first connection portions 103a and 103b having the above shapes are folded to cover both side surfaces and the top surface of the first circuit board 102.

3C, the second and third connectors 203a, 203b, 303a of the second ball grid array package 200 and the third ball grid array package 300 are operated in the same manner as described above. 303b is folded to cover both side surfaces and top surfaces of the second and third molding bodies 204 and 304.

Subsequently, the second circuit board 202 of the second ball grid array package 200 is stacked on the folded first connectors 103a and 103b of the first ball grid array package 100. By way of example, the third circuit board 302 of the third ball grid array package 300 is stacked on the folded second connectors 203a and 203b of the second ball grid array package 200.

In the first and second embodiments of the present invention, the ball grid array package has been described as an example in which three single layers are stacked, but three or more layers can be stacked.

As described above, in the present invention, first, by wrapping the side and the top surface of the package using a conductive tape, by stacking a plurality of packages having the above structure can effectively reduce the volume occupied by the package. Thus, more packages can be stacked in the same volume.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (8)

First and second molding bodies are formed on the upper surface, and the first and second conductive balls are attached to the lower surface, and the first and second circuit boards having the first and second connection parts extending from the side. And providing a second package; Folding the first and second connectors to cover the first and second moldings; And attaching a bottom surface of the second circuit board from which the second conductive ball is removed to an upper surface of the folded first connector. The method of claim 1, wherein the first and second connectors are formed on one side of the first and second circuit boards. The method of claim 1, wherein in the folding step, the first and second connection parts cover all of the side surfaces and a part of the upper surface of the first and second molding bodies. The method of claim 1, wherein the first and second connectors are formed on both sides of the first and second circuit boards. The method of claim 1, wherein in the folding step, the first and second connectors cover the side surfaces and the top surfaces of the first and second molding bodies. The method of claim 1, wherein a solder paste, an ACF, or an ACP is interposed between the first and second moldings and the folded first and second connectors. The method of claim 1, further comprising removing the second conductive balls after the folding process. The method of claim 1, wherein the first, second, and third connectors are conductive tapes.