KR20090074694A - Semiconductor device and manufacturing of method the same - Google Patents

Abstract

A semiconductor device and a manufacture method thereof are provided to allow some of an interlayer insulating layer to remain on an isolating layer corresponding to a bit line contact region, thereby preventing a defect in the alignment of a gate pattern. An isolating layer(102) is formed on a semiconductor substrate(100). An active area is insulated by the isolating layer and includes a bit line contact region. Gate patterns(110a,110b) are formed to cross the active area and the isolating layer. Some of an interlayer insulating layer(114a) remains to fill the interval of gate patterns. A plug(118) is formed to be contacted with the bit line contact region of the active area. The lower part of the plug is formed on the active area and the upper part is formed on both the upper part of the active area and the remaining interlayer insulating layer.

Description

Semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same, which can prevent a bridge between a gate conductive film and a landing plug to prevent self alignment contact defects.

As semiconductor devices become more integrated, channel lengths of transistors are decreasing, and ion implantation concentrations into junction regions (source / drain regions) are increasing.

As a result, a so-called short channel effect is generated in which interference sharing between source / drain regions is increased, gate control capability is lowered, and threshold voltage is drastically lowered.

Accordingly, a method of implementing a transistor having various types of recess channels capable of securing an effective channel length has been proposed.

However, when the transistor having the recess channel is formed, a portion of the device isolation layer is also lost during the etching process of the interlayer insulating layer for forming the landing plug. Thus, a gate electrode material is formed on the lost device isolation layer. As a result, the passing gate affects the transistor during the actual cell operation, which causes a problem of decreasing the characteristics of the transistor by decreasing the threshold voltage and increasing the leakage current.

In addition, if a misalignment occurs between the device isolation layer and the recess gate during the recess mask, an attack is applied to the active region of the semiconductor substrate during the subsequent recess gate etching process. A bridge is caused between the polysilicon films used as the conductive films of the passing gates.

This causes unwanted electrical short between the recess gate and the landing plug, so-called self-aligned contact defects.

As a result, a defect of a semiconductor element is caused, deteriorating element characteristic and a manufacturing yield fall.

The present invention provides a semiconductor device capable of preventing a bridge between a gate conductive film and a landing plug conductive film to prevent self-aligned contact defects, and a method of manufacturing the same.

In addition, the present invention provides a semiconductor device and a method of manufacturing the same that can improve the characteristics and manufacturing yield of the semiconductor device.

In an aspect, a semiconductor device according to an embodiment of the present invention may include an isolation region formed in a semiconductor substrate, an active region insulated by the isolation layer, and including a bit line contact region, an active region and an element of the semiconductor substrate. A gate pattern formed to cross the separation layer and the gate pattern to fill the gap, and exposing a bit line contact region of the active region and a portion of a thickness remaining on the device isolation layer corresponding to the bit line contact region. And an interlayer insulating layer and a plug formed to contact the bit line contact region of the active region in the interlayer insulating layer having the remaining thickness, wherein the plug is formed on the active region in the lower portion, and the upper and the partial thicknesses of the active region in the upper portion. And formed on the remaining interlayer insulating film portion.

The gate pattern includes a spacer formed on the side surface.

The gate pattern includes a gate insulating film, a gate conductive film, and a gate hard mask film.

The gate pattern has a line shape and is formed as a recess gate or a saddle fin gate in an active region.

The interlayer insulating film includes an oxide film or a nitride film.

The plugs have different widths at the top and bottom.

The plug has a "-" shape in cross section in the bit line contact region.

In another aspect, a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, forming a device isolation film defining an active region including a bit line contact region in the semiconductor substrate, the active region and the device isolation film on the semiconductor substrate Forming a gate pattern crossing the gate pattern, forming an interlayer insulating layer so as to fill the gate pattern, and exposing the bit line contact region of the active region and on the device isolation layer corresponding to the bit line contact region. Etching the interlayer insulating film so that a partial thickness of the interlayer insulating film remains, and forming a plug in the interlayer insulating film having the partial thickness remaining in contact with the bit line contact region of the active region, wherein the plug has a lower portion Is formed on the active region in the upper portion and the active region in the upper portion It characterized in that formed on the interlayer insulating film having a thickness of the residual portion.

The gate pattern is formed to include a gate insulating film, a gate conductive film, and a gate hard mask film.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, the method may further include forming a spacer on a side surface of the gate pattern after forming the gate pattern and before forming the interlayer insulating layer.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, after the forming of the gate pattern, and before the forming of the interlayer insulating film, the step of forming a spacer film on the semiconductor substrate including the gate pattern further Include.

The gate pattern has a line shape and is formed as a recess gate or a saddle fin gate in an active region.

The interlayer insulating film is formed of an oxide film or a nitride film.

The plugs are formed to have different widths at the top and bottom.

The plug is formed in the bit line contact region so that its cross section has a "-" shape.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, etching the interlayer insulating film may include forming a first mask pattern exposing the active region on the interlayer insulating film, and forming the first mask pattern. Forming a groove by etching a part thickness of the interlayer insulating layer using the etching mask; and a second mask exposing an active region corresponding to a bit line contact region and a device isolation layer on the resultant semiconductor substrate on which the groove is formed. Forming a pattern and using the second mask pattern as an etch mask to expose a bit line contact region of an active region of the bottom of the groove and to retain a portion of a thickness on the device isolation layer corresponding to the bit line contact region. And etching the interlayer insulating layer to remove the first and second mask patterns.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, etching the interlayer insulating film may include forming a mask film on the interlayer insulating film and exposing the active area by exposing the mask film. Forming a groove by etching a partial thickness of the interlayer insulating layer using the first mask pattern as an etching mask, and additionally exposing the first mask pattern remaining after the etching. And forming a second mask pattern exposing the device isolation layer corresponding to the bit line contact region, using the second mask pattern as an etching mask, exposing an active region of the bottom surface of the groove and simultaneously exposing the bit line contact. Further etching the interlayer dielectric layer so that a part of thickness remains on the isolation layer corresponding to the region; and And a step of removing the second mask pattern group.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, etching the interlayer insulating film may include forming a barrier film on the interlayer insulating film, and forming a first mask pattern exposing an active region on the barrier film. Forming a barrier pattern exposing an active region on the interlayer insulating layer by etching the barrier layer portion to expose the interlayer insulating layer by using the first mask pattern as an etching mask; Removing the first mask pattern, forming a second mask pattern exposing the device isolation layer corresponding to the active region and the bit line contact region on the barrier pattern, and using the second mask pattern as an etch mask. And etching the interlayer insulating layer so that the bit line contact region of the active region is exposed. Removes the barrier pattern of the upper isolation film that corresponds to the chosen area, and a step and removing the barrier pattern and a second mask pattern to etch some part of the thickness of the interlayer insulating film below.

The barrier film is formed to include a nitride film.

The barrier film is formed to a thickness of 300 to 700 GPa.

The second mask pattern is formed in a bar type type to expose an active region, a device isolation layer corresponding to a bit line contact region, and a device isolation layer between the active regions in the long axis direction of the active region.

The barrier pattern has a lower etching speed than the interlayer insulating layer.

In the method of manufacturing a semiconductor device according to an embodiment of the present disclosure, the method may further include cleaning the semiconductor substrate on which the interlayer insulating layer is etched after etching the interlayer insulating layer and before forming the plug.

The cleaning is carried out in a dry manner.

The cleaning is carried out using a mixed gas of NH ₃ + HF.

According to an embodiment of the present invention, an interlayer insulating layer for forming a landing plug is formed such that an active region and a bit line contact region are exposed and a partial thickness of the interlayer insulating layer remains on the device isolation layer corresponding to the bit line contact region.

In this case, since the cross-section of the interlayer insulating film having the partial thickness has a “L” shape on the device isolation film corresponding to the bit line contact region, the interlayer insulating film having the partial thickness remains due to the interlayer insulating film having the partial thickness remaining. In addition to preventing etching, misalignment of the gate pattern can be prevented.

In addition, the present invention prevents misalignment, thereby preventing unwanted electrical disconnection between the gate pattern and subsequent landing plugs, so-called self-aligned contact defects. As a result, semiconductor device characteristics and manufacturing yields can be improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention, and FIG. 2 is a line A-A 'and line B-B' in FIG. 1 to describe a semiconductor device in accordance with an embodiment of the present invention. Each is cut according to, and the cross-sectional view showing the result of the plug forming process is performed. Here, (a) is sectional drawing cut along the gate width direction, (b) is sectional drawing cut along the gate longitudinal direction.

1 and 2, an active region AR including a storage node contact region and a bit line contact region is defined in the semiconductor substrate 100, and the active region AR is insulated from the semiconductor substrate 100. The device isolation film 102 is formed. A gate pattern groove H is provided in the active region AR and the device isolation layer 102 to secure an effective channel length.

Gate patterns 110a and 110b are formed on the gate pattern groove H to cross the active region AR of the semiconductor substrate 100 and the device isolation layer 102. The gate patterns 110a and 110b include a gate insulating film, a gate conductive film, and a gate hard mask film. The gate patterns 110a and 110b have a line type, and are formed as recess gates or saddle fin gates in the active region AR. Spacers 112 formed of nitride layers are formed on side surfaces of the gate patterns 110a and 100b. The spacer 112 may be further formed on the device isolation layer 102.

Exposing the storage node contact area and the bit line contact area of the active area AR to fill the gate patterns 110a and 110b on the semiconductor substrate 100 and simultaneously corresponding to the bit line contact area. Interlayer insulating films 114 and 114a with a partial thickness remaining on the device isolation layer 102 are formed. The interlayer insulating layers 114 and 114a include an oxide film or a nitride film, for example, a spin-on dielectric (SOD) film.

Here, the cross-sectional insulating films 114 and 114a having the partial thickness remain on the device isolation layer 102 corresponding to the bit line contact region, for example, having an “L” shape.

A landing plug plug 118 is formed in the interlayer insulating layers 114 and 114a having the remaining thickness to contact the storage node contact region and the bit line contact region of the active region AR. The plug 118 is formed to a thickness of 200 to 3,000 Å, and is formed of a polysilicon film. The plug 118 has different widths at upper and lower portions thereof, and has a cross-sectional shape of the letter “a” on the device isolation layer 102 corresponding to the bit line contact region.

On the other hand, in the semiconductor device according to the embodiment of the present invention, when the cross-sectional insulating film is viewed on the device isolation film corresponding to the bit line contact region, the cross-section has an "L" shape, so that the etching of the device isolation film is performed. In addition to preventing the misalignment of the gate pattern.

In addition, the semiconductor device according to the embodiment of the present invention can prevent unwanted electrical disconnection between the gate pattern and the subsequent landing plug, so-called self-aligned contact failure, by preventing misalignment, thereby improving device characteristics and manufacturing. Yield.

Herein, reference numeral FR denotes an isolation region, 104 denotes a first gate conductive layer, 106 denotes a second gate conductive layer, and 108 denotes a gate hard mask layer.

3 is a cross-sectional view illustrating a result of cutting along a line A-A 'and line B-B' of FIG. 1 and performing a plug forming process to explain a semiconductor device according to another exemplary embodiment of the present inventive concept. Here, (a) is sectional drawing cut along the gate width direction, (b) is sectional drawing cut along the gate longitudinal direction.

1 and 3, an active region AR including a storage node contact region and a bit line contact region is defined in the semiconductor substrate 200, and the active region AR is insulated from the semiconductor substrate 200. The device isolation film 202 is formed. A gate pattern groove H is provided in the active region AR and the device isolation layer 202 to secure an effective channel length.

Gate patterns 210a and 210b are formed on the gate pattern groove H to cross the active region AR of the semiconductor substrate 200 and the device isolation layer 202. The gate patterns 210a and 210b include a gate insulating layer, a gate conductive layer, and a gate hard mask layer.

The gate patterns 210a and 210b have a line shape, and are formed as recess gates or saddle fin gates in the active region AR. Spacers 212 made of a nitride film are formed on side surfaces of the gate patterns 210a and 200b. Herein, reference numeral FR denotes an isolation region, 204 denotes a first gate conductive layer, 206 denotes a second gate conductive layer, and 208 denotes a gate hard mask layer.

Exposing a storage node contact region and a bit line contact region of the active region AR to fill the gap between the gate patterns 210a and 210b on the semiconductor substrate 200, and simultaneously corresponding to the bit line contact region. Interlayer insulating films 214 and 214a with a partial thickness remaining on the device isolation film 202 are formed. The interlayer insulating films 214 and 214a include an oxide film or a nitride film, for example, an SOD film. Here, the cross-sectional insulating films 214 and 214a having the partial thickness remaining on the device isolation layer 202 corresponding to the bit line contact region have a cross-section, for example, “L” shape.

A landing plug plug 220 is formed in the interlayer insulating layers 214 and 214a having the remaining thickness to contact the storage node contact region and the bit line contact region of the active region AR. The plug 220 is formed to a thickness of 500 ~ 2,000Å, it is formed of a polysilicon film. The plug 220 has a different width at an upper portion and a lower portion thereof, and has a cross-section “a” on the device isolation layer 202 corresponding to the bit line contact region.

In the semiconductor device according to another embodiment of the present invention, when the cross-sectional insulating film is viewed on the device isolation film corresponding to the bit line contact region, the cross-section insulating film has an "L" shape, so that the surface etching of the device isolation film is performed. And misalignment of the gate patterns.

Accordingly, in the semiconductor device according to the embodiment of the present invention, as shown in FIGS. 2 and 3, the etching of the device isolation layer is prevented to prevent unwanted electrical disconnection between the gate pattern and the landing plug, so-called self-aligned contact. Defects can be prevented and as a result have improved device properties and manufacturing yields.

4A to 4I are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, after forming an isolation layer 102 defining an active region AR including a storage node contact region and a bit line contact region in the semiconductor substrate 100, the isolation layer 102 may be included. A gate pattern groove H is formed in the gate pattern forming portion of the active region AR to secure an effective channel length. After forming the gate patterns 110a and 110b crossing the active region AR and the device isolation layer 102 on the gate pattern groove H, the semiconductor substrate including the gate patterns 110a and 110b ( A spacer film (not shown) made of a nitride film is formed on 100.

Then, the spacer layer is etched back to expose the active region AR, thereby forming a spacer 112 on the side surfaces of the gate patterns 110a and 110b. In this case, the spacer 112 corresponding to the device isolation layer 102 may be left without being removed during the etch back to prevent loss of the device isolation layer 102.

 The gate patterns 110a and 110b include a gate insulating film, a gate conductive film, and a hard mask film. The gate patterns 110a and 110b have a line type, and are formed as recess gates or saddle fin gates in the active region AR.

Here, reference numeral FR denotes an isolation region, 104 denotes a first gate conductive layer, 106 denotes a second gate conductive layer, and 108 denotes a gate hard mask layer.

Referring to FIG. 4B, an interlayer insulating layer 114 is formed on the spacer layer 112 to fill the gaps between the gate patterns 110a and 110b, and then a spacer corresponding to upper surfaces of the gate patterns 110a and 110b. Chemical mechanical polishing (CMP) is performed to expose the film 112. The interlayer insulating layer 114 includes an oxide film or a nitride film, for example, an SOD film.

4C is a plan view showing a first mask pattern exposing an active region on an interlayer insulating film. 4D is a cross-sectional view taken along lines AA ′ and BB ′ of FIG. 4C.

4C and 4D, a first mask pattern 116a exposing the active region AR is formed on the interlayer insulating layer 114.

Referring to FIG. 4E, using the first mask pattern 116a as an etching mask, a portion of the thickness of the interlayer insulating layer 114 may be, for example, dry-etched to form the groove H1. In this case, the partially etched interlayer insulating layer 114 has a height of 200 to 3,000 μs, which is lower than that of the gate patterns 110a and 110b, for example, and after the dry etching of the interlayer insulating layer 114. For the mask process, it is preferable that the first mask pattern 116a leaves a thickness of, for example, 200 to 2,000 GPa.

4F is a plan view illustrating a second mask pattern exposing an active region and an isolation layer corresponding to a bit line contact region. 4G is a cross-sectional view taken along lines AA ′ and BB ′ of FIG. 4F.

4G and 4F, a second mask exposing the active region AR and the device isolation layer FR corresponding to the bit line contact region on a result of the semiconductor substrate 100 having the groove H1 formed therein. Pattern 116b is formed.

On the other hand, although not shown and described, the second mask pattern 116b may have an active region AR and an isolation layer FR corresponding to the bit line contact region on the resultant of the semiconductor substrate 100 on which the groove H1 is formed. ) And the active region AR corresponding to the storage node contact region may be exposed, and the first mask pattern 116a is removed during the patterning process for forming the second mask pattern 116b. Can be.

Referring to FIG. 4H, using the second mask pattern 116b as an etch mask, the storage node contact region and the bit line contact region of the active region AR on the bottom surface of the groove H1 are exposed and at the same time the bit line is exposed. The interlayer insulating layer 114 is further etched to form a contact hole C so that a partial thickness remains on the device isolation layer 102 corresponding to the contact region.

Although not shown and described, the contact hole C may be formed using one mask pattern. In detail, a mask film made of a photosensitive film is formed on the interlayer insulating film. In order to form the contact hole, for example, two etching processes are performed to form the contact hole, the mask layer is preferably formed to have a certain thickness. Subsequently, after forming the first mask pattern exposing the active region by exposing the mask layer, a portion of the interlayer insulating layer is etched using the first mask pattern as an etch mask to form a groove. Further exposing the first mask pattern remaining after the etching to form a second mask pattern exposing the device isolation layer corresponding to the active region and the bit line contact region, and then using the second mask pattern as an etching mask, The contact hole may be formed by exposing the active region of the bottom of the groove and additionally etching the interlayer insulating layer so that a portion of the thickness remains on the device isolation layer corresponding to the bit line contact region.

Referring to FIG. 4I, after removing the first and second mask patterns, a polysilicon layer is formed in the contact hole C of the interlayer insulating layers 114 and 114a with the partial thickness remaining. Thereafter, the polysilicon layer is etched back or CMP to form a plug 118 that contacts the storage node contact region and the bit line contact region of the active region AR. The plug 118 is formed to have a thickness of, for example, 200 to 3,000 mm 3. The plug 118 has different widths at upper and lower portions thereof, and has a cross-sectional shape of the letter “a” on the device isolation layer 102 corresponding to the bit line contact region.

As described above, in the exemplary embodiment of the present invention, the interlayer insulating layer may be formed on the device isolation layer corresponding to the bit line contact region to have an “L” shape in cross section, thereby preventing etching of the device isolation layer. In addition, misalignment of the gate pattern can be prevented.

Thus, in one embodiment of the present invention, by preventing misalignment, it is possible to prevent unwanted electrical disconnection between the gate pattern and subsequent landing plugs, so-called self-aligned contact defects, resulting in device characteristics and manufacturing yields. Can be improved.

Meanwhile, in the above-described embodiment of the present invention, a spacer and a second protective pattern are formed on the device isolation film to prevent bridges between the gate conductive film and the landing plug conductive film, thereby preventing self-aligned contact defects. In another embodiment, by forming only a protective pattern on the device isolation layer, the same effects as in the above-described embodiment of the present invention can be obtained.

In detail, FIGS. 5A to 5J are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to another exemplary embodiment.

Referring to FIG. 5A, after forming an isolation layer 202 defining an active region AR including a storage node contact region and a bit line contact region in a semiconductor substrate 200, the isolation layer 202 may be included. A gate pattern groove H is formed in the gate pattern forming portion of the active region AR to secure an effective channel length.

After the gate patterns 210a and 210b are formed on the gate pattern groove H to cross the active region AR and the device isolation layer 202, a nitride layer is formed on side surfaces of the gate patterns 210a and 210b. A spacer 212 is formed. The gate patterns 210a and 210b include a gate insulating film, a gate conductive film, and a hard mask film. The gate patterns 210a and 210b have a line type, and are formed as recess gates or saddle fin gates in the active region AR.

Meanwhile, in another exemplary embodiment, the gate patterns 210a and 210b may include a gate oxide film (not shown), a first gate conductive film 204, a second gate conductive film 206, and a gate hard mask film ( 206) to form a laminated film. For example, the gate oxide film is formed to a thickness of 30 to 60 kPa, and the first gate conductive film 204 is formed of a polysilicon film, and is formed to a thickness of 400 to 1500 kPa. The second gate conductive film 206 is formed of a hybrid tungsten (Hybride W), and has a thickness of 400 to 600 GPa, and the gate hard mask film 206 is formed of a nitride film. Form to thickness.

Referring to FIG. 5B, an interlayer insulating layer 214 is formed to fill between the gate patterns 210a and 210b including the spacer 112. The interlayer insulating film 214 includes an oxide film or a nitride film, for example, an SOD film. Then, after CMP the top surface of the interlayer insulating film 214, the barrier film 216 is formed on the CMP interlayer insulating film 214. The barrier film 216 includes a nitride film having a lower etching speed than the interlayer insulating film 214 and is formed to have a thickness of 300 to 700 Å.

5C is a plan view in which a first mask pattern is formed on a barrier film. 5D is a cross-sectional view taken along lines AA ′ and BB ′ of FIG. 5C.

5C and 5D, a first mask pattern 217 exposing the active region AR is formed on the barrier layer 216.

5E is a cross-sectional view illustrating a barrier pattern exposing an active region on an interlayer insulating layer. 5F is a plan view of FIG. 5E.

5E and 5F, the barrier layer 216 is etched to expose the interlayer insulating layer 214 using the first mask pattern 217 as an etching mask. Thus, the barrier pattern 216a exposing the active region AR is formed on the interlayer insulating layer 214. Then, the first mask pattern is removed.

5G is a plan view in which a second mask pattern is formed on the barrier pattern. 5H is sectional drawing cut along the AA 'line and the B-B' line | wire of FIG. 5G.

5G and 5H, a second mask pattern 218 is formed on the barrier pattern 216a to expose the device isolation layer 202 corresponding to the active region AR and the bit line contact region. The second mask pattern 218 may be formed between the active region AR in the major axis direction of the active region AR, the device isolation layer 202 corresponding to the bit line contact region, and the active region AR. The separator 202 may be formed in a bar type that exposes the separator 202 together.

Referring to FIG. 5I, using the second mask pattern 218 as an etching mask, the interlayer insulating layer 214 is etched to expose the storage node contact region and the bit line contact region of the active region AR. At the same time, the barrier pattern 216a on the device isolation layer 202 corresponding to the bit line contact region is removed, and a portion of the interlayer insulating layer 214 below is etched to form a contact hole C.

Here, the interlayer insulating layers 214 and 214a having the partial thickness etched have a cross-section, for example, “L” shape on the device isolation layer 202 corresponding to the bit line contact region.

Referring to FIG. 5J, after removing the second mask pattern and the barrier pattern, the resultant of the semiconductor substrate 200 on which the interlayer insulating films 214 and 214a having the partial thicknesses are etched is cleaned. The cleaning is carried out in a dry manner using, for example, a mixed gas of NH ₃ + HF. The interlayer insulating layers 214 and 214a having the partial thickness etched away may be partially lost during the cleaning.

Thereafter, a polysilicon layer is formed in the contact hole C of the interlayer insulating layers 214 and 214a where the thickness is partially etched, and then the polysilicon layer is etched back or CMP to etch the storage node contact region of the active region AR. And a plug 220 in contact with the bit line contact region. The plug 220 is formed to a thickness of, for example, 500 to 2,000 mm 3. The plug 220 has different widths at the top and the bottom thereof, and has a cross-section of the shape “a” on the device isolation layer 122 corresponding to the bit line contact region.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the semiconductor device according to the embodiment of the present invention.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a result of cutting along a line A-A 'and line B-B' of FIG. 1 and performing a plug forming process to explain a semiconductor device according to an exemplary embodiment of the present invention.

3 is a cross-sectional view illustrating a result of cutting along a line A-A 'and line B-B' of FIG. 1 and performing a plug forming process to explain a semiconductor device according to another exemplary embodiment of the present inventive concept.

(a) is sectional drawing cut along the gate width direction.

(b) is sectional drawing cut along the gate longitudinal direction.

4A to 4I are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

4C is a plan view in which a first mask pattern is formed on an interlayer insulating film.

4F is a plan view in which a second mask pattern is formed.

5A through 5J are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to another embodiment of the present invention.

5C is a plan view in which a first mask pattern is formed on a barrier film. 5D is a cross-sectional view taken along lines AA ′ and BB ′ of FIG. 5C.

5E is a cross-sectional view of a barrier pattern formed on an interlayer insulating film. 5F is a plan view of FIG. 5E.

5G is a plan view in which a second mask pattern is formed on the barrier pattern. 5H is sectional drawing cut along the AA 'line and the B-B' line | wire of FIG. 5G.

Claims (25)

An isolation layer formed in the semiconductor substrate; An active region insulated by the device isolation layer and including a bit line contact region; A gate pattern formed to cross an active region of the semiconductor substrate and an isolation layer; An interlayer insulating layer formed to fill between the gate patterns and exposing a bit line contact region of the active region and at least partially remaining on a device isolation layer corresponding to the bit line contact region; And And a plug formed to contact the bit line contact region of the active region in the interlayer insulating layer having the remaining thickness. And the plug is formed on the active region in the lower portion and on the interlayer insulating layer portion in which the upper portion and the thickness of the active region remain in the upper portion. The method of claim 1, The gate pattern comprises a spacer formed on the side. The method of claim 1, The gate pattern comprises a gate insulating film, a gate conductive film and a gate hard mask film. The method of claim 1, The gate pattern has a line shape, characterized in that formed in the active region as a recess gate or saddle fin gate. The method of claim 1, The interlayer insulating film includes an oxide film or a nitride film. The method of claim 1, And the plug has a different width at the top and the bottom. The method of claim 1, And the plug has a "-" shape in cross section in the bit line contact region. Forming an isolation layer defining an active region including a bit line contact region in the semiconductor substrate; Forming a gate pattern crossing the active region and the device isolation layer on the semiconductor substrate; Forming an interlayer insulating film to fill between the gate patterns; Etching the interlayer insulating layer such that the bit line contact region of the active region is exposed and the thickness of the interlayer insulating layer remains on the device isolation layer corresponding to the bit line contact region; And And forming a plug in the interlayer insulating film having the remaining thickness, the plug contacting the bit line contact region of the active region. And the plug is formed on the active region in the lower portion and formed on the interlayer insulating layer portion in which the upper portion and the thickness of the active region remain in the upper portion. The method of claim 8, The gate pattern is formed to include a gate insulating film, a gate conductive film and a gate hard mask film. The method of claim 8, After forming the gate pattern and before forming the interlayer insulating film, Forming a spacer on a side of the gate pattern; Method of manufacturing a semiconductor device further comprising. The method of claim 8, After forming the gate pattern and before forming the interlayer insulating film, Forming a spacer layer on the semiconductor substrate including the gate pattern; Method of manufacturing a semiconductor device further comprising. The method of claim 8, The gate pattern has a line shape and a method of manufacturing a semiconductor device, characterized in that formed in the active region as a recess gate or saddle fin gate. The method of claim 8, And said interlayer insulating film is formed of an oxide film or a nitride film. The method of claim 8, The plug is a semiconductor device manufacturing method characterized in that formed to have a different width at the top and bottom. The method of claim 8, And the plug is formed in the bit line contact region so that its cross section has a "-" shape. The method of claim 8, Etching the interlayer insulating film, Forming a first mask pattern exposing the active region on the interlayer insulating film; Using the first mask pattern as an etching mask, etching a portion of the interlayer insulating layer to form a groove; Forming a second mask pattern exposing an active region corresponding to a bit line contact region and a device isolation layer on the resultant of the groove formed semiconductor substrate; By using the second mask pattern as an etch mask, the interlayer insulating layer is further etched such that a bit line contact region of the active region of the bottom surface of the groove is exposed and a partial thickness remains on the device isolation layer corresponding to the bit line contact region. Doing; And Removing the first and second mask patterns; Method of manufacturing a semiconductor device comprising a. The method of claim 8, Etching the interlayer insulating film, Forming a mask film on the interlayer insulating film; Exposing the mask layer to form a first mask pattern exposing the active region; Using the first mask pattern as an etching mask, etching a portion of the interlayer insulating layer to form a groove; Further exposing the first mask pattern remaining after the etching to form a second mask pattern exposing the device isolation layer corresponding to the active region and the bit line contact region; Further etching the interlayer insulating layer using the second mask pattern as an etch mask to expose an active region of the bottom surface of the groove and to leave some thickness on the device isolation layer corresponding to the bit line contact region; And Removing the second mask pattern; Method of manufacturing a semiconductor device comprising a. The method of claim 8, Etching the interlayer insulating film, Forming a barrier film on the interlayer insulating film; Forming a first mask pattern exposing an active region on the barrier layer; Using the first mask pattern as an etch mask, etching the barrier film portion to expose the interlayer insulating film to form a barrier pattern exposing an active region on the interlayer insulating film; Removing the first mask pattern; Forming a second mask pattern on the barrier pattern to expose an isolation layer corresponding to an active region and a bit line contact region; By using the second mask pattern as an etching mask, the interlayer insulating layer is etched to expose the bit line contact region of the active region, and at the same time, the barrier pattern on the device isolation layer corresponding to the bit line contact region is removed and beneath it. Etching a portion of the interlayer insulating film in thickness; And Removing the barrier pattern and the second mask pattern; Method of manufacturing a semiconductor device comprising a. The method of claim 18, The barrier film is a semiconductor device manufacturing method characterized in that it comprises a nitride film. The method of claim 18, The barrier film is a method of manufacturing a semiconductor device, characterized in that formed to a thickness of 300 ~ 700Å. The method of claim 18, The second mask pattern may be formed as a bar type to expose an active region, a device isolation layer corresponding to a bit line contact region, and a device isolation layer between the active regions in the long axis direction of the active region. Way. The method of claim 18, The barrier pattern has a lower etching speed than the interlayer insulating film. The method of claim 8, After etching the interlayer insulating film, and before forming the plug, Cleaning the semiconductor substrate on which the interlayer insulating layer is etched; Method of manufacturing a semiconductor device further comprising. The method of claim 23, And the cleaning is performed in a dry manner. The method of claim 23, The cleaning is a method of manufacturing a semiconductor device, characterized in that performed using a mixed gas of NH ₃ + HF.

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