KR20090032879A - Method for manufacturing semiconductor device - Google Patents

Abstract

A formation method of a semiconductor device is provided to prevent the SAC(Self Align Contact) fail between a landing plug contact and a passing gate by forming a landing plug of the storage electrode and an isolation structure of the passing gate. An element isolation film(14) defining an active region(12) is formed in a semiconductor substrate. A photosensitive pattern defining the SEG(Selective Epitaxial Growth) reserved region of the active region through the exposure development process is formed. An Epitaxial layer(13) of the active region is formed by performing the SEG process. A gate recess region is formed by etching the gate recess reserved region of the growth layer of the active region. A gate electrode material layer(22), a gate conductive material layer(24), and a gate hard mask material layer(26) are successively laminated. A gate pattern(28) is formed by successively etching the gate electrode material layer, the gate conductive material layer, and the gate hard mask material layer. A gate spacer(30) is formed in the side wall of the gate pattern.

Description

Method for forming a semiconductor device {Method for manufacturing semiconductor device}

1A to 1I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

<Description of the symbols for the main parts of the drawings>

12: active area

13. Growth layer

14: device separator

16: photoresist pattern

18: nitride film pattern

20: recessed area

22: gate electrode material

24: gate conductive layer material

26: gate hard mask material

28: gate pattern

30: gate spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, a step is generated between a passing gate and an operation gate because a step is formed between the passivation gate and the operation gate after the device isolation layer is formed to grow an active region. Self Align Contact (SAC) between the passing gate and the landing plug contact because it reduces the Passing Gate Effect and the Neighbor Gate Effect and separates the landing plug from the storage electrode and the passing gate. The present invention relates to a method for forming a semiconductor device capable of preventing a fail.

As the semiconductor device becomes more integrated, the short channel effect (SCE) is reduced, which decreases the channel length as the gate's critical dimension (CD) decreases and thus decreases the electrical characteristics of the field effect transistor (FET). Occurred.

In order to overcome this problem, multi-channel FETs (MFETs) such as recessed gates, fin type gates and saddle type gates have been used.

Here, the recessed gate is a gate structure that increases a channel length by etching a semiconductor substrate in a gate predetermined area by a predetermined depth.

On the other hand, the fin type gate (Fin Type Gate) is a gate structure that can form an active region in the form of a fin to increase the contact area between the active region and the gate to increase the driving ability of the gate and improve the electrical characteristics.

In addition, the saddle type gate forms a fin type active region by etching the gate predetermined region of the device isolation layer, and forms a recessed region by etching the gate predetermined region of the active region to complete the saddle type gate structure. .

Here, the saddle-type gate has the advantage that the operating voltage increases, but there is a problem that the parasitic capacitor (Parasitic Capacitor) occurs.

On the other hand, as semiconductor devices are highly integrated, process margins for forming active regions and device isolation layers are reduced.

Therefore, since the distance between the device isolation layers defining the active region is reduced, the characteristics of the cell transistors are affected by the neighboring gate effect and the passing gate effect, which are parasitic field effects. There was a problem of deterioration. Here, the Passing Gate Effect, one of the Parasitic Field Effects, is a source junction and a channel that act as a barrier for electrons to enter a channel from a source. Since the potential difference in the vicinity biases the neighboring and passing gates and increases the electric potential around it, it reduces the electric potential difference between the channel and the source junction region, It is a phenomenon in which the cell transistor threshold is reduced due to the easy inflow of electrons into the channel. Meanwhile, the neighbor gate effect is a phenomenon in which the threshold voltage of the cell transistor is decreased by increasing the vertical channel potential by decreasing the spacing between the operation recess gate and the neighboring recess gate. Say.

In the present invention, since a stepped portion is formed between the passivating gate and the operation gate because the active region is grown after the device isolation layer is formed to form a step, the passing gate effect and the neighboring gate effect are generated. It is an object of the present invention to provide a method for forming a semiconductor device that can reduce a (Neighbor Gate Effect).

In addition, in the present invention, since the active region is grown after the device isolation layer is formed to form a step with the device isolation layer, the landing plug and the passing gate of the storage electrode are separated from each other. Align Contact) It is an object of the present invention to provide a method for forming a semiconductor device capable of preventing a fail.

The method of forming a semiconductor device according to the present invention

Forming an isolation layer defining an active region;

Forming a hard mask pattern exposing the active region;

Forming a growth layer of an active region by performing a self epitaxial growth (SEG) on the active region using the hard mask pattern as a barrier;

Etching the active region including the growth layer to form a gate recess region; And

And forming a gate in the gate predetermined region using the gate mask.

In addition, the method of forming a semiconductor device according to the present invention

The isolation layer is formed by a shallow trench isolation (STI) method,

Forming the hard mask pattern is

Depositing the hard mask material layer over the entire surface;

Applying a photoresist film on the hard mask material layer;

Forming a photoresist pattern on the photoresist to expose the active region through an exposure and development process; And

Etching the hard mask material layer by using the photoresist pattern as an etching mask;

The hard mask material layer is formed of a nitride film,

Removing the hard mask material layer using a selected one of a buffer oxide etchant (BOE) solution, H 3 PO 4, and a combination thereof;

The BOE solution is a chemical solution consisting of BOE and De-Ionized Water (DIW) in a ratio of 300: 1,

The growth layer of the active region is as small as 100 ~ 400 ~ from the longitudinal edge of the active region,

The growth layer of the active region is formed to 1000 ~ 2000Å thickness,

Forming the gate

Sequentially depositing a gate electrode material layer, a gate conductive material layer, and a gate hard mask material layer over the front surface; And

Sequentially etching the gate hard mask material layer, the gate conductive material layer, and the gate electrode material layer using the gate mask;

Planarizing the gate hard mask material layer;

The forming of the gate may further include forming a gate spacer on the gate sidewall.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the spirit of the present invention is thoroughly and completely disclosed, and the spirit of the present invention to those skilled in the art will be fully delivered. Also, like reference numerals denote like elements throughout the specification.

In the present invention, since a stepped portion is formed between the passivating gate and the operation gate because the active region is grown after the device isolation layer is formed to form a step, the passing gate effect and the neighboring gate effect are generated. Since a (Neighbor Gate Effect) is reduced and the landing plug and the passing gate of the storage electrode are isolated, a technique capable of preventing a self alignment contact (SAC) failure between the passing gate and the landing plug contact is disclosed.

1A to 1I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention. 1A to 1I are cross-sectional views cut perpendicular to the longitudinal direction of the gate.

Referring to FIG. 1A, an isolation layer 14 defining an active region 12 is formed in a semiconductor substrate. Here, the device isolation layer 14 is formed by a shallow trench isolation (STI) method.

Referring to FIG. 1B, a nitride film 16 is deposited on an upper surface of the front surface, a photosensitive film is coated on the nitride film 16, and a selective epitaxial growth (SEG) of the active region 12 is planned through an exposure and development process on the photosensitive film. The photosensitive film pattern 18 which defines an area | region is formed.

Subsequently, the nitride film is etched using the photosensitive film pattern 18 as an etching mask to form the nitride film pattern 16, and the photosensitive film pattern 18 is removed.

Referring to FIG. 1C, an epitaxial layer 13 of the active region 12 may be formed by performing a SEG process on an SEG predetermined region of the active region 12 using the nitride film pattern 16 as a barrier. To form. Here, the growth layer 13 is formed to be as small as 100 ~ 400 로부터 from the longitudinal edge of the active region. In addition, the growth layer 13 is formed to a thickness of 1000 kPa to 2000 kPa.

Referring to FIG. 1D, the nitride layer pattern 16 is removed using one of a buffer oxide etchant (BOE) solution, H 3 PO 4, and a combination thereof. Here, the BOE solution uses a chemical solution consisting of BOE and De-Ionized Water (DIW) in a ratio of 300: 1.

Referring to FIG. 1E, the gate recess region 20 of the growth layer 13 of the active region 12 is etched to a predetermined depth using a mask defining a gate recess region to form the gate recess region 20. .

1F and 1G, the gate electrode material layer 22, the gate conductive material layer 24, and the gate hard mask material layer 26 are sequentially deposited. In this case, a planarization process is performed on the gate hard mask material layer 26. Here, the gate electrode material layer 22 is formed using polysilicon, the gate conductive material layer 24 is formed using tungsten (WSIX), and the gate hard mask material layer 26 is formed. Is formed using a nitride film.

Referring to FIG. 1H, the gate electrode material layer 22, the gate conductive material layer 24, and the gate hard mask material layer 26 are sequentially etched using a gate mask to form a gate pattern 28.

Referring to FIG. 1I, a gate spacer 30 is formed on sidewalls of the gate pattern 28. Here, the gate spacer 30 is formed by depositing a nitride film on the entire top surface including the gate pattern 28 and performing a blanket etching and cleaning process on the nitride film.

As described above, in the present invention, since the active region is grown after forming the device isolation layer to form a step with the device isolation layer, a step is generated between the passing gate and the operation gate, thereby causing a passing gate effect. ) And the neighbor gate effect can be reduced.

In addition, in the present invention, since the active region is grown after the device isolation layer is formed to form a step with the device isolation layer, the landing plug and the passing gate of the storage electrode are separated from each other. Align Contact) There is an effect that can prevent the failure.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (11)

Forming an isolation layer defining an active region; Forming a hard mask pattern exposing the active region; Forming a growth layer of an active region by performing a self epitaxial growth (SEG) on the active region using the hard mask pattern as a barrier; Etching the active region including the growth layer to form a gate recess region; And Forming a recess gate using the gate mask. The method of claim 1, The device isolation layer is formed using a shallow trench isolation (STI) method. The method of claim 1, wherein forming the hard mask pattern comprises: Depositing the hard mask material layer over the entire surface; Applying a photoresist film on the hard mask material layer; Forming a photoresist pattern on the photoresist to expose the active region through an exposure and development process; And Etching the hard mask material layer by using the photoresist pattern as an etching mask. The method of claim 3, wherein And the hard mask material layer is formed of a nitride film. The method of claim 4, wherein And removing the hard mask material layer using a selected one of a buffer oxide etchant (BOE) solution, H 3 PO 4, and a combination thereof. The method of claim 5, wherein The BOE solution is a semiconductor device forming method, characterized in that the chemical solution consisting of BOE and De-Ionized Water (DIW) in a ratio of 300: 1. The method of claim 1, The growth layer of the active region is a semiconductor device forming method, characterized in that as small as 100 ~ 400 로부터 from the longitudinal edge of the active region. The method of claim 1, The growth layer of the active region is formed in the semiconductor device forming method characterized in that the thickness of 1000 ~ 2000Å. The method of claim 1, wherein the forming of the recess gate is performed. Sequentially depositing a gate electrode material layer, a gate conductive material layer, and a gate hard mask material layer over the front surface; And And sequentially etching the gate hard mask material layer, the gate conductive material layer, and the gate electrode material layer using the gate mask. The method of claim 9, And planarizing the gate hard mask material layer. The method of claim 1, And forming the recess gate further comprising forming a gate spacer on the sidewall of the gate.

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