KR20090045012A - 실리콘 인터포저 제조 방법, 실리콘 인터포저 및 실리콘 인터포저를 구비하는 반도체 장치 패키지 및 반도체 장치 - Google Patents

실리콘 인터포저 제조 방법, 실리콘 인터포저 및 실리콘 인터포저를 구비하는 반도체 장치 패키지 및 반도체 장치 Download PDF

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Publication number
KR20090045012A
KR20090045012A KR1020080103373A KR20080103373A KR20090045012A KR 20090045012 A KR20090045012 A KR 20090045012A KR 1020080103373 A KR1020080103373 A KR 1020080103373A KR 20080103373 A KR20080103373 A KR 20080103373A KR 20090045012 A KR20090045012 A KR 20090045012A
Authority
KR
South Korea
Prior art keywords
hole
thermal expansion
hole electrode
silicon interposer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020080103373A
Other languages
English (en)
Korean (ko)
Inventor
마사히로 스노하라
Original Assignee
신꼬오덴기 고교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20090045012A publication Critical patent/KR20090045012A/ko
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
KR1020080103373A 2007-10-30 2008-10-22 실리콘 인터포저 제조 방법, 실리콘 인터포저 및 실리콘 인터포저를 구비하는 반도체 장치 패키지 및 반도체 장치 Withdrawn KR20090045012A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2007-281345 2007-10-30
JP2007281345A JP5311609B2 (ja) 2007-10-30 2007-10-30 シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置

Publications (1)

Publication Number Publication Date
KR20090045012A true KR20090045012A (ko) 2009-05-07

Family

ID=40377454

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080103373A Withdrawn KR20090045012A (ko) 2007-10-30 2008-10-22 실리콘 인터포저 제조 방법, 실리콘 인터포저 및 실리콘 인터포저를 구비하는 반도체 장치 패키지 및 반도체 장치

Country Status (4)

Country Link
US (1) US7851359B2 (https=)
EP (1) EP2056343A3 (https=)
JP (1) JP5311609B2 (https=)
KR (1) KR20090045012A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120010616A (ko) * 2010-07-21 2012-02-06 삼성전자주식회사 적층 패키지, 반도체 패키지 및 적층 패키지의 제조 방법
US9196506B2 (en) 2009-09-14 2015-11-24 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing interposer

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4833307B2 (ja) * 2009-02-24 2011-12-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体モジュール、端子板、端子板の製造方法および半導体モジュールの製造方法
JP5532744B2 (ja) * 2009-08-20 2014-06-25 富士通株式会社 マルチチップモジュール及びマルチチップモジュールの製造方法
JP5367523B2 (ja) * 2009-09-25 2013-12-11 新光電気工業株式会社 配線基板及び配線基板の製造方法
US20110089531A1 (en) * 2009-10-16 2011-04-21 Teledyne Scientific & Imaging, Llc Interposer Based Monolithic Microwave Integrate Circuit (iMMIC)
US8723049B2 (en) 2011-06-09 2014-05-13 Tessera, Inc. Low-stress TSV design using conductive particles
CN106783787B (zh) * 2017-01-24 2025-04-04 深圳市槟城电子股份有限公司 用于芯片封装的电极以及使用该电极的芯片封装结构
US20240224422A1 (en) * 2021-01-28 2024-07-04 Kyocera Corporation Wiring board

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266181A (en) * 1991-11-27 1993-11-30 C. Uyemura & Co., Ltd. Controlled composite deposition method
US5614043A (en) * 1992-09-17 1997-03-25 Coors Ceramics Company Method for fabricating electronic components incorporating ceramic-metal composites
JPH0790413A (ja) * 1993-09-22 1995-04-04 Sumitomo Special Metals Co Ltd 複合材料
US6193910B1 (en) * 1997-11-11 2001-02-27 Ngk Spark Plug Co., Ltd. Paste for through-hole filling and printed wiring board using the same
JP4246132B2 (ja) * 2004-10-04 2009-04-02 シャープ株式会社 半導体装置およびその製造方法
JP4698296B2 (ja) * 2005-06-17 2011-06-08 新光電気工業株式会社 貫通電極を有する半導体装置の製造方法
JP2007027451A (ja) * 2005-07-19 2007-02-01 Shinko Electric Ind Co Ltd 回路基板及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9196506B2 (en) 2009-09-14 2015-11-24 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing interposer
KR20120010616A (ko) * 2010-07-21 2012-02-06 삼성전자주식회사 적층 패키지, 반도체 패키지 및 적층 패키지의 제조 방법

Also Published As

Publication number Publication date
JP5311609B2 (ja) 2013-10-09
US7851359B2 (en) 2010-12-14
US20090121345A1 (en) 2009-05-14
EP2056343A2 (en) 2009-05-06
EP2056343A3 (en) 2011-09-21
JP2009111120A (ja) 2009-05-21

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PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000