KR20090033464A - A nano imprint technique with increased flexibility with respect to alignment and feature shaping - Google Patents

Abstract

By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.

Description

Nano imprint technology with increased flexibility in alignment and feature molding {A NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO ALIGNMENT AND FEATURE SHAPING}

TECHNICAL FIELD The present invention relates to the field of microstructures manufacturing, and more particularly, to a method of defining microstructured features based on nanoimprint technology.

In the manufacture of microstructures such as integrated circuits, very small areas with precisely controlled sizes to be formed in the material layers of suitable substrates, such as silicon substrates, are needed. These very small areas with precisely controlled sizes are formed by patterning the material layer, for example by performing photolithography and etching processes. For this purpose, in conventional semiconductor technology, a mask layer is formed over the material layer to first define this very small area in the mask layer. In general, the mask layer may consist of a photoresist layer patterned by a lithography process, such as a photolithography process, or may be formed using such a photoresist layer. During a typical photolithography process, the resist can be spin coated onto the wafer surface and then selectively exposed to ultraviolet radiation. Depending on the type of resist (positive resist or negative resist), after developing the photoresist, the exposed or unexposed portions are removed to form the required pattern in the photoresist layer. As the dimensions of patterns in finely crafted integrated circuits are steadily decreasing, the equipment required for patterning device features is subject to very stringent requirements regarding the resolution and overlay accuracy of the associated manufacturing process. Must be satisfied. In this regard, resolution is considered as a dimension that specifies a consistent ability to print images of minimum size under predefined manufacturing variation conditions. One important factor in improving the resolution is represented by the phytography process, wherein the pattern contained in the photomask or reticle is optionally transferred to the substrate via an optical imaging system. Thus, much effort has been made to steadily improve the optical properties of lithographic systems such as numerical aperture, depth of focus, and wavelength of light source used.

The quality of a lithographic image is very important in producing very small feature sizes. However, accuracy is at least comparably important, with which accuracy an image can be placed on the surface of the substrate. Various types of microstructures, for example integrated circuits, are fabricated by sequentially patterning material layers, wherein the features on the continuous material layers have well defined spatial relationships with each other. Each pattern formed in the subsequent material layer must be aligned with the corresponding pattern formed in the previously patterned material layer within specified registration tolerances. This registration tolerance is caused by variations in the photoresist image on the substrate due to non-uniformities in parameters such as resist thickness, baking temperature, exposure and development, for example. Moreover, the nonuniformity of the etching process may also result in variations of etched features. In addition, there is uncertainty in overlaying an image of the pattern for the current material layer on the etched pattern of the previously formed material layer, while photolithographically transferring the image onto the substrate. Several factors contribute to the image system's ability to completely overlay the two layers, such as imperfections in the set of masks, temperature differences at different exposure times, and limited registration performance of the alignment tool. There is this. As a result, the dominant criteria for determining the minimum feature size that can be finally obtained are the resolution and global overlay error for creating features in the individual substrate layers, and the factors described above, in particular the lithographic process, Contribute.

For continuous scaling of microstructures, it is necessary to adjust the photolithography system correspondingly in terms of exposure wavelength, beam optics, alignment means, etc. to provide the required resolution, but this is a huge burden on the tool manufacturer in terms of development efforts. At the same time, manufacturers of microstructures must increase tool investments and pay significant cost of ownership. Accordingly, new techniques have been proposed to define microstructured features in each layer of material and at the same time avoid or reduce some of the problems associated with conventional photolithography techniques. One promising approach is nanoimprint technology, which is a method of mechanically transferring a pattern defined in a mold or die to a suitable mask layer, which can then be used to pattern the material layer. For example, during the fabrication of metallization layers of elaborately fabricated semiconductor devices, which require metal structures with reduced feature size, low parasitic capacitance, and high resistance to electrical movement, so-called inlay techniques ( inlaid technique or damascene technique is used. In this technique of forming a wiring layer providing a complex circuit layout of an integrated circuit, a suitable dielectric material is patterned to accommodate the trenches and vias, which are subsequently subjected to highly conductive materials such as copper, copper alloys, silver , Or any other suitable metal. Thus, the vias providing electrical connection between the metal regions of the stacked different metallization layers must be precisely aligned with respect to the metal regions, such as the metal lines, wherein the lateral dimensions of the metal lines and vias are at least below. In metallization layers, comparable to the minimum critical dimension, whereby very sophisticated lithography techniques are required. In addition, the surface morphology at higher device layers will have to be fully controlled for the optical patterning technique, which requires a very sophisticated planarization technique since it uses a low-k dielectric material. k dielectric material may have reduced mechanical stability compared to "conventional" dielectric materials such as silicon dioxide, silicon nitride, and the like. Thus, by avoiding the optical patterning method, each trench or via can be formed based on nanoimprint technology, where a resist material or any other mask material is contacted by the corresponding die, the corresponding die being a metal line It has a relief that includes each line and space for forming the trench when a trench for the trench is to be formed. In the next process step, a mask layer can be used to transfer the pattern from the mask layer to the dielectric material of the material layer, for example the metallization layer.

By using nanoimprint technology, many problems associated with photolithography can be avoided, but the trench defined by the imprint process must be precisely aligned with the previously formed vias, thereby imprint process technology also has very strict constraints. . In other cases, nanoimprint techniques have reduced flexibility in shaping the opening when formed directly in the interlayer dielectric material, because, for example, tapered shapes are used as an efficient control method in conventional photolithography techniques. Adjusting exposure and / or etching parameters to obtain a shape may no longer be available.

The present invention is directed to various methods that can solve or at least reduce some or all of the aforementioned problems.

The following provides a simplified overview of the invention to provide a basic understanding of some embodiments of the invention. This summary is not an overview of the invention. This is not intended to identify key or critical elements of the invention or to limit the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the detailed description of the invention that is presented later.

In general, what is described herein forms a microstructured feature, such as a semiconductor device, using techniques in which mechanical interaction is used to form or provide respective features, such as conductive lines, vias, and the like, within a particular material layer. It is about technology. For this purpose, the degree of flexibility is, in some embodiments, greatly reduced the number of process steps required to form the metallization layer of the semiconductor device, for example in that via openings and trenches can be defined in a common imprint process. Can be reinforced.

In other embodiments, sidewall configurations of trenches, vias, etc., can be effectively adjusted based on a correspondingly designed imprint mold or die to obtain a non-vertical sidewall portion, for metallization layers or the like. This is because a plurality of specific device features such as trenches and openings may be used. As a result, by reducing the process complexity of the imprint technology and / or providing enhanced flexibility in shaping each feature, the overall performance of each microstructured device can be enhanced with a reduction in process complexity, because For example, any critical alignment operation may be reduced and / or the process performance of certain circuit features may be enhanced, for example when improved metallization structures of sophisticated semiconductor devices are considered. Because you can get.

According to one exemplary embodiment disclosed herein, a method is provided that includes commonly imprinting via openings and trenches in a layer of deformable material formed over a substrate, wherein the via openings and trenches are formed of a microstructure device. Corresponds to the features of the metallized structure. Moreover, the method includes forming vias and conductive lines based on via openings and trenches.

According to another exemplary embodiment disclosed herein, the method includes imprinting an opening in a layer of deformable material formed over a substrate, wherein the opening corresponds to a feature of the microstructured device and is non-vertical to the bottom of the opening. Has a sidewall portion with an orientation. Moreover, the method includes forming a feature based on the opening, wherein the feature has a sidewall portion that is non-perpendicular to the bottom of the feature.

According to yet another exemplary embodiment disclosed herein, a method is provided that includes forming a metallization layer for a semiconductor device and mechanically transferring the metallization layer to a substrate on which a plurality of circuit elements are formed. .

The disclosure of the present specification may be understood with reference to the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals refer to like elements.

1A-1E are cross-sectional views of a microstructure during formation of via / line metallization structures in a common imprint process for directly forming respective openings in an interlayer dielectric material, in accordance with exemplary embodiments disclosed herein. It is shown schematically.

2A-2D schematically illustrate cross-sectional views of a microstructured device during fabrication of a via / line metallization structure based on a common imprint process with a subsequent etching process in accordance with another exemplary embodiment.

3A-3E schematically illustrate cross-sectional views during various fabrication steps for forming via / line structures based on a common imprint process with subsequent removal of dielectric material in accordance with yet another exemplary embodiment.

4A-4C diagrammatically illustrate a process flow for forming a negative form of an imprint mold or die, ie, via / line structures, according to another exemplary embodiment.

FIG. 5 schematically illustrates a diagram for mechanically transferring one or more metallization structures to a substrate including a plurality of circuit elements, according to another exemplary embodiment disclosed herein.

6A-6C diagrammatically illustrate cross-sectional views of a plurality of imprint molds or dies having non-vertical sidewall configurations of each negative type of metallization features for semiconductor devices, in accordance with example embodiments disclosed herein. It is shown.

7A-7B schematically illustrate cross-sectional views of a semiconductor device during formation of a isolation trench based on a tapered shaped imprint die or mold according to another embodiment.

8A-8D are cross-sectional views of semiconductor devices during various fabrication steps for forming conductive lines, such as gate electrodes, having modified sidewall configurations obtained by imprint techniques in accordance with another exemplary embodiment disclosed herein. It is shown schematically.

Various modifications and alternative forms to those disclosed herein are possible, and specific embodiments thereof are shown in the drawings for illustrative purposes and described in detail herein. It is to be understood, however, that the description herein of these specific embodiments is not intended to limit the invention to these specific forms disclosed, and on the contrary, the spirit of the invention as defined by the appended claims. And all variations, equivalents, and alternatives falling within the scope.

Various exemplary embodiments of the invention are described below. For clarity, not all features of an actual implementation are described in this specification. It should be understood, of course, that in the development of any such practical embodiment, in order to achieve compatibility with system-specific and business-related constraints that may vary from developer to particular purpose, eg implementation. Various specific decisions as needed have to be made. Moreover, as should be understood, such development efforts are complex and time consuming, but are routine tasks for those of ordinary skill in the art that nevertheless benefit from the present disclosure.

The present invention is now described with reference to the accompanying drawings. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The terms and phrases used herein should be understood and interpreted to have a meaning consistent with those terms and phrases understood by those skilled in the art. Any special meaning of a term or phrase, that is, a definition different from the usual and general meaning understood by those skilled in the art, is implied through the consistent use of the term or phrase as used herein. Not. If any term or phrase has a special meaning, that is, if it has a meaning different from what a skilled person would understand, such a special definition is a form of definition that provides no direct ambiguity to that particular definition of the term or phrase. As is clearly described herein.

Generally, what is described herein relates to a technique for forming a microstructured feature, such as a semiconductor device, wherein at least some of the photolithography steps are replaced with an imprint technique, in which the feature or at least a feature is formed. A mimic layer for forming is formed by direct mechanical contact between the deformable material and the corresponding imprint mold or nano die or stamp, and in some embodiments, two different types of features may be formed in a common imprint process. The number of alignment processes required can thus be reduced, and the number of individual process steps such as deposition, planarization, and the like can be reduced. In another embodiment, shaping of each feature can be accomplished by appropriately designing each imprint mold so that the performance of each feature can be enhanced and / or the performance of each patterning process can be enhanced. . For example, in some example embodiments, tapered shaped vias or trenches may be formed based on correspondingly designed imprint dies or molds, so that correspondingly reliably fill conductive materials such as metals, metal alloys, and the like. The filling operation of the deposition process can be greatly enhanced. As a result, overall process efficiency and production costs can be reduced, because in many manufacturing steps, expensive and extensive and complex photolithography steps can be avoided, or each photolithography process can be used to form an appropriate imprint mold. This is because the efficiency of each photolithography process can be greatly increased, which means that, through a single photolithography process, a corresponding imprint mold or die can also be created that can also be used to process multiple substrates. Because there is.

1A schematically illustrates a microstructure device 100, and in some exemplary embodiments, it may house a metallization structure to electrically connect respective circuit elements such as transistors, capacitors, resistors, and the like. Which can represent a semiconductor device. In other cases, microstructure device 100 may represent a device on which optoelectronic devices and / or mechanical devices and the like are formed. Microstructure device 100 may include substrate 101, which, when silicon-on-insulator (SOI) architecture is contemplated, is buried in an insulating layer (not microscopic). Any suitable substrate, such as a silicon-based semiconductor substrate, which may include a), in which case an appropriate semiconductor layer is formed on each insulating layer. In other cases, substrate 101 may represent any suitable carrier material having a suitable layer of material formed thereon that enables the manufacture of each of the components, at least some of each of which components being electrically interconnected between the respective circuit elements. Corresponding metallization structures may be required to provide a connection. In another case, the substrate 101 may represent any suitable carrier material, on which a metallization structure can be formed that can be transferred to each semiconductor device in subsequent steps, as described in more detail below. Can be. In some example embodiments, a plurality of features are formed in the substrate 101 including respective contact regions 102, which may be provided in the form of highly conductive semiconductor regions, metal regions, and the like. Moreover, a deformable material layer 103 can be formed over the substrate 101, where in the embodiment illustrated in FIG. 1A, the layer 103 can represent a suitable dielectric material for forming the features of the metallized structure. have.

For example, in some exemplary embodiments, the deformable material of layer 103 may consist of a dielectric having a dielectric constant of 3.0 and significantly less, which is typically a low-k dielectric or an ultra low-k dielectric. It is also mentioned. As should be understood, the term “deformable” refers to a material property that enables mechanical contact with the negative shape of an imprint mold or die, ie an opening to be formed in material layer 103, so that the deformable material is It can be deformed and subsequently each imprint die can be removed, where the deformable material 103 can substantially maintain the deformed shape after removal of the imprint mold. For example, a wide variety of thermoplastics are available, which may be low in viscosity when heat is applied and each material 103 may deform in this low viscosity, where after the thermoplastic has cooled, Each deformed shape may be maintained even after removal of the deformed imprint die. In other cases, each material, such as a polymeric material, a resist material, or the like, may be provided in a low viscosity state, and, for example, after UV contact, heat treatment, etc., to maintain the deformed shape after contact with each imprint mold. Can be cured on the basis of.

In the embodiment shown in FIG. 1A, contact with each imprint mold or die 150 may include a substrate 151 made of any suitable material, such as silicon, silicon dioxide, metal, metal alloy, any plastic material, and the like. Previous microstructure device 100 is shown. Moreover, the imprint mold 150 can include a plurality of negative shapes 152 of each complex opening to be formed in the material layer 103. In the illustrated embodiment, negative form 152 may include via portion 152A and trench portion 152B, which will correspond to respective vias and metal lines of the metallization structure to be formed in dielectric layer 103. Can be. For example, in elaborately fabricated microstructured devices, such as device 100, depending on the level of the metallization structure in question and the minimum critical dimension for any circuit elements of device 100, the order may be approximately 100 nm to several. Each metal line or other conductive line having a width of μm may be formed.

As previously described, each feature of the metallization structure is typically formed based on photolithography and the corresponding etching process, where high complexity lithography tools are needed that include high complexity alignment entities. During each fabrication sequence to form the vias and the metal lines connected thereto, regardless of the process strategy considered, the trenches and vias must be aligned with respect to each other, which in turn must be considered by each design rule. Can cause alignment errors. By using the imprint mold 150 comprising each negative shape 152A of the corresponding via opening and negative shape 152B representing each twirl, the via and metal lines are automatically aligned with respect to each other with high precision. This reduces process complexity, increases device performance, and reduces process margins that must normally be provided to account for some degree of misalignment between via openings and trenches.

A typical process flow for forming microstructure device 100 may include the following processes. Based on well-established techniques, which may include a photolithography process or other imprint process, as described later, an implantation process, an etching technique, a planarization process, etc., if provided, the conductive region 102 or any After formation of any microstructured feature, such as other circuit elements, the deformable material of layer 103 may be formed based on any suitable deposition technique. For example, layer 103 may be applied at a low viscosity state by spin-on technology, and may be maintained at a low viscosity state, in which case it is curable, such as certain polymeric materials, deformable resist materials, and the like. It is a substance. In another exemplary embodiment, the layer 103 can be formed by any suitable deposition technique, and when a thermoplastic material is used, it is appropriate to transition to a high deformable state, for example by heat treating the layer 103. Can be processed. Next, the imprint mold 150 is placed and aligned with respect to the microstructure 100 based on well-established alignment tools using, for example, respective mechanical alignment marks (not shown), optical alignment marks, and the like. After properly placing the imprint mold 150 and the microstructure 100 relative to each other, the imprint mold 150 and / or the microstructure device 100 are relative to each other as indicated by arrow 153. While their lateral position is substantially maintained.

1B schematically illustrates the microstructure device 100 when in contact with the imprint mold 150, where each negative shape 152 defines a layer of deformable material 103 to define via openings and trenches. Transform. Afterwards, the material of layer 103 is in a substantially non-deformable state, i.e., after removal of imprint mold 150 with the required high fidelity, the material layer 103 is in a state capable of substantially maintaining its shape. For example, the layer 103 can be processed by curing the layer 103 by appropriate treatment such as Ultra Violet (UV) radiation or the like, for example by reducing its temperature.

1C schematically depicts the microstructure device 100 when the imprint mold 150 is removed, as indicated by arrow 154, wherein the imprint mold 150 is removed, thereby substantially removing the material 103. Due to the non-deformable state, each imprinted structure 104 including via opening 104A and trench 104B is left, each of which is a negative form of each of the imprint mold 150 in size and shape. Substantially corresponds to 152A, 152B. It should be understood that the imprint mold 150 may have low adhesion in a substantially undeformable state to the material of the layer 103, which may be achieved by using a well-established technique for the nanoimprint process to achieve individual surface treatment or It can be achieved based on the substance component. Moreover, during the common imprint of via opening 104A and trench 104B to layer 103, the height level of the material in layer 103 may vary due to the additional volume of each negative form 152. Here, each increase in height level may vary locally, depending on the pattern density of each negative form 152 throughout the substrate 101. For example, due to the pattern configuration of the negative form 152B that substantially suppresses fluid communication in the final step of placing the imprint mold 150 in the material 103, the layer 103 may be formed throughout the substrate 101. When fluid communication between each of the parts cannot be provided, the mold 150 may provide respective fluid channels that can provide efficient communication between different device parts or that can remove excess material in the layer 103. (Not shown). As a result, when removing the imprint mold 150 from the layer 103 in a substantially non-deformable state, a substantially flat surface configuration can be obtained, where the material of the layer 103 becomes non-deformable. Depending on whether the excess material of layer 103 has been removed previously, the thickness of layer 103 may be different from the thickness of layer 103 originally deposited. Moreover, each material residue 104C may still be present at the bottom of each via opening 104A due to a small non-uniformity in the surface morphology of microstructure 100 and / or imprint mold 150, As a result, incomplete mechanical contact with underlying structures such as conductive region 102 may occur.

1D schematically illustrates the microstructure device 100 in a further manufacturing step, where the structure 100 is placed in an etch atmosphere 105 to remove material residue 104C. During the etching process 105, a well-established method can be used to efficiently remove the residue 104C, where for some exemplary embodiments, the etching of the process 105 with respect to the material of the conductive region 102. A constant selectivity of chemistry can be provided. In this manner, the process time of the etching process 105 can be controlled to reliably remove the residue 104C across the entire substrate 101 without substantially causing inadequate damage to the underlying region 102. . Moreover, due to the etching process 105, the material of the layer 103 can be removed out of the via opening 104A, but where each depth of the trench 104B is a trench 104B and a layer 103. Due to the simultaneous material removal at the horizontal surface portion 103S of Eq.), It may remain substantially the same, while the overall thickness of the layer 103 is dependent on the degree of overetching during the process 105. Can be reduced accordingly. The microstructure device 100 will then fill each structure 104 with a conductive material such as metal, metal alloy, etc. to provide respective vias and metal lines to form respective metallized structures of the microstructure 100. You can be prepared.

FIG. 1E schematically illustrates the microstructure device 100 at a further stage of manufacture, where each via 106A is provided in a previously formed via opening 104A and connected to an underlying conductive region 102. . Furthermore, conductive line 106B is formed in trench 104B previously defined. As a result, a material layer 103 representing any suitable dielectric material may define each metallization layer 107 along with conductive lines 106B and vias 106A, where each conductive line 106B This inner level provides electrical connection, while via 106A provides electrical contact to conductive region 102, which may include contact plugs, contact regions of circuit elements, metal regions of underlying metallization layers, and the like. Can be represented. It should be understood that, depending on the technical style of the microstructure 100 in question, the lateral dimension, i.e., the horizontal extension of the vias 106A and the conductive lines 106B in FIG. It may be much smaller than this, where each dimension may vary with device level, and with each current density that occurs during operation of microstructure device 100. Moreover, as should be understood, the specific shape of each via and / or conductive line 106B may vary depending on design requirements. For example, the width and / or depth of each conductive line 106B may vary at the same device level, thereby providing high flexibility in adapting each metallization structure to operating conditions, process conditions of deposition techniques, and the like. May be provided. The same is valid for via 106A. Moreover, vias 106A and conductive lines 106B may be formed based on any suitable conductive material, wherein in sophisticated applications, highly conductive metals such as copper, copper alloys, silver, silver alloys, etc., have high performance metallization. It can be used to provide a structure. Depending on the nature of the conductive material to be filled in each via opening 104A and trench 104B, the conductive material may also include a conductive barrier layer to the peripheral dielectric material of layer 103 and finally to the sensitive device region. Diffusion of metals can be substantially prevented, and unwanted interactions between the dielectric material or reactive components such as oxygen, fluorine, etc. contained therein, with each conductive material such as copper, copper alloy, etc. Can be suppressed.

The microstructure 100 shown in FIG. 1E can be formed based on the following process. After the etching process 105 (FIG. 1D), in some exemplary embodiments, each conductive barrier material (not shown) may be applied to any suitable deposition technique, such as sputter deposition, chemical vapor deposition, CVD. ), Electroless plating, atomic layer deposition (ALD), and the like. For example, suitable materials such as tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, and the like may be deposited by sputter deposition, where it may be performed as an etching process 105 or as an additional etching step. Previous sputter etching steps that result can reliably expose the underlying conductive region 102. Thereafter, a suitable seed material such as copper may be deposited by, for example, sputter deposition, electroless deposition, or the like, followed by deposition of bulk metal such as copper, copper alloy, silver, silver alloy, or the like. Next, any excess material, such as barrier material, seed material and actual bulk metal, can be removed based on any suitable technique, such suitable techniques include electromechanical etching, chemical mechanical polishing (CMP) Etc. may be included. In some exemplary embodiments, while each of the excess material is removed, a CMP process may be performed, whereby the surface morphology of the microstructured device 100 is also flattened, possibly via vias 104A and trenches. It can be generated during the common imprint process to form 104B (FIG. 1C).

As a result, metallization layer 107 including vias 106A and conductive lines 106B, which may have any suitable size and shape, can be easily formed into highly efficient process sequences with reduced process complexity, because This is because vias 106A and metal lines 106B can be formed based on a common lithography process without requiring individual alignment for each component. Moreover, the specific size and shape of the vias and lines 106A, 106B, and in particular the middle portions thereof, can be designed according to device requirements without being limited by photolithography and etching techniques, as in many conventional patterning methods. have. For example, the sidewalls of vias 106A and / or trench 106B can be easily adapted to process and device requirements, as described in greater detail below, in which case process techniques such as photolithography and etching processes It is not substantially limited to the specific process parameters of. Furthermore, in the embodiment shown with respect to FIGS. 1A-1E, vias 106A and line 106B may be formed directly in the dielectric material of metallization layer 107, ie in deformable material layer 103. And thereby the process complexity is also reduced.

With reference to FIGS. 2A-2D, another exemplary embodiment of what is disclosed herein is described in more detail, where high flexibility with respect to the dielectric material of the metallization layer is obtained, so that non-deformable materials can be effectively used. And vias and trenches may still be formed by common imprint techniques.

2A schematically illustrates a microstructure device 200 that includes a substrate 201, in which a conductive region 202 may be formed, and electrical connections to such conductive region may be formed over the substrate 201. Provided by one or more metallization layers. With respect to components 201 and 202, the same criteria apply as those previously described with respect to microstructure 100. Moreover, in this manufacturing step, a dielectric layer 207 can be provided with a substrate 201, where the material of the dielectric layer 207 can be selected as an interlayer dielectric material for the metallization layer, in its properties. have. For example, in sophisticated applications, dielectric layer 207 may comprise a low-k dielectric material. Moreover, mask layer 203 may be formed over dielectric layer 207, which may be composed of a deformable material, that is, a material that may have a high deformable state when mechanically contacted by imprint mold 250. In addition, such materials may be placed in a high undeformable state such that each degree of deformation caused by contact with the imprint mold 250 may be maintained. For example, the mask layer 203 may include a deformable resist material, thermoplastic material, and the like. Imprint mold or die 250 may include a respective substrate 251, on each substrate 251 a negative shape 252A for each via opening and its corresponding negative shape 252B corresponding to the trench. Each negative form 252 is formed that includes a. With regard to the imprint mold 250, the same criteria as previously described with reference to the mold 150 apply.

During the manufacturing step as shown in FIG. 2A, the imprint mold 250 is aligned with respect to the microstructure device 200, and similarly described above with respect to the device 100 and the mold 150, and the mold ( 250 is in contact with mask layer 203 as indicated by arrow 253, where mask layer 203 is in a low viscous state or a high deformable state.

2B schematically illustrates the situation when the imprint mold 250 is in contact with the mask layer 203, where each treatment, such as heat treatment and / or UV radiation, may be performed to The material may be in a high undeformable state.

2C schematically illustrates the removal of the imprint mold as indicated by arrow 254, thereby resulting in respective via openings 204A and trench 204B due to the substantially undeformable state of mask layer 203. Is generated. Regarding the characteristics of the imprint mold 250 in the surface adhesion, etc., the same criteria as described above with reference to the imprint mold 150 apply. Thus, after removal of the imprint mold 250, the patterned mask layer 203 serves as an image or mask during the subsequent anisotropic etching process for transferring the via openings 204A and trench 204B to the underlying dielectric layer 207. Can be used.

2D schematically illustrates the microstructured device 200 during the anisotropic etching process 205, where etch chemistry that results in an equivalent etch rate for the material of the mask layer 203 and the dielectric material of the underlying layer 207. This can be used. As a result, a high anisotropic etch operation can be established because no distinct etch selectivity between the materials of layers 203 and 207 is needed. Thus, during the etching process 205, the material of the mask layer 203 is gradually removed along the material of the exposed portion of the dielectric layer 207. In this manner, the vias 204A and trenches 204B of the mask layer 203 gradually “push” into the dielectric layer 206, with respective via openings 207A and trenches 207B in the dielectric layer 207. Is finally obtained, where high etch fidelity may be achieved due to the high anisotropic operation of process 205. Thus, in the final step of the etching process 205, the dielectric layer 207 may be covered with a residue of the mask layer 203 as indicated by 203R, while the etching process 205 may be via opening 207A. Continue to reliably expose each conductive region 202 at the bottom of the residue, where residue 203R may be consumed by the etching process 205. In some demonstrative embodiments, residue 203R may remain during the final stage of etching process 205, and subsequently further etching process, eg, material and dielectric layer 207 of residue 203R. A wet chemical process or a dry chemical process with high selectivity between) may be performed to remove residue 203R, thereby providing enhanced process flexibility, since the initial stage of mask layer 203 may be provided. This is because the thickness is less critical.

After removal of the residue 203R by the etching process 205 or subsequent additional etching steps, subsequent processing to the microstructured device 200 may be performed in a similar manner as previously described with respect to FIG. 1E for the device 100. It can be performed as. That is, any suitable process sequence can be performed such that a suitable conductive material, such as a barrier material, and a highly conductive metal can be filled, so that each via to define each metallization layer in common with the dielectric layer 107. And conductive lines may be provided. As a result, each metallization structure can be formed based on a highly efficient imprint process, where each via opening and trench can be formed in a common process step, while additionally providing a suitable dielectric material for the metallization layer. High flexibility is provided in the selection.

With reference to FIGS. 3A-3D, yet another exemplary embodiment is now described, wherein a metallization structure can be formed based on efficient imprint techniques, where each via opening and trench are defined and the metallization structure is defined. A sacrificial layer can be used to form.

3A schematically illustrates a cross-sectional view of a microstructure device 300 that includes a substrate 301 and a layer of deformable material 303 formed over the substrate 301. Moreover, an imprint mold 350, including the negative shape for the via opening 352A and the trench 352B, is shown while being removed from the layer 303, which shows the respective via opening 304A and trench ( Is in a high undeformable state to define 304B). With regard to the properties of the imprint mold 350, reference is made to the respective components 150 and 250 described above. Moreover, microstructure 300 may represent a microstructured device as described above with reference to devices 100 and 200 or may represent a base component for forming one or more metallized structures therein. Thus, the substrate 301 may represent any suitable carrier material for forming the deformable material layer 303 on the substrate, and in some exemplary embodiments, the substrate may have respective circuit elements and conductive regions ( (Not shown), on the other hand, in other embodiments, substantially no other functional components may be provided to the substrate 301. Deformable material layer 303 may be provided in the form of any suitable material, and its dielectric properties may not be essential, because layer 303 may be removed after respective via and metal lines are formed therein. Because it can be used as a sacrificial layer.

3B schematically illustrates the microstructure 300 at a further stage of manufacture. Respective vias 306A and conductive lines 306B are formed in sacrificial layer 303, where any suitable conductive material may be used to form vias 306A and lines 306B. In one exemplary embodiment, a suitable conductive high metal such as copper, copper alloy, silver, silver alloy, etc. may be filled in each via opening 304A and trench 304B (FIG. 3A), where each barrier material No previous step is needed to form a C, since the corresponding barrier property can be provided in a later step. In some exemplary embodiments, the surface portion of the substrate 301 may include any suitable catalytic material, such as palladium, platinum, copper, and the like, which may be exposed during the formation of the via openings 304A and trenches 304B. have. Thus, high efficiency electroless plating techniques can be used, for example based on copper and copper alloys, thereby typically in conventional electroplating schemes for reliably filling high aspect ratio openings from bottom to top. Any constraints on the filling behavior that may occur can be greatly relaxed. As a result, in combination with the highly efficient definition of each via opening 304A and trench 304B in a common imprint process, further reductions in process complexity and process performance can be obtained with regard to fill operation and barrier deposition.

3C schematically illustrates the microstructure device 300 during a selective isotropic etching process 308 to selectively remove the sacrificial layer 303 for the metallization structure 306. For this purpose, a high selective etching method can be used, where a high degree of flexibility is provided in selecting the appropriate material, because layer 303, regardless of its dielectric properties, has only required properties during the common imprint process. Because it is provided about.

3D schematically illustrates the microstructure device 300 at a further stage of manufacture. Here, device 300 is placed in a process 309 to form each barrier layer 310 on an exposed surface portion of metallization structure 306. As described above, for a plurality of highly conductive metals, such as copper, copper alloys, and the like, a reliable metal seal is required to suppress any interaction with the surrounding dielectric material. Moreover, due to the usual high current densities that can typically occur in very sophisticated integrated circuits, the electrophoretic effect can play a leading role in terms of overall reliability and lifetime of each metallization structure. Since electrophoretic phenomena are highly correlated with the presence of diffusion paths, any interface region can be particularly critical with respect to electrical movement, so that the overall electrophoretic behavior will vary greatly with the quality of each interface with the barrier material. Can be. As a result, since the barrier layer 310 is provided regardless of the presence of the surrounding dielectric material, a highly efficient manufacturing technique such as electroless plating can be used, whereby a reliable and uniform sealing of the metallization structure 306 is achieved. At the same time, additional highly effective barrier materials such as cobalt / tungsten / boron, cobalt / tungsten / phosphorus, etc. can be formed, which are known to exhibit high resistance to electrical transfer phenomena when combined with copper materials. As a result, by correspondingly exposing the surface portion of the metallization structure 306, each material can be deposited in a self-aligned manner, whereby the barrier layer 310 can be formed with high uniformity. As a result, the overall performance of each metallization structure 306 can be greatly increased, and at the same time, despite this, the process complexity can be reduced due to the common patterning of each via opening 304A and trench 304B. And the precision can be increased.

3E schematically illustrates the microstructure device 300 during the deposition process 311 to form an appropriate dielectric layer 307 to combine with the metallization structure 306 to define each metallization layer. . The deposition process 311 is a spin-on technique, CVD, for reliably sealing the metallization structure 306 with a suitable dielectric material, which may have a low dielectric constant that may be required for sophisticated integrated circuits. Any suitable deposition technique, such as techniques. Depending on the nature of the deposition process 311, any excess material of the dielectric layer 307 may be removed, for example by CMP, to provide a substantially flat surface morphology, where this process may be a barrier layer 310. Can be reliably stopped when exposing the upper portion of C), while in other exemplary embodiments, the CMP can be combined with a selective etching process, which is also to be controlled based on the exposure of the barrier layer 310. Can be.

4A-4B, yet further embodiments are described, where an appropriate imprint mold or die may be formed to provide a negative shape for the via opening with the trench.

4A schematically illustrates a cross-sectional view of an imprint mold or die 450 at a further stage of manufacture. Die 450 may include any suitable substrate 451, which may represent any suitable carrier material, which may allow for proper patterning according to the respective process technology on any suitable carrier material. The surface part is formed. For example, substrate 451 may represent a silicon substrate, on which a silicon layer, silicon dioxide layer, or any other suitable material is formed to form respective negative images or shapes of via openings and trenches. During subsequent processing to provide the required mechanical stability and respective etching characteristics. The corresponding negative shape of trench 452B may be formed in the upper portion of substrate 451 or in any suitable material layer provided on substrate 451, where negative shape 452B is It may be made of any suitable material, such as silicon dioxide, silicon nitride, and the like, which may have a high etch selectivity with respect to the surrounding material of the substrate 451. Moreover, an etch stop layer 455 may be formed over the substrate 451, and then over an additional material layer 456, where each negative shape of the via opening 452A may be formed. Depending on process and device requirements, negative form 452A may be composed of substantially the same material as negative form 452B or may be composed of other materials. In the example embodiment shown in FIG. 4A, the material of layer 456 and the material of negative form 542A may exhibit high etch selectivity with respect to a particular etching scheme. For example, layer 456 may be comprised of polysilicon or the like, while negative form 452A may be comprised of silicon dioxide, silicon nitride, or the like.

An exemplary process flow for forming the imprint mold 450 as shown in FIG. 4A may include the following process. First, the substrate 451 may be patterned to accommodate each trench, which may be performed based on photolithography and respective etching techniques to provide each resist mask, and based on the resist mask Is patterned. In another exemplary embodiment, each material layer comprising deformable material may be patterned based on a respective imprint mold, and subsequently, the patterned mask layer transfers each trench to the substrate 451. It can be used as an etching mask for For example, each etching technique for silicon or any other suitable material is well established in the prior art. The trench formed in the substrate 451 may then be filled with a suitable material, such as silicon dioxide, based on well established deposition techniques such as high density plasma CVD, sub-atmospheric CVD (SACVD), and the like. The surface morphology can then be planarized by CMP, and an etch stop layer 455 composed of silicon nitride, for example, can be deposited based on well established process technology. For example, layer 456 may be deposited by low pressure CVD when provided in the form of a polysilicon material. Subsequently, layer 456 may be patterned to receive respective openings corresponding to negative shape 452A, which may be performed based on photolithography and anisotropic etching processes or based on imprint process techniques. And a corresponding deformable material layer may be formed over layer 456, which may be patterned by each imprint technique as described above. Then, based on the corresponding resist mask or any other etch mask, layer 456 may be patterned, and each opening may be filled with a suitable material, such as silicon dioxide. As a result, the die 450 as shown in FIG. 4A may be formed based on well-established photolithography techniques, or may be formed based on imprint techniques, where the negative shapes 452B and 452A are It is manufactured in a subsequent process step.

4B schematically illustrates the imprint die 450 at a further advanced manufacturing stage. In one exemplary embodiment, a selective etching process 457 may be performed to selectively remove the material of the layer 456, while the material of the negative form 452A may be substantially maintained. For example, high selective wet chemical etching processes are well established in the art to selectively remove polysilicon relative to silicon dioxide. In other embodiments, a high selective dry etch process may be used. In another exemplary embodiment, the etching process 457 may represent a high anisotropic etching process performed based on an etch mask (not shown) that substantially covers the negative form 452A, where the negative form 452A is formed of a layer ( 456 may be formed directly. For this purpose, the imprint mold 450 can be formed to receive the negative form 452B in a similar manner as described above with reference to FIG. 4A, and subsequently the etch stop layer 455 and layer 456 May be deposited as described above. Thereafter, each etching mask, for example in the form of a resist mask formed by photolithography, or any other mask formed by, for example, an imprint technique, can be used to cover the portion 452A, which is a layer 456. ) May be formed during the etching process 457 from the material. As a result, regardless of the method selected, negative form 452A may be provided after completion of etching process 457.

4C diagrammatically illustrates imprint die 450 during another selective etching process 458 to selectively remove material of substrate 451 relative to material of negative shapes 452A and 452B. For example, high selective etching methods for removing silicon for silicon dioxide are well established in the prior art. In order to reliably control the etching process 458, a corresponding etch stop layer (not shown), which may be composed of substantially the same material as the negative forms 452A, 452B, may be provided for this. . As a result, after completion of the etching process 458, each of the negative shapes 452A, 452B is exposed and substantially corresponding trench openings and trenches for the metallization structures to be formed in other substrates based on the common imprint process. It can be represented as It should be understood that the die 450 may be prepared in any suitable manner to appropriately reduce surface roughness or adhesion with respect to any suitable deformable material, for example for subsequent imprint processes by surface modification processes. have. For example, each thin surface film can be formed based on suitable deposition techniques such as CVD, ALD, and the like. In another exemplary embodiment, each surface treatment may be performed, for example by nitriding or the like, to provide the desired surface properties. It should also be understood that, depending on the process description, the specific configuration of each negative form, i. E. Size and shape, may be adjusted based on the preceding process description. For example, if a different height is required for each negative form 452B, the corresponding portion of die 450 may be covered and the corresponding anisotropic etching process may be performed from the uncovered negative form 452B. May be performed to selectively remove. In other cases, when each etching mask is defined by an imprint technique, different sizes and shapes of each negative shape 452A, 452B may be obtained based on each imprint mold. As a result, die 450 may be used efficiently in the process technology as described above with reference to microstructure devices 100, 200, and 300, and may also be used in conjunction with other example embodiments to be described. It may be. In another exemplary embodiment, the imprint mold 450 may itself be formed as a metallized structure, which may be formed on each microstructured device, such as devices 100, 200, and 300, as described above. Imprint ".

5 schematically illustrates a metallization structure 550, which in some example embodiments may be considered as an “imprint mold or die” that is imprinted, ie, mechanically connected to each microstructure device 500. Microstructure device 500 may represent a semiconductor device including a plurality of circuit elements 510 connected to each of contact portions 511. Metallization structure 550 may also be formed based on a process technique as described above with reference to respective metallization layers 107, 207 and 307, or as described with reference to imprint die 450. It may comprise one or more metallization layers, which may be formed according to the same process flow, wherein each negative form may be formed based on a suitable metal material. In one exemplary embodiment, the metallization structure 550 is based on each imprint process for commonly patterning each metal line 552B with each via 552A, as described above. And a plurality of respective process sequences can be repeated, if necessary, to provide a plurality of metallization layers. The metallization structure 550 may be aligned with respect to the device 500 based on the alignment procedure as described above. Moreover, in some exemplary embodiments, the "deformable" layer 503 may be provided, for example in the form of a thin layer of a suitable electrolyte solution, from which the layer 503 of the metallization structure 550 Upon contacting, selective material deposition may be initiated to provide electrical and mechanical contact with contact portion 511. The excess material of layer 503 can then be removed and replaced with a suitable dielectric material, which can be applied in a high viscosity state.

As a result, the metallization structure 550 can be formed based on a high efficiency imprint technique, as described above, wherein the process for forming the metallization structure of each semiconductor device and the fabrication for forming circuit elements. The degree of separation of the sequences can be increased. In this way, the overall fabrication time for the completed device including the metallization structure 550 and the semiconductor device 500 can be greatly reduced, and further the process flexibility and yield can be improved because the metallization structure This is because any failure at or at the device level results in no loss of the complete semiconductor device.

6A-6C, yet another exemplary embodiment is now described, where a properly designed imprint mold or die is provided to provide the proper shape of each circuit feature, particularly the sidewall portion.

6A schematically depicts an imprint mold 650 comprising a substrate 651 and a plurality of negative shapes 652 of each circuit feature, which, in one exemplary embodiment, provides for via openings. A negative form 652A and a negative form 652B for the trench for the conductive lines of the metallized structure can be shown. In other example embodiments, as described in more detail below, each negative shape 652 may represent another circuit element, such as a isolation trench, a gate electrode, or the like. With regard to the material component of the substrate 651 and the negative form 652, the same criteria may be applied as described above with reference to the imprint molds 150, 250, 350, 450. In the illustrated embodiment, at least the upper portion of each sidewall 652S of negative shapes 652A, 652B may include a non-vertical orientation with respect to the lower portion 652D, and in one exemplary embodiment, Each sidewall portion 652S may define a tapered shape that provides increasing width or diameter at each top portion of the via opening and trench, which can efficiently improve fill operation during each deposition technique. .

6B schematically illustrates the imprint mold 650, on which a negative form 652A is formed for each via opening, which may be advantageous when the patterning process is performed separately for the via opening and trench. . It should be understood that sidewall 652S of negative form 652A does not necessarily have continuous tapering along its entire depth, but may have different sidewall angles depending on device and process requirements. For example, a significant slope of the sidewall portion 652S may be provided only in the upper portion, while the lower portion may have a substantially perpendicular orientation with respect to the lower portion 652D. However, depending on the device requirements, any other sidewall configuration may be provided.

6C schematically illustrates an imprint mold 650 comprising a negative shape 652B for each trench, in which case the appropriate size, in this example each tapering of sidewall portion 652S, is provided according to device requirements. Can be.

As a result, when using the imprint mold 650 to form each opening, the filling operation in the subsequent deposition of the barrier material and / or bulk material can be greatly enhanced, whereby the reliability of each metallization structure Can be increased because, for example, the deposition of the barrier material can be performed more reliably, thereby greatly enhancing the resistance to electrical movement, and improving the electrical and mechanical properties. For example, the imprint mold 650 shown in FIG. 6A can be advantageously used with the process technique described above, where each via opening and trench is formed in a common imprint process. On the other hand, the imprint mold 650 as shown in FIGS. 6B and 6C can be advantageously used in each process sequence, where each via opening and trench is patterned in a separate process step.

With reference to FIGS. 7A and 7B and FIGS. 8A-8D, yet another exemplary embodiment is now described, wherein each imprint mold with non-vertical sidewall portions differs from the metallization structure for a sophisticated integrated circuit. Can be used to pattern.

7A schematically illustrates a cross-sectional view of a semiconductor device 700 including a substrate 701, where the substrate 701 may represent any suitable substrate, on which a semiconductor device, such as a transistor, a capacitor, or the like. A layer of material is formed to form. For example, the substrate 701 may represent a carrier material, on which a silicon based semiconductor layer is formed to form each circuit element. In this regard, a silicon based semiconductor layer should be understood as a substantially crystalline semiconductor layer comprising a significant amount of silicon, for example approximately 50 atomic percent or more silicon. Moreover, a mask layer 703 may be formed over the substrate 701, and each opening 704A may be formed in the mask layer 703, and each opening 704A may be an opening 704A. A sidewall 704S having a non-vertical orientation at least partially with respect to the bottom 704D of. In one exemplary embodiment, opening 704B may represent a trench used to form a corresponding trench in substrate 701, which may be a sophisticated semiconductor to define a corresponding active region in substrate 701. It can act as a separate trench for the device.

As shown in FIG. 7A, a typical process flow for forming device 700 may include the following process. After providing the substrate 701, the layer 703 may be formed by any suitable deposition technique, where the material of the layer 703 is a deformable material, ie, the layer 703 may be, for example, illustrated in FIG. It may be in a highly deformable or low viscosity state upon contact with a corresponding imprint mold (not shown), which may have any suitable shape as described with reference to 6c. Thus, with each imprint mold having each designed sidewall portion, as a result, a corresponding opening 704B having a desired non-vertical shape, for example, a tapered shape configuration as shown in FIG. 7A can be formed. have. Thereafter, as described above, the imprint mold can be removed, and the material of layer 703 is in a high undeformable state. Thereafter, the device 700 may be placed in a corresponding etching process 705, during which the material of the layer 703 and the material of the exposed portion of the substrate 701 may be removed, so that As a result, the opening 704B can be increasingly transferred to the substrate 701.

7B schematically illustrates a semiconductor device 700 after completion of the etching process 705, where each opening 706B is formed in the substrate 701, where the required tapering, i.e., each sidewall portion ( The non-vertical configuration of 706S is obtained based on the molded openings 704B, respectively. Thus, by providing each imprint mold with the required size and shape, each configuration of the opening 706B can be designed with high flexibility without requiring specially modified etching techniques or the like.

8A schematically illustrates a semiconductor device 800 including a substrate 801, on which a layer of material 807 is formed, which, in one exemplary embodiment, may be compatible with subsequent process steps. Any suitable material such as silicon dioxide, and the like. Furthermore, a mask layer 803 can be formed on layer 807, with a corresponding opening 804B formed in the mask layer 803, and the opening 804B being in the lower portion 804D of the opening 804B. Has a particular shape including sidewall portion 804S that is non-vertical in relation. In the embodiment illustrated in FIG. 8A, opening 804B may have an increased diameter in the upper portion, while exhibiting a substantially constant width in the lower portion. For example, opening 804B may represent a gate electrode to be formed over substrate 801.

A typical process flow for forming a semiconductor device 800 as shown in FIG. 8A may include a process similar to that described above, where it is to be formed based on isolation trenches as shown in FIGS. 7A and 7B. After formation of any separation structure that may be, a layer of material 807 may be formed based on well established deposition techniques. Thereafter, a layer 803 of deformable material may be formed based on the appropriate technique, and then the opening 804B may be formed based on a suitably designed imprint mold such that the opening 804B shape is required as required. Can be configured. In this example, a substantially constant lower portion of substantially constant width may be provided to obtain a well defined gate length, and the upper portion may provide enhanced conductivity of each gate electrode. After forming the openings 804B by correspondingly curing the layer 803 and removing each imprint mold, the device 800 can be placed in each anisotropic etching process 805 so that the material of the layer 803 And material of the exposed portion of layer 807 may be commonly removed, thereby openings 804B may be increasingly transferred to layer 807.

8B schematically illustrates the device 800 after completion of the etching process 805, thereby creating a corresponding opening 807B.

8C schematically illustrates the device 800 in a further manufacturing stage. Here, a gate insulating layer 812 is formed below the opening 807B, where the gate insulating layer 812 can have any suitable configuration in terms of material composition and thickness, which material component and thickness can be formed It is required by each transistor device to be. Moreover, a layer of gate electrode material 813, such as polysilicon, for example, may be formed to reliably fill the opening 807B. For this purpose, suitable deposition techniques such as low pressure CVD can be used. Thereafter, excess material in layer 813 may be removed by CMP.

8D schematically illustrates the device 800 at a further stage of manufacture. Here, layer 807 is removed so that gate electrode 813A having an upper portion having a width 813U and a lower portion having a width 813L is retained, thereby increasing the conductivity of gate electrode 813A and On the other hand, the required gate length, which is substantially defined by the width 813L, can be maintained. Gate electrode 813A may be formed based on a high selective etching process, where a well established isotropic etching technique may be used. For example, if the gate insulating layer 812 can be composed of silicon nitride, a well established isotropic etching method can be used to remove the material of the layer 813 if provided in the form of silicon dioxide. And may optionally be used to remove even the gate electrode 813A and the gate insulating layer 812. In other cases, when the gate insulation layer 812 is formed based on silicon dioxide, an appropriate material may be selected for the layer 807, for example silicon nitride, or any other such as polymeric material. There may be a suitable material, which may only have the ability to enable reliable deposition of the gate electrode material 813.

As a result, what is disclosed herein provides an improved technique for patterning microstructured features, and in some exemplary embodiments, patterning features of metallized structures, such as vias and metal lines, based on imprint techniques. An improved technique is provided wherein at least some complex alignment procedures can be avoided by commonly imprinting the via openings and trenches, which can greatly reduce process complexity. For this purpose, a suitably constructed imprint mold including vias and line structures can be used. As another embodiment, the shape, in particular the sidewall configuration of each circuit feature, may be suitably modified based on the respective designed imprint mold, thereby forming circuit elements such as vias, metal lines, isolation trenches, gate electrodes, and the like. High flexibility can be provided, in addition to the overall size, the sidewall configuration can be suitably modified to include non-vertical portions to enhance the manufacturing process and / or the final performance of each circuit feature. Thus, in addition to reduced process complexity, improved device performance can be achieved because improved reliability and performance in electrical movement can be obtained, for example with respect to metallization structures. Moreover, the "mechanical" patterning of at least a substantial portion of the metallized structure can increase the flexibility of forming each structure, where for some exemplary embodiments, the formation of the metallized structure is at the device level. It can be completely separated from the formation, which greatly reduces the overall manufacturing time and increases the production yield.

The specific embodiments disclosed above are merely exemplary, since the invention is apparent to those skilled in the art having the benefit of the description herein and may be modified and practiced in other but equivalent ways. Because it can be. For example, the process steps described above may be performed in a different order. Moreover, any limitations other than those set forth in the claims below do not limit the details of construction or design shown herein. Accordingly, the specific embodiments described above may be changed or modified, and all such modifications are considered to be within the scope and spirit of the invention. Therefore, the protection scope of the present invention is as described in the claims below.

Claims (20)

Common imprinting the via openings and trenches in the layer of deformable material formed over the substrate, wherein the via openings and the trenches correspond to features of the metallized structure of the microstructured device; And Forming vias and conductive lines based on said via openings and said trenches. The method of claim 1, Filling the via opening and the trench with a conductive material. The method of claim 1, Patterning a layer of material located between the substrate and the layer of deformable material using the layer of deformable material having the via opening and the trench formed as a mask. The method of claim 3, Patterning the material layer comprises etching the deformable material layer and the material layer in a common anisotropic etching process. The method of claim 1, Wherein the deformable material layer comprises a dielectric material having a relative dielectric constant of approximately 3.0 or less. The method of claim 3, Wherein the deformable material layer comprises a dielectric material having a relative dielectric constant of approximately 3.0 or less. The method of claim 2, Removing at least a portion of the deformable material layer after filling the via opening and the trench with a conductive material. The method of claim 7, wherein Forming a conductive barrier layer on the via and the exposed surface of the conductive line. The method of claim 1, Removing residue of the layer of deformable material from the bottom of the via opening prior to forming the via and the conductive line. The method of claim 1, Forming an imprint mold representing a negative image of the via and the conductive line, and commonly imprinting the via opening and the trench in a plurality of layers of deformable material provided over a plurality of substrates; Characterized in that the method. The method of claim 10, Forming the imprint mold comprises performing a lithography process and an etching process to pattern a mold substrate to receive the via opening and the negative image of the trench. The method of claim 10, And the imprint mold is formed by an imprint process. Imprinting the opening in a layer of deformable material formed over the substrate, wherein the opening corresponds to a feature of the microstructured device and has sidewall portions that are non-vertical in orientation with respect to the bottom of the opening; And Forming the feature based on the opening, wherein the feature has a sidewall portion that is non-perpendicular to the bottom of the feature. The method of claim 13, Imprinting the opening includes using an imprint mold that exhibits a negative shape, the negative shape comprising a sidewall portion that is non-perpendicular to the bottom of the negative shape. The method of claim 13, And said opening represents at least one of a via opening and a trench for forming metal containing regions of a metallization layer of said microstructured device. The method of claim 13, Filling the opening with a conductive material to form the feature. The method of claim 13, Patterning a layer of material formed under the layer of deformable material by an anisotropic etching process using the layer of deformable material as a mask. The method of claim 17, Wherein the feature represents one of a isolation trench and a gate electrode of a semiconductor device. The method of claim 17, Wherein the feature represents at least one of a via opening and a trench for a metallization layer of a semiconductor device. Forming a metallization layer for the semiconductor device; And And mechanically transferring the metallization layer to a substrate, wherein a plurality of circuit elements are formed on the substrate.

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