KR20080070642A - 반도체 구조 및 그 형성 방법 - Google Patents

반도체 구조 및 그 형성 방법 Download PDF

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Publication number
KR20080070642A
KR20080070642A KR1020087010524A KR20087010524A KR20080070642A KR 20080070642 A KR20080070642 A KR 20080070642A KR 1020087010524 A KR1020087010524 A KR 1020087010524A KR 20087010524 A KR20087010524 A KR 20087010524A KR 20080070642 A KR20080070642 A KR 20080070642A
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South Korea
Prior art keywords
semiconductor layer
region
devices
device region
forming
Prior art date
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Ceased
Application number
KR1020087010524A
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English (en)
Korean (ko)
Inventor
분-유 디안
지안 첸
비츠-옌 구옌
마리암 지. 사다카
다 장
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20080070642A publication Critical patent/KR20080070642A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

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  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020087010524A 2005-10-31 2006-10-20 반도체 구조 및 그 형성 방법 Ceased KR20080070642A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/263,120 2005-10-31
US11/263,120 US7575975B2 (en) 2005-10-31 2005-10-31 Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer

Publications (1)

Publication Number Publication Date
KR20080070642A true KR20080070642A (ko) 2008-07-30

Family

ID=37996936

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020087010524A Ceased KR20080070642A (ko) 2005-10-31 2006-10-20 반도체 구조 및 그 형성 방법

Country Status (6)

Country Link
US (1) US7575975B2 (https=)
JP (1) JP5289968B2 (https=)
KR (1) KR20080070642A (https=)
CN (1) CN101341597A (https=)
TW (1) TW200725756A (https=)
WO (1) WO2007053339A2 (https=)

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US9543323B2 (en) 2015-01-13 2017-01-10 International Business Machines Corporation Strain release in PFET regions

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US7465972B2 (en) 2005-01-21 2008-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS device design
US7754560B2 (en) * 2006-01-10 2010-07-13 Freescale Semiconductor, Inc. Integrated circuit using FinFETs and having a static random access memory (SRAM)
US7723805B2 (en) * 2006-01-10 2010-05-25 Freescale Semiconductor, Inc. Electronic device including a fin-type transistor structure and a process for forming the electronic device
US7709303B2 (en) * 2006-01-10 2010-05-04 Freescale Semiconductor, Inc. Process for forming an electronic device including a fin-type structure
US7323392B2 (en) * 2006-03-28 2008-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistor with a highly stressed channel
JP4991254B2 (ja) 2006-11-17 2012-08-01 株式会社東芝 二重リング・ネットワークの通信制御方法及び二重リング・ネットワークの伝送局
US7612405B2 (en) * 2007-03-06 2009-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication of FinFETs with multiple fin heights
US7560785B2 (en) 2007-04-27 2009-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multiple fin heights
JP4459257B2 (ja) * 2007-06-27 2010-04-28 株式会社東芝 半導体装置
US20110084308A1 (en) * 2007-08-08 2011-04-14 Ter-Hoe Loh Semiconductor arrangement and a method for manufacturing the same
US8440517B2 (en) * 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US8236634B1 (en) * 2011-03-17 2012-08-07 International Business Machines Corporation Integration of fin-based devices and ETSOI devices
US9287385B2 (en) * 2011-09-01 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-fin device and method of making same
US8692291B2 (en) 2012-03-27 2014-04-08 International Business Machines Corporation Passive devices for FinFET integrated circuit technologies
JP5612035B2 (ja) 2012-07-31 2014-10-22 株式会社東芝 半導体装置
US8946063B2 (en) * 2012-11-30 2015-02-03 International Business Machines Corporation Semiconductor device having SSOI substrate with relaxed tensile stress
EP3087602A4 (en) * 2013-12-27 2017-08-09 Intel Corporation Bi-axial tensile strained ge channel for cmos
CN105336772B (zh) * 2014-05-26 2021-11-30 中芯国际集成电路制造(上海)有限公司 鳍式tfet及其制造方法
US9653602B1 (en) * 2016-03-21 2017-05-16 International Business Machines Corporation Tensile and compressive fins for vertical field effect transistors
CN107305865B (zh) * 2016-04-18 2020-07-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US10229856B2 (en) * 2017-05-16 2019-03-12 International Business Machines Corporation Dual channel CMOS having common gate stacks
US10699967B2 (en) 2018-06-28 2020-06-30 International Business Machines Corporation Co-integration of high carrier mobility PFET and NFET devices on the same substrate using low temperature condensation

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US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
JP2001160594A (ja) * 1999-09-20 2001-06-12 Toshiba Corp 半導体装置
US6551937B2 (en) * 2001-08-23 2003-04-22 Institute Of Microelectronics Process for device using partial SOI
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
KR100508756B1 (ko) * 2003-03-12 2005-08-17 삼성전자주식회사 반도체 장치의 트랜지스터 형성 방법
US6882025B2 (en) * 2003-04-25 2005-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel transistor and methods of manufacture
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
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US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
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US7193279B2 (en) * 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543323B2 (en) 2015-01-13 2017-01-10 International Business Machines Corporation Strain release in PFET regions
US9761610B2 (en) 2015-01-13 2017-09-12 International Business Machines Corporation Strain release in PFET regions
US9966387B2 (en) 2015-01-13 2018-05-08 International Business Machines Corporation Strain release in pFET regions

Also Published As

Publication number Publication date
CN101341597A (zh) 2009-01-07
US7575975B2 (en) 2009-08-18
WO2007053339A2 (en) 2007-05-10
WO2007053339A3 (en) 2007-11-29
JP2009514247A (ja) 2009-04-02
US20070099353A1 (en) 2007-05-03
JP5289968B2 (ja) 2013-09-11
TW200725756A (en) 2007-07-01

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