KR20080063880A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20080063880A
KR20080063880A KR1020070000402A KR20070000402A KR20080063880A KR 20080063880 A KR20080063880 A KR 20080063880A KR 1020070000402 A KR1020070000402 A KR 1020070000402A KR 20070000402 A KR20070000402 A KR 20070000402A KR 20080063880 A KR20080063880 A KR 20080063880A
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KR
South Korea
Prior art keywords
interlayer insulating
film
hard mask
layer
contact plug
Prior art date
Application number
KR1020070000402A
Other languages
Korean (ko)
Inventor
이성권
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070000402A priority Critical patent/KR20080063880A/en
Publication of KR20080063880A publication Critical patent/KR20080063880A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to prevent the open defect of a contact hole for forming a contact plug by recessing a part of an interlayer dielectric for forming the contact plug. Plural patterns on which a conductive layer and a dielectric are laminated are formed on a substrate. An etch barrier layer(40) is formed on the substrate along a step thereof. A first interlayer dielectric(50) is formed on the etch barrier layer so that a part between the patterns is gap-filled. A hard mask pattern is formed on the first interlayer dielectric to expose a part region between the patterns. The first interlayer dielectric and a part of the etch barrier layer are etched by using the hard mask pattern as an etch mask to form a first contact hole. A part of the substrate is exposed through the first contact hole. A conductive layer is gap-filled in the first contact hole to form a contact plug(70). A constant thickness of the dielectric is etched to protrude the contact plug.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10: substrate 20: gate pattern

30 junction region 40 etching layer

50, 80: interlayer insulation film 60: hard mask film pattern

61, 81: contact hole 70: contact plug

90 mask pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device to which a Self Aligned Contact (hereinafter referred to as SAC) process is applied.

In general, in the case of a semiconductor device, a contact hole exposing a part of a lower metal or a junction region is formed, and a contact hole is formed by filling it with a conductive material to form a conductive contact plug. Electrically connect the conductive interlayers.

In recent years, due to the integration of semiconductor devices, design rules are rapidly decreasing, resulting in a lack of dose, focus and alignment margin in the photolithography process, and an etching selection in the etching process. Due to the limitation of the ratio, it is increasingly difficult to form a fine pattern, that is, a fine contact hole. Self Align Contact (SAC) etching, which uses the difference in the etching selectivity between the films to obtain the etch profile to automatically align the contact holes using the underlying pattern structure to solve this problem. The process is universally applied.

The self-aligned contact etching process mainly uses an etching selectivity difference between the hard mask layer or the etch stop layer and the insulating layers below, and forms the hard mask layer or etch stop layer on the entire surface of the substrate on which the predetermined lower pattern structure is formed. An insulating film, a hard mask film, or an etch stop film is formed thereon. Subsequently, the hard mask film or the etch stop film on the insulating film is etched and etched using the hard mask film or the etch stop film as a mask to remove the insulating film in the region between the lower patterns to form a contact hole. However, the gap between the pattern and the pattern becomes narrower due to the increase in the degree of integration, and the phenomenon that the insulating film in the contact hole forming region is not completely removed due to the increase in the aspect ratio of the contact hole occurs. As such, the contact hole region is not completely opened, and thus, the electrical connection between the lower metal or the junction region and the upper conductive layer is not smoothly performed, which causes a problem that the device does not operate.

Therefore, the present invention has been proposed to solve the above problems of the prior art, by making a contact plug of the protruding form through the SAC process to reduce the etch target of the fine contact hole produced through the subsequent process to reduce the fine contact hole An object of the present invention is to provide a method for manufacturing a semiconductor device that can be effectively formed.

According to an aspect of the present invention, there is provided a method of forming an etch barrier layer along a step on a substrate on which a plurality of patterns on which a conductive layer and an insulating layer are stacked are formed, and a portion between the plurality of patterns is partially formed. Forming a first interlayer insulating film on the etch barrier layer to be buried, forming a hard mask pattern exposing a portion of the region between the patterns on the first interlayer insulating film, and using the hard mask pattern as an etch mask Etching the first interlayer insulating layer and a portion of the etch barrier layer to form a first contact hole exposing a portion of the substrate, and filling the inside of the first contact hole with a conductive layer to form a contact plug. And etching the insulating film to a predetermined thickness to protrude the contact plug.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same elements.

Example

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in FIG. 1A, a gate pattern 20 and a junction region 30 are formed on a semiconductor substrate 10.

Although not shown on the semiconductor substrate 10, a device isolation film defining an active region and an inactive region is formed. Thereafter, the gate insulating film 21, the conductive film for the gate electrode 22, and the gate hard mask film 23 are formed over the entire structure. The gate hard mask film 23, the conductive film for the gate electrode 22, and the gate insulating film 21 are etched through an etching process to include the gate insulating film 21, the gate electrode 22, and the gate hard mask film 23. A gate pattern 20 is formed. It is preferable to use a multilayer film having a tungsten silicide layer (or a tungsten / tungsten silicide layer) formed on the polysilicon film as the gate electrode 22. Impurity ions are implanted into the semiconductor substrate 10 on both sides of the gate pattern 20 to form the junction region 30 (source / drain). Although not shown, a gate spacer including an oxide film and an oxide film / nitride film may be formed on both sides of the gate pattern 20.

Subsequently, the etch barrier layer 40 is formed along the step on the entire structure including the gate pattern 20. In this case, the etching barrier layer 40 is preferably formed of a nitride film-based insulating film that can maximize the etching selectivity with the oxide film used as a subsequent interlayer insulating film. That is, at least one selected from the group consisting of a nitride film-based SiBN film, a SiCN film, a SiC film, and a SiBCN film is used.

Subsequently, as illustrated in FIG. 1B, a first interlayer dielectric layer 50 is deposited to cover the entire structure including the etch barrier layer 40. A portion of the first interlayer insulating layer 50 is etched to the upper side surface region of the gate hard mask layer 23 to recess a portion of the first interlayer insulating layer 50. Therefore, the space between the gate patterns 20 may not be completely filled with the first interlayer insulating film 50. As a result, the height of the first interlayer insulating layer 50 between the gate patterns 20 that are etched during SAC etching may be reduced. At this time, it is preferable that the first interlayer insulating film 50 to be recessed is 100 to 500 kV. That is, the first interlayer insulating film 50 is recessed within the above range on the basis of the upper surface of the gate hard mask film 23. If it is smaller than the above range, the height of the first interlayer insulating film 50 removed during self-alignment etching becomes high, and if it is larger than the above range, the first interlayer insulating film 50 does not act as a barrier and the gate electrode pattern ( 2) the inflow of the hard mask film produced during the subsequent process increases, so that the etching thereof is difficult.

The first interlayer insulating film 50 may be formed of an oxide-based material, for example, boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), un-doped silicate glass (USG), or tetra ethole ortho silicate (TEOS). ), At least one selected from the group consisting of SOG (Spin On Glass) and SOD (Spin On Dielectric).

Of course, the first interlayer insulating film 50 may be formed to a thickness sufficient to fill the space between the gate patterns 20, and then the planarization process may be further performed using chemical mechanical polishing (CMP).

Subsequently, as shown in FIG. 1C, hard to compensate an etch magin due to the lack of thickness of the photoresist mask pattern (not shown) to be formed on the first interlayer insulating layer 50 through a subsequent process. A hard mask is deposited and the hard mask layer is etched to form a hard mask layer pattern 60.

The hard mask layer is preferably formed through a spin coating method. As a result, a portion of the first interlayer insulating layer 50 may completely fill the space between the recessed gate patterns 20, and may planarize the upper surface. A photoresist film is coated on the hard mask layer and etched through a photolithography process to form a photoresist mask pattern. In this case, a BARC (Bottom Anti-Reflective Coating) film may be further applied as an anti-reflection film (not shown) before application of the photoresist film. Here, it is preferable to use ArF or F2 as an exposure source in the photolithography process. The hard mask layer pattern 60 is removed by etching the photoresist mask pattern as an etch mask to form a hard mask layer pattern 60. It is preferable to remove the photoresist mask pattern remaining after the hard mask layer pattern 60 is formed. Of course, the subsequent process may be performed without removing the photoresist mask pattern.

As the hard mask layer pattern 60, a material layer having a large etching selectivity with respect to the first interlayer insulating layer 50 and the etching barrier layer 40 is preferably used. In this embodiment, at least one selected from the group consisting of an organic polymer film, an inorganic polymer film, a nitride film, a polysilicon film, an amorphous carbon layer, or a metal film is used.

Subsequently, as illustrated in FIG. 1D, the first interlayer insulating layer 50 between the gate patterns 20 is removed through an etching process using the hard mask pattern 60 as an etching mask, and the upper portion of the junction region 30 is formed. A portion of the etch barrier layer 40 provided on the surface is removed to form the first contact hole 61.

The etching of the first interlayer insulating film 50 is a self-aligned etching, except for the first interlayer insulating film 50 and the first interlayer insulating film 50 (hard mask film pattern 60, gate hard mask film 23). ) And the etching selectivity between the etching barrier layer 40 is performed. As a result, an alignment error occurs in the hard mask layer pattern 60, or due to the high integration of the device, an opening pattern of the hard mask layer pattern 60 may not be manufactured finely, thereby exposing a part of the upper portion of the gate pattern 20. Even if only the first interlayer insulating film 50 between the gate pattern 20 is selectively removed, a sufficient process margin can be secured, and process defects and thus device pattern defects can be prevented. As described above, the first interlayer insulating layer 50 may be formed and then a portion thereof may be recessed to reduce the height of the first interlayer insulating layer 50 etched during the self-aligned etching.

As a result, when the first interlayer insulating layer 50 for forming the contact hole 61 is etched, the first interlayer insulating layer 50 in the lower region between the gate patterns 20 is not completely removed, and thus the contact hole 61 is not completely opened. It can prevent the phenomenon. In addition, even when the interval between the gate pattern 20 and the pattern becomes minute, the contact hole 61 opening at least a part of the region therebetween can be formed.

In the above-described self-aligned etching, a dry etching process using C 4 F 6 / Ar gas is preferably performed to etch only the oxide film used as the first interlayer insulating film 50.

Subsequently, the entire surface is etched using the hard mask layer pattern 60 as an etch mask to remove a portion of the etch barrier layer 40 on the junction region 30 between the gate patterns 20. The contact hole 61 exposing a part of the junction region 30 between the () is formed. In this case, a portion of the etching barrier layer 40 provided on the gate pattern 20 may also be etched as shown in the drawing. As a result, the etch barrier layer 40 remains on the side of the gate pattern 20 in the form of a spacer.

Subsequently, as shown in FIG. 1E, a conductive film is formed to fill the contact hole 61, and a contact plug 70 is formed by removing the conductive film on the hard mask layer pattern 60 through an etching process. In this case, after the conductive film is formed, the conductive film on the hard mask film pattern 60 is removed through a chemical mechanical polishing (CMP) process or an etch back process.

After forming the contact plug 70, a portion of the hard mask layer pattern 60, the first interlayer insulating layer 50, the etch barrier layer 40, and the gate hard mask layer 23 are etched. A part of the plug 70 protrudes. As described above, the hard mask layer pattern 60, the first interlayer insulating layer 50, and the gate hard mask layer 23 on the side of the contact plug 70 are recessed through an etching process using an etch back process to contact the contact plug 70. Expose Through this, the etching target may be reduced when forming the subsequent fine contact hole. In this case, it is preferable that 20% to 80% of the total height of the gate hard mask layer 23 is removed during etching for protruding the contact plug 40. If it is smaller than the above range, the height of the protruding contact plug 70 may not be high, and the contact plug 70 may not open when the contact is formed in a subsequent process. If it is larger than the above range, the height of the gate hard mask layer 23 remaining on the gate electrode 22 is lowered, which may cause the gate hard mask layer 23 to not act as a barrier.

Subsequently, as illustrated in FIGS. 1F and 1G, a second interlayer insulating layer 80 is formed on the substrate 10 provided with the protruding contact plug 70. Subsequently, a mask pattern 90 is formed on the second interlayer insulating layer 80 to expose an upper surface of the contact plug 70, and the contact plug 70 is formed through an etching process using the mask pattern 90. A second contact hole 81 exposing the contact plug 70 is formed by removing the upper second interlayer insulating layer 80. Since the contact plug 70 protrudes, the height of the etching target of the second interlayer insulating layer 80 that is etched during the etching for forming the second contact hole 81 may be reduced. That is, since the contact plug 70 protrudes as shown in FIG. 1F, the thickness T1 of the second interlayer insulating film 80 between the upper surface of the second interlayer insulating film 80 and the top surface of the contact plug 70. ) Is thinner than the thickness T2 of the second interlayer insulating film 80 between the top surface of the gate hard mask film pattern 23 on the top surface of the second interlayer insulating film 80. As a result, when the contact plug 70 does not protrude as in the conventional art, the second contact hole 81 is formed by removing the second interlayer insulating film 80 having the thickness T2. However, since the contact plug 70 protrudes as in the present embodiment, the second contact hole 81 can be formed even by removing the second interlayer insulating film 80 only by the thickness of T1.

Up to now, the present invention has been described with respect to the process of forming a landing plug contact of a DRAM device using the SAC process, but the present invention is not limited thereto, and all semiconductor devices electrically connecting upper and lower conductive films by forming fine contact holes. It can be applied to the manufacturing process.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a part of the interlayer insulating film for forming the contact plug can be recessed to prevent the defective opening of the contact hole for forming the contact plug, and the contact for exposing the contact plug to expose the contact plug. The etching target of the hole can be reduced, and the height of the entire device can be reduced.

Claims (7)

Forming an etch barrier layer along a step on the substrate on which the plurality of patterns on which the conductive layer and the insulating layer are stacked are formed; Forming a first interlayer insulating layer on the etch barrier layer to partially fill the gaps between the plurality of patterns; Forming a hard mask pattern on the first interlayer insulating layer to expose a portion of the region between the patterns; Etching the first interlayer insulating layer and a portion of the etch barrier layer using the hard mask pattern as an etch mask to form a first contact hole through which a portion of the substrate is exposed; Filling the inside of the first contact hole with a conductive film to form a contact plug; And Etching the insulating layer to a predetermined thickness to protrude the contact plug; Method for manufacturing a semiconductor device comprising a. The method of claim 1, After protruding the contact plug, Forming a second interlayer insulating film on the substrate on which the contact plug is formed; And Etching a portion of the second interlayer insulating layer to form a second contact hole through which a portion of the contact plug is exposed; Method of manufacturing a semiconductor device further comprising. The method of claim 1, Filling a portion of the region between the plurality of patterns with the first interlayer insulating film, Forming the first interlayer insulating layer to fill the region between the patterns; And Recessing a portion of the first interlayer insulating layer above the inter-pattern region Method for manufacturing a semiconductor device comprising a. The method of claim 3, wherein Recessing the portion of the first interlayer insulating film, the method of manufacturing a semiconductor device so that the first interlayer insulating film is recessed to a thickness of 100 ~ 500Å relative to the pattern upper surface. The method of claim 1, And the hard mask pattern is formed of at least one film selected from the group consisting of an organic polymer, an inorganic polymer, and a metal film. The method of claim 1, The projecting of the contact plug may include removing 20% to 80% of the entire thickness of the insulating layer. The method of claim 1, The conductive layer is a gate electrode, and the insulating film is a gate hard mask manufacturing method.
KR1020070000402A 2007-01-03 2007-01-03 Method for manufacturing semiconductor device KR20080063880A (en)

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KR1020070000402A KR20080063880A (en) 2007-01-03 2007-01-03 Method for manufacturing semiconductor device

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