KR20080060370A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to open a contact hole having a high aspect ratio by using unlimited etch selectivity between oxide layers. An etch barrier layer(40) is formed along a stepped part on a substrate(10) including a conductive pattern. An organic layer(50) is formed to bury a gap between the conductive patterns. An oxide layer-based hard mask pattern(62) is formed to open a partial region between the conductive patterns. A contact hole(70) for exposing a part of the substrate between the conductive patterns is formed by removing partially the organic layer and the etch barrier layer by using the oxide layer-based hard mask pattern. A landing pad is formed by burying the inside of the contact hole with the conductive layer.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10: substrate 20: gate pattern

30 junction region 40 etching layer

50: organic film 60: hard mask film

62: hard mask film pattern 70: contact hole

80 landing pad 90 interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device to which a Self Aligned Contact (hereinafter referred to as SAC) process is applied.

In general, in the case of a semiconductor device, a contact hole exposing a part of a lower metal or a junction region is formed, and a contact hole is formed by filling it with a conductive material to form a conductive contact plug. A landing pad is formed to electrically connect the conductive interlayers.

In recent years, due to the integration of semiconductor devices, design rules have been rapidly reduced, resulting in a lack of dose, focus, and alignment margin in the photolithography process, and etching. Due to the limitation of the etching selectivity of the process, it is increasingly difficult to form fine patterns, that is, fine contact holes. In order to solve such a problem, a SAC etching process using a difference in etching selectivity between layers and obtaining an etch profile to automatically align contact holes using a lower pattern structure is commonly applied. The SAC etching process uses a difference in etching selectivity between the silicon nitride film used as the hard mask and the silicon oxide film used as the lower interlayer insulating film.

However, in general, the etching selectivity between the nitride film and the oxide film has a problem that it is difficult to obtain more than tens of days. Therefore, the conventional nitride film hard mask may not function as a sufficient etching barrier layer when the oxide layer for forming the contact hole is etched so that the oxide layer in the contact hole forming region may not be completely removed or used as an etching barrier layer under the contact hole region. The formed nitride film is not completely removed. This causes a problem that the contact hole is not fully opened. In addition, as the integration of devices increases, the distance between adjacent conductive layers becomes very small, and a nitride film is buried in an area between the conductive layers so that the nitride film inside the contact hole may not be completely removed after the subsequent oxide film is removed. As such, the contact hole region is not completely opened, and thus, the electrical connection between the lower metal or the junction region and the upper conductive layer is not smoothly performed, which causes a problem that the device does not operate.

Therefore, the present invention has been proposed to solve the problems of the prior art, a method of manufacturing a semiconductor device that can solve the problem that the contact hole is not fully opened by using the infinite etch selectivity between the organic material and the oxide film. The purpose is to provide.

According to an aspect of the present invention, there is provided a method of forming an etching barrier layer on a substrate on which a conductive pattern is formed, and forming an organic layer to fill the gap between the conductive patterns. Forming a hard mask pattern based on an oxide layer to open a partial region between the conductive patterns, and removing a portion of the organic layer and the etch barrier layer using the hard mask layer pattern to partially form the substrate between the conductive patterns Forming a contact hole exposing the contact hole and filling the inside of the contact hole with a conductive film to form a landing pad.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same elements.

Example

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, as shown in FIG. 1A, a gate pattern 20 and a junction region 30 are formed on a semiconductor substrate 10.

For example, the gate pattern 20 and the junction region 30 are formed in the following manner.

Although not illustrated in the semiconductor substrate 10, a device isolation film is formed by performing a shallow trench isolation (STI) process. Thereafter, the gate insulating film 21, the conductive film for the gate electrode 22, and the gate hard mask 23 are formed on the entire structure. Thereafter, the gate hard mask 23, the conductive film for the gate electrode 22, and the gate insulating film 21 are etched through an etching process to include the gate insulating film 21, the gate electrode 22, and the gate hard mask 23. A gate pattern 20 is formed. At this time, the gate electrode 22 preferably uses a multilayer film having a tungsten silicide layer (or a tungsten / tungsten silicide layer) formed on the polysilicon film. Thereafter, impurity ion implantation is performed in the semiconductor substrate 10 on both sides of the gate pattern 20 to form the junction region 30 (source and drain regions). Although not shown, a gate spacer formed of an oxide film, a nitride film, or a stacked structure in which these layers are stacked is formed on both sidewalls of the gate pattern 20.

Subsequently, the etch barrier layer 40 for SAC is formed along the stepped portion of the substrate 10 including the gate pattern 20. In this case, the etch barrier layer 40 is formed of a material that can prevent the buried due to the etch barrier layer 40 in the region where the contact hole is to be formed between the gate pattern, the gate pattern using an insulating film having a low dielectric film characteristics The thickness of the etching barrier layer 40 remaining on the side surface 20 may be reduced. At least one selected from the group consisting of a SiBN film, a SiCN film, a SiC film, and a SiBCN film is used as the etching barrier layer 40. In addition, the etching barrier layer 40 is formed to a thickness of 20 to 150Å. Here, the etch barrier layer 40 may be positioned on both sidewalls of the gate pattern 20 to act as the spacer described above. Thus, the gate spacer may be replaced with the etch barrier layer 40.

Subsequently, as shown in FIG. 1B, the empty space between the gate patterns 20 is filled with the organic layer 50. That is, the organic layer 50 is formed to cover the upper portion of the substrate 10 including the etch barrier layer 40. In this case, as the organic layer 50, an organic material layer having an etch selectivity with an oxide layer used as the hard mask pattern 62 manufactured through a subsequent process may be infinite. For example, the organic film 50 is formed of an amorphous carbon film or SilK (product name).

Subsequently, an entire surface is etched, that is, a planarization process is performed to remove the organic layer 50 on the gate pattern 20. In this case, it is preferable to use an etch back process or a chemical mechanical polishing (CMP) process for the front surface etching. By lowering the height of the organic layer 50 through the entire surface etching, the thickness of the organic layer 50 removed in a subsequent process may be reduced.

Subsequently, as illustrated in FIG. 1C, an etch margin due to lack of thickness of the photoresist mask pattern 61 to be formed through a subsequent process is formed on the substrate 10 on which the organic layer 50 is formed. In order to form the hard mask 60 to the oxide-based material.

Subsequently, the photoresist film is coated on the hard mask 60, and then the photoresist mask pattern 61 is formed through a photolithography process using a photo mask. At this time, a BARC (Bottom Anti-Reflective Coating) film may be further applied as an anti-reflection film (not shown) before application of the photoresist film. At this time, it is preferable to use ArF or F2 as an exposure source during the photolithography process. Here, the hard mask 60 may use various types of oxide films manufactured by thermal oxide films or CVD processes. For example, a group consisting of Boron Phosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), Un-doped Silicate Glass (USG), Tetra Ethyle Ortho Silicate (TEOS), Spin On Glass (SOG), and Spin On Dielectric (SOD) Use at least one selected from

Subsequently, as illustrated in FIG. 1D, a part of the hard mask 60 is removed by an etching process using the photoresist mask pattern 61 as an etching mask to form the hard mask pattern 62. In this case, it is preferable to use C ₄ F ₆ / Ar gas to selectively etch only the oxide film during the etching process. For convenience of explanation, the hard mask pattern will be referred to as '62'.

Subsequently, it is preferable to remove the photoresist mask pattern 61 remaining after the hard mask pattern 62 is formed. Of course, the subsequent process may be performed without removing the photoresist mask pattern 61.

Subsequently, as shown in FIG. 1E, the organic layer 50 in the region between the gate patterns 20 is removed through an etching process using the hard mask pattern 62 as an etching mask, and the junction between the gate patterns 20 is removed. The etching barrier layer 40 provided on the region 30 is removed to form a contact hole 70 exposing a portion of the junction region 30. In this case, the etching process is a SAC process, which is performed under an etching condition having a high etching selectivity between the organic layer 50 and the remaining pattern layer except for the organic layer 50, the hard mask pattern 62, and the etching barrier layer 40. It is preferable.

Meanwhile, as described above, the etch selectivity between the organic layer 50 and the hard mask pattern 62 may be infinite. Therefore, even if the thickness of the hard mask pattern 62 is reduced, it is possible to play a sufficient etching prevention role. That is, the hard mask pattern 62 is not removed at all during etching to remove the organic layer 50. In addition, the etch barrier layer 40 provided on the gate pattern 20 may also have an infinite etching selectivity with respect to the organic layer 50, so that the etch barrier layer 40 may remain without being removed during etching to remove the organic layer 50. have. As a result, the organic layer 50 between the gate patterns 20 may be completely removed, thereby preventing the contact hole 70 from being opened due to the remaining of the organic layer 50. Due to the removal of the organic layer 50, the space between the gate patterns 20 is opened to expose the etch barrier layer 40.

Subsequently, the entire surface is etched using the hard mask pattern 62 as an etch mask to remove a portion of the etch barrier layer 40 on the junction region 30 between the gate patterns 20, thereby partially removing the portion of the junction region 30. Expose In this case, as shown in the figure, a portion of the etching barrier layer 40 provided on the gate pattern 20 may also be etched. As a result, the etch barrier layer 40 remains on the side of the gate pattern 20 in the form of a spacer. As mentioned above, since the material film having the low dielectric constant is used as the etching barrier layer 40, the thickness of the etching barrier layer 40 may be reduced. As a result, when the etch barrier layer 40 is deposited, the bottom of the contact hole 70 region may be prevented from being filled by the etch barrier layer 40, thereby preventing the contact hole 70 from being opened.

Subsequently, as illustrated in FIG. 1F, a conductive film is formed to fill the contact hole 70, and the planarization film is formed to form a landing pad 80, and the organic film 50 remaining between the gate patterns 20 is removed. do. In this case, at least one selected from the group consisting of W, Ti, TiN, and WN is used as the conductive film, that is, the landing pad 80. In addition, an etch back process or a chemical mechanical polishing method may be used as a process for planarization. That is, the conductive film for the landing pad is formed and then the etch back process is performed to remove the conductive film and the hard mask pattern 62 on the gate pattern 20. Thereafter, the organic layer 50 remaining through the etching process is removed. As a result, the contact hole 70 is filled with the conductive film for the landing pad to form the landing pad 80, and an empty space is generated between the gate patterns 20.

Subsequently, as shown in FIG. 1G, an interlayer insulating film 90 is formed in the empty space between the gate patterns 20. That is, an oxide film having excellent fluidity is formed on the entire substrate 10 over the entire structure, and the inside of the empty space is filled with the oxide film. At this time, as an oxide film having excellent fluidity, an Advanced Planarization Layer (APL) film, Boron Phosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), Un-doped Silicate Glass (USG), Tetra Ethyle Ortho Silicate (TEOS), and SOG ( At least one selected from the group consisting of Spin On Glass) and SOD (Spin On Dielectric) is used.

Subsequently, the oxide layer in the upper region of the landing pad 80 is removed through the planarization process to fill the empty space between the gate patterns 20 with the interlayer insulating layer 90. In this case, the planarization process may use an etch back method or a chemical mechanical polishing method as described above.

Of course, the present embodiment is not limited to the above-described method, and the landing pad 100 may be formed through various processes. Thus far, the present invention has been described with respect to the process of forming a landing pad of a DRAM device using the SAC process. However, the present invention is not limited thereto. For example, all semiconductor devices electrically connecting upper and lower conductive layers to form fine contact holes are described. It can be applied to manufacturing process.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, an etching barrier layer having a low dielectric constant can be formed to reduce the spacer thickness of the sidewall of the gate pattern, and an infinite etching selectivity between the organic film and the oxide film used as the hard mask film can be used. The contact hole having a large aspect ratio can be opened to prevent device defects caused by the problem that the contact hole is not fully opened.

Claims (6)

Forming an etch barrier layer along the step on the substrate on which the conductive pattern is formed; Forming an organic layer to fill the conductive patterns; Forming an oxide film-based hard mask pattern to open a partial region between the conductive patterns; Forming a contact hole exposing a portion of the substrate between the conductive pattern by removing a portion of the organic layer and the etch barrier layer using the hard mask layer pattern; And Filling the inside of the contact hole with a conductive film to form a landing pad Method for manufacturing a semiconductor device comprising a. The method of claim 1, The organic film is a method of manufacturing a semiconductor device formed of an amorphous carbon film or SilK (product name). The method of claim 1, The etching barrier layer is a method of manufacturing a semiconductor device formed of at least one low dielectric film selected from the group consisting of SiBN film, SiCN film, SiC film and SiBCN film. The method of claim 1, The etching barrier layer is a manufacturing method of a semiconductor device to form a thickness of 20 to 150Å. The method of claim 1, Forming the organic film, Forming the organic layer on the substrate including the conductive pattern; And Removing the organic layer on the conductive pattern Method for manufacturing a semiconductor device comprising a. The method of claim 1, Forming the landing pad, Depositing the conductive layer to fill the contact hole; And Removing the conductive layer on the conductive pattern through a planarization process Method for manufacturing a semiconductor device comprising a.

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