KR20050006470A - Method for forming a metal line in semiconductor device - Google Patents
Method for forming a metal line in semiconductor device Download PDFInfo
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- KR20050006470A KR20050006470A KR1020030046293A KR20030046293A KR20050006470A KR 20050006470 A KR20050006470 A KR 20050006470A KR 1020030046293 A KR1020030046293 A KR 1020030046293A KR 20030046293 A KR20030046293 A KR 20030046293A KR 20050006470 A KR20050006470 A KR 20050006470A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 금속플러그와 금속배선 간의 기생 스페이서로 인해 접촉면적이 감소되는 현상을 방지하여 이 들 간의 접촉저항을 개선시킬 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, in particular to prevent the phenomenon that the contact area is reduced due to the parasitic spacer between the metal plug and the metal wiring to form a metal wiring of the semiconductor device can improve the contact resistance therebetween It is about a method.
반도체 소자 또는 전자 소자 등에 있어서는, 금속배선형성 기술로서 절연막 상에 알루미늄(Al) 또는 텅스텐(W) 등과 같은 도전체막이 증착된 후, 상기 도전체막이 통상의 포토리소그래피(photography) 공정 및 건식식각(dry etching) 공정을 통해 패터닝됨으로써 금속배선이 형성되는 기술이 확립되어 이 분야에서 널리 이용되고 있다. 특히, 최근에는 반도체 소자 중에서 고집적화와 고성능화가 요구되는 로직(logic) 소자를 중심으로 해서 RC 지연을 줄이기 위한 일환으로 알루미늄 또는 텅스텐 대신에 구리(Cu)와 같이 비저항이 낮은 금속을 배선으로 이용하는 방법이 연구되고 있다. 상기 RC에서, 'R'은 배선 저항을 나타내고, 'C'는 절연막의 유전율을 나타낸다.In a semiconductor device or an electronic device, a conductor film such as aluminum (Al) or tungsten (W) is deposited on an insulating film as a metal wiring forming technique, and then the conductor film is subjected to a conventional photolithography process and dry etching ( The technique of forming metal wiring by patterning through dry etching process has been established and widely used in this field. In particular, recently, a method of using a low-resistance metal such as copper (Cu) instead of aluminum or tungsten as wiring to reduce the RC delay centering on logic devices requiring high integration and high performance among semiconductor devices has recently been used. Is being studied. In RC, 'R' represents wiring resistance, and 'C' represents dielectric constant of the insulating film.
구리를 이용한 금속배선 형성공정에서는 알루미늄 또는 텅스텐에 비해 패터닝 공정이 어렵다. 이에 따라, 먼저 트렌치(trench)를 형성한 후 상기 트렌치가 매립되도록 금속배선을 형성하는 소위 '다마신(damascene)' 공정이 사용되고 있다. 현재 일반적으로 사용되는 공정으로는 싱글 다마신 공정(single damascene)과 듀얼 다마신 공정(Dual damascene)이 있다. 싱글 다마신 공정은 비아홀(via hole)을 형성한 후 도전재료로 상기 비아홀을 매립하고 그 상부에 배선용 트렌치를 형성한 후 다시 배선재료로 상기 트렌치를 매립하여 금속배선을 형성하는 방법이다. 듀얼 다마신 공정은 비아홀과 배선용 트렌치를 형성한 후 배선재료를 동시에 비아홀과 배선용 트렌치를 매립하여 금속배선을 형성하는 방법이다. 이 외에도 다양한 방법들이 제시되고 있다.In the metallization process using copper, the patterning process is more difficult than aluminum or tungsten. Accordingly, a so-called 'damascene' process is used in which a trench is first formed and a metal wiring is formed to fill the trench. Currently commonly used processes include the single damascene process and the dual damascene process. The single damascene process is a method of forming a via hole and then filling the via hole with a conductive material, forming a wiring trench on the upper portion thereof, and then filling the trench with a wiring material to form a metal wiring. The dual damascene process is a method for forming metal vias by forming via holes and wiring trenches and then filling the wiring material with via holes and wiring trenches at the same time. In addition, various methods are suggested.
그러나, 구리는 실리콘내의 인터스티셜 사이트(interstitial site)를 통한 확산이 매우 빠르게 이루어져 트랜지스터의 포화전류(saturation current), 문턱전압(threshold voltage) 및 누설전류(leakage current) 등 특성을 열화시키는 문제가 발생된다. 이로 인하여, 실리콘 기판과의 접촉을 위한, 즉 메탈콘택(metal contact)공정에서는 플러그(plug)로 구리 금속층이 사용될 수 없게 된다. 따라서, 메탈콘택을 위한 콘택홀(contact hole) 내에는 텅스텐 플러그(W plug)가 매립된 후, CMP(Chemical Mechanical Polishing)을 이용한 평탄화 공정이 진행된다. 이와 같이 메탈콘택을 텅스텐 플러그로 형성할 경우에는, 도 6에 도시된 바와 같이 텅스텐 플러그와 구리 금속배선 간에 기생 스페이서가 발생되고, 이로 인하여 접촉면적이 줄어드는 결과가 발생된다. 이러한 결과는 배선저항의 증가를 야기시키고, 배선의 신뢰성을 저하시키게 된다. 더욱이 배선용 트렌치의 라인-엔드-쇼트링(line-end-shorting)에 의한 영향과 30nm 이상의 노광장비의 오버레이 마진(overlay margin)을 고려한다면, 0.13㎛ 이하의 테크놀로지(technology)에서는 쉽게 발견할 수 있게 된다.However, copper has a problem of degrading characteristics such as saturation current, threshold voltage and leakage current due to the rapid diffusion through the interstitial site in silicon. Is generated. As a result, the copper metal layer cannot be used as a plug for contact with the silicon substrate, that is, in a metal contact process. Therefore, after the tungsten plug is embedded in the contact hole for the metal contact, a planarization process using the chemical mechanical polishing (CMP) is performed. As described above, when the metal contact is formed of a tungsten plug, as shown in FIG. 6, a parasitic spacer is generated between the tungsten plug and the copper metal wiring, resulting in a reduction in contact area. This result causes an increase in wiring resistance, which lowers the reliability of the wiring. Furthermore, considering the line-end-shorting effect of the wiring trenches and the overlay margin of exposure equipment above 30 nm, it is easy to find them in technologies below 0.13 μm. do.
따라서, 본 발명의 바람직한 실시예는 금속플러그와 금속배선 간의 기생 스페이서로 인해 접촉면적이 감소되는 현상을 방지하여 이 들 간의 접촉저항을 개선시키는데 그 목적이 있다.Therefore, a preferred embodiment of the present invention is to prevent the phenomenon that the contact area is reduced due to the parasitic spacer between the metal plug and the metal wiring to improve the contact resistance therebetween.
도 1 내지 도 5은 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위하여 도시한 단면도들이다.1 to 5 are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to a preferred embodiment of the present invention.
도 6은 종래기술에서 발생되는 기생 스페이서를 설명하기 위하여 도시한 TEM 사진이다.6 is a TEM photograph illustrating a parasitic spacer generated in the prior art.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
10 : 반도체 기판 12 : 게이트 산화막10 semiconductor substrate 12 gate oxide film
14 : 폴리실리콘막 16 : 게이트 전극14 polysilicon film 16 gate electrode
18 : 소오스/드레인 영역 20 : 제1 층간절연막18 source / drain region 20 first interlayer insulating film
22 : 금속 플러그 24 : 확산방지막22: metal plug 24: diffusion barrier
26 : 제2 층간절연막 28 : 베리어막26: second interlayer insulating film 28: barrier film
30 : 금속배선30: metal wiring
본 발명의 일측면에 따르면, 제1 층간절연막 내에 금속 플러그가 형성된 반도체 기판이 제공되는 단계와, 상기 금속 플러그의 양측벽의 일부가 노출되도록 상기 제1 층간절연막이 리세스(recess)되는 단계와, 전체 구조 상부에 제2 층간절연막이 증착된 후 패터닝되어 트렌치가 형성되는 단계와, 상기 트렌치가 매립되도록 금속배선이 형성되는 단계를 포함하는 금속배선 형성방법이 제공된다.According to an aspect of the invention, there is provided a semiconductor substrate having a metal plug formed in the first interlayer insulating film, the step of recessing the first interlayer insulating film to expose a portion of both side walls of the metal plug; And forming a trench by depositing a second interlayer insulating film on the entire structure, and forming a metal wiring to fill the trench.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.
도 1 내지 도 5는 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위하여 도시한 단면도들이다. 여기서, 도 1 내지 도 5에 도시된 참조부호들 중 서로 동일한 참조부호는 동일한 기능을 하는 동일한 구성요소이다.1 to 5 are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device in accordance with a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 5 are the same components having the same function.
도 1을 참조하면, 다양한 웰(well)영역과 문턱전압 이온주입영역이 포함되는 반도체 구조물층(미도시)이 형성된 반도체 기판(10)이 제공된다. 이어서, 전체 구조 상부에 게이트 산화막(12), 폴리실리콘막(14) 및 금속 실리사이드층(미도시)이 순차적으로 증착된 후 패터닝되어 게이트 전극(16)이 형성된다. 이후, 게이트 전극(16)의 양측벽에는 LDD(Lightly Doped Drain) 스페이서가 형성된다. 이어서, 소오스/드레인 이온주입공정을 실시하여 게이트 전극(16)의 양측으로 노출되는 반도체 기판(10)에는 소오스/드레인 영역(18)이 형성된다. 이로써, 게이트 전극(16) 및 소오스/드레인 영역(18)을 포함하는 트랜지스터가 형성된다.Referring to FIG. 1, a semiconductor substrate 10 having a semiconductor structure layer (not shown) including various well regions and threshold voltage ion implantation regions is provided. Subsequently, the gate oxide film 12, the polysilicon film 14, and the metal silicide layer (not shown) are sequentially deposited on the entire structure, and then patterned to form the gate electrode 16. Thereafter, lightly doped drain (LDD) spacers are formed on both sidewalls of the gate electrode 16. Subsequently, a source / drain region 18 is formed in the semiconductor substrate 10 exposed to both sides of the gate electrode 16 by performing a source / drain ion implantation process. As a result, a transistor including the gate electrode 16 and the source / drain regions 18 is formed.
도 2를 참조하면, 전체 구조 상부에는 제1 층간절연막(inter layer dielectric; 20)이 형성된다. 이때, 상기 제1 층간절연막(20)은 예컨대, BPSG(Boron Phosphorus Silicate Glass), PSG(Phosphorus Silicate Glass), PETEOS(Plasma Enhanced Tetra Ethyle Ortho Silicate), USG(Un-doped Silicate Glass) 또는 FSG(Fluorinated Silicate Glass) 등으로 형성될 수 있다. 또한, SiO 또는 SiO2에 국부적으로 불소, 수소, 붕소 또는 인 등이 결합(substitutional) 또는 삽입(interstitial)된 막으로 형성될 수 있다. 이후, 상기 제1 층간절연막(20)은 CMP 공정을 통해 평탄화된다.2, a first inter layer dielectric 20 is formed on the entire structure. In this case, the first interlayer insulating layer 20 may be formed of, for example, boron phosphorus silicate glass (BPSG), phosphorus silicalicate glass (PSG), plasma enhanced tetra-ethoxy ortho silicate (peteos), un-doped silicate glass (USG), or fluorinated glass (SGS). Silicate Glass) or the like. In addition, it may be formed of a film in which fluorine, hydrogen, boron, phosphorus or the like is locally bonded or interstitial to SiO or SiO 2 . Thereafter, the first interlayer insulating film 20 is planarized through a CMP process.
도 3을 참조하면, 전체 구조 상부에는 포토레지스트(photoresist)이 전면 코팅된 후, 포토 마스크(photomask)를 이용한 노광 및 현상공정을 순차적으로 실시하여 제1 층간절연막(20)의 일부가 노출되는 포토레지스트 패턴(photoresistpattern; 미도시)이 형성된다. 그런 다음, 상기 포토레지스트 패턴을 식각 마스크로 이용한 식각공정을 건식 또는 습식식각방식으로 실시하여 노출되는 제1 층간절연막(20)이 패터닝된다. 이로써, 게이트 전극(16) 사이로 소오스/드레인 영역(18)이 노출되는 콘택홀(contact hole; 미도시)이 형성된다. 이후, 상기 포토레지스트 패턴은 스트립 공정(strip)을 통해 제거된다.Referring to FIG. 3, after the photoresist is entirely coated on the entire structure, a photoresist in which a portion of the first interlayer insulating film 20 is exposed by sequentially performing exposure and development processes using a photomask. A resist pattern (not shown) is formed. Then, the first interlayer insulating layer 20 exposed by performing an etching process using the photoresist pattern as an etching mask by dry or wet etching is patterned. As a result, a contact hole (not shown) through which the source / drain regions 18 are exposed is formed between the gate electrodes 16. Thereafter, the photoresist pattern is removed through a strip process.
상기 콘택홀이 형성된 후 상기 콘택홀의 내부면에는 제1 베리어막(barrier;미도시)이 형성된다. 상기 제1 베리어막은 접착층(glue layer)으로서 기능과, 확산 방지층으로의 기능을 한다. 이때, 상기 제1 베리어막은 Ti, TiN, Ta 또는 TaN의 단일막, 또는 이들이 적층된 구조로 이중막으로 형성될 수 있다. 이후, 상기 콘택홀이 매립되도록 금속물질(미도시)이 증착된 후 CMP 공정 대신에, SF6/Cl2/BCl3등의 가스를 주(main) 식각가스로 하고, O2, N2, Ar 또는 He 가스 등의 첨가가스를 이용한 에치백(etchback) 공정을 금속 플러그(22)가 형성된다. 이때, 상기 금속 플러그(22)는 텅스텐(W), 알루미늄(Al) 또는 기타 금속물질로 형성될 수 있다. 바람직하게는 텅스텐으로 형성된다.After the contact hole is formed, a first barrier layer (not shown) is formed on an inner surface of the contact hole. The first barrier film functions as a glue layer and functions as a diffusion barrier layer. In this case, the first barrier layer may be formed of a single layer of Ti, TiN, Ta, or TaN, or a double layer having a stacked structure. Subsequently, after the metal material (not shown) is deposited to fill the contact hole, a gas such as SF 6 / Cl 2 / BCl 3 is used as the main etching gas instead of the CMP process, and O 2 , N 2 , The metal plug 22 is formed by an etchback process using an additive gas such as Ar or He gas. In this case, the metal plug 22 may be formed of tungsten (W), aluminum (Al) or other metal material. It is preferably formed of tungsten.
도 4를 참조하면, 도 3에서 금속 플러그(22)가 형성된 후, 상기 제1 층간절연막(20)은 BOE(Bufferd Oxide Etchant; HF/NH4F) 용액을 이용한 습식식각공정을 통해 리세스(recess; 원형안)된다. 이때, 금속 플러그(22)가 텅스텐 금속층이고, 제1 확산방지막이 Ti/TiN으로 형성되는 경우, 상기 습식식각공정시 텅스텐과 Ti/TiN에 대한 식각률은 50Å/min이하이고, 제1 층간절연막(20)에 대한 식각률은 50Å/min이상이다. 상기 습식식각공정을 통해 제1 층간절연막(20)이 리세스되는 정도는 100Å 내지 2000Å가 된다. 이로써, 금속 플러그(22)의 양측벽의 일부가 노출된다. 이때, 상기 접착층은 금속 플러그(22)의 양측벽에 잔류될 수 있다. 그런 다음, 노출되는 금속 플러그(22)는 주기율표상 라디칼(radical) 족의 원소를 포함한 식각가스, 예컨대, Cl2와 BCl3의 혼합가스, 또는 SF6등의 주(main) 식각가스와 Ar, O2, N2또는 He 등의 첨가가스를 이용하여 라운딩(rounding)처리된다. 이로써, 노출되는 금속 플러그(22)의 모서리(edge)는 라운딩된다. 또한, Ar, O2, N2또는 He 등의 첨가가스를 이용하여 스퍼터링(sputtering) 및 패싯(facet)를 형성함으로써 기생 스페이서가 형성되지 않도록 할 수도 있다. 이후, 전체 구조 상부에 대하여 세정공정이 실시될 수 있다.Referring to FIG. 4, after the metal plug 22 is formed in FIG. 3, the first interlayer insulating layer 20 is recessed through a wet etching process using a BOE (Buffered Oxide Etchant (HF / NH 4 F) solution. recess; At this time, when the metal plug 22 is a tungsten metal layer and the first diffusion barrier layer is formed of Ti / TiN, the etching rate of the tungsten and Ti / TiN is 50 Å / min or less during the wet etching process, and the first interlayer insulating film The etching rate for 20) is over 50 μs / min. The degree to which the first interlayer insulating film 20 is recessed through the wet etching process is 100 kPa to 2000 kPa. As a result, a part of both side walls of the metal plug 22 is exposed. In this case, the adhesive layer may remain on both side walls of the metal plug 22. Then, the exposed metal plug 22 is an etching gas containing an element of the radical group on the periodic table, for example, a mixed gas of Cl 2 and BCl 3 , or a main etching gas such as SF 6 and Ar, It is rounded by using additive gas such as O 2 , N 2 or He. As a result, the edge of the exposed metal plug 22 is rounded. In addition, parasitic spacers may not be formed by forming sputtering and facets using additive gases such as Ar, O 2 , N 2, or He. Thereafter, the cleaning process may be performed on the entire structure.
도 5를 참조하면, 전체 구조 상부에는 확산방지막(24)이 형성된다. 이때, 확산방지막(24)은 SiON, SiN 또는 SiC 등의 물질로 형성될 수 있다. 또한, 확산 방지막(24)은 100Å 내지 1000Å의 두께로 형성된다. 그런 다음, 상기 확산방지막(24) 상에는 제2 층간절연막(26)이 증착된다. 상기 제2 층간절연막(26)은 상기 제1 층간절연막(20)과 동일한 물질로 형성될 수 있다. 이때, 제2 층간절연막(26)은 1000Å 내지 8000Å의 두께로 증착된다. 그런 다음, 전체 구조 상부에는 포토레지스트가 전면 코팅된 후, 포토 마스크를 이용한 노광 및 현상공정을 순차적으로 실시하여 제2 층간절연막(26)의 일부가 노출되는 트렌치(trench)용 포토레지스트 패턴(미도시)이 형성된다. 그런 다음, 상기 포토레지스트 패턴을 식각 마스크로 이용한 식각공정을 건식 또는 습식방식으로 실시하여 노출되는 제2 층간절연막(26)이 패터닝된다. 이로써, 트렌치(미도시)가 형성되고, 상기 트렌치를 통해 금속 플러그(22)가 노출된다. 도 5는 일례로 오정렬이 발생되는 경우 제1 층간절연막(20)의 상부 일부가 노출되도록 도시되었다. 이후, 상기 포토레지스트 패턴은 스트립 공정(strip)을 통해 제거된다.Referring to FIG. 5, a diffusion barrier 24 is formed over the entire structure. At this time, the diffusion barrier 24 may be formed of a material such as SiON, SiN or SiC. In addition, the diffusion barrier 24 is formed to a thickness of 100 kPa to 1000 kPa. Then, a second interlayer insulating film 26 is deposited on the diffusion barrier film 24. The second interlayer insulating layer 26 may be formed of the same material as the first interlayer insulating layer 20. At this time, the second interlayer insulating film 26 is deposited to a thickness of 1000 mW to 8000 mW. Then, after the photoresist is entirely coated on the entire structure, a photoresist pattern for trenches (not shown) is exposed by sequentially performing exposure and development processes using a photomask to expose a portion of the second interlayer insulating layer 26. O) is formed. Then, the second interlayer insulating layer 26 exposed by performing an etching process using the photoresist pattern as an etching mask in a dry or wet manner is patterned. As a result, a trench (not shown) is formed, and the metal plug 22 is exposed through the trench. FIG. 5 illustrates an example in which an upper portion of the first interlayer insulating layer 20 is exposed when misalignment occurs. Thereafter, the photoresist pattern is removed through a strip process.
이어서, 상기 트렌치 내부면(즉, 내측면과 저면)에 제2 베리어막(28)이 형성된다. 예컨대, 제2 베리어막(28)은 상기 제1 베리어막과 동일한 물질로 형성될 수 있다. 예컨대, Ta, TaN, TaAlN, TaSiN, TaSi2, Ti, TiN, TiSiN, WN, Co 및 CoSi2중 어느 하나로 형성된 단층막으로 형성되거나, 이들이 적층된 이층막으로 형성될 수 있다. 이어서, 상기 트렌치가 매립되도록 금속배선(30)이 형성된다. 상기 금속배선(30)은 구리 금속층으로 형성되는 것이 바람직하다. 그러나, 이 외에도 Al, Pt(Platinum), Pd(Palladium), Ru(Rubidium), St(Strontium), Rh(Rhadium) 및 Co 중 어느 하나로 이루어진 금속층으로 형성될 수도 있다. 이때, 상기 금속배선(30)은 전기도금 방식을 이용하여 형성될 수도 있다. 상기 전기도금 방식은 구리 금속층인 경우 제2 베리어막(28)의 상에 구리 금속물질로 시드층(미도시)이 형성된 후 상기 시드층을 시드(seed)로 하여 시드층 상에 구리 금속물질이 증착됨으로써 형성된다. 이후, CMP 방식을 이용한 평탄화 공정을 실시하여 트렌치가 매립되도록 구리 금속층이 평탄화되어 금속배선(30)이 형성된다.Subsequently, a second barrier layer 28 is formed on the inner surface of the trench (ie, the inner side and the bottom). For example, the second barrier layer 28 may be formed of the same material as the first barrier layer. For example, it may be formed of a single layer film formed of any one of Ta, TaN, TaAlN, TaSiN, TaSi 2 , Ti, TiN, TiSiN, WN, Co, and CoSi 2 , or may be formed of a stacked two-layer film. Subsequently, the metal wiring 30 is formed to fill the trench. The metal wiring 30 is preferably formed of a copper metal layer. However, in addition to this, it may be formed of a metal layer made of any one of Al, Pt (Platinum), Pd (Palladium), Ru (Rubidium), St (Strontium), Rh (Rhadium) and Co. In this case, the metal wiring 30 may be formed using an electroplating method. In the electroplating method, in the case of the copper metal layer, a seed layer (not shown) is formed on the second barrier layer 28 using a copper metal material, and then the copper metal material is deposited on the seed layer using the seed layer as a seed. It is formed by depositing. Thereafter, a planarization process using a CMP method is performed to planarize the copper metal layer to fill the trench, thereby forming the metal wiring 30.
지금까지 설명한 본 발명의 바람직한 실시예에 따른 반도체 소자의 금속배선형성방법은 도 5에 도시된 바와 같이, 금속 플러그(22)와 금속배선(30) 간에 오정렬이 발생되는 경우, 이를 보상하기 위하여 금속 플러그(22)의 상부중 일부를 노출시켜 후속 금속배선(30) 형성공정을 실시함으로써 오버레이 마진을 확보할 수 있다. 이에 따라, 오정렬에 의한 금속 플러그(22)와 금속배선(30) 간에 발생되는 기생 스페이서를 방지하여 이 들(22 및 30) 간의 접촉면적이 감소되는 것을 방지할 수 있다.As described above, in the method of forming a metal wiring of a semiconductor device according to the preferred embodiment of the present invention, when misalignment occurs between the metal plug 22 and the metal wiring 30, the metal wiring is compensated for. An overlay margin can be secured by exposing a portion of the upper portion of the plug 22 to a subsequent metallization 30 forming process. Accordingly, parasitic spacers generated between the metal plug 22 and the metal wiring 30 due to misalignment can be prevented, thereby preventing the contact area between these 22 and 30 from being reduced.
상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같이, 본 발명에 의하면, 금속 플러그와 금속배선 사이에서 발생되는 기생 스페이서를 최대한 억제하여 이 들간의 접촉면적을 향상시킴으로써 금속배선의 신뢰성을 향상킬 수 있다. 이에 따라, 반도체 소자의 특성을 개선시킬 수 있다.As described above, according to the present invention, the parasitic spacers generated between the metal plug and the metal wiring can be suppressed as much as possible to improve the contact area therebetween, thereby improving the reliability of the metal wiring. As a result, the characteristics of the semiconductor device can be improved.
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| KR20070066432A (en) * | 2005-12-22 | 2007-06-27 | 매그나칩 반도체 유한회사 | Method of forming copper wiring in semiconductor device |
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| KR100278274B1 (en) * | 1997-12-30 | 2001-03-02 | 김영환 | A method for forming stack contact in semiconductor device |
| KR100322536B1 (en) * | 1999-06-29 | 2002-03-18 | 윤종용 | Forming method of a polysilicon contact plug using etch-back and manufacturing method of a semiconductor device using the same |
| KR20030002525A (en) * | 2001-06-29 | 2003-01-09 | 주식회사 하이닉스반도체 | Method for forming a metal line |
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| KR20070066432A (en) * | 2005-12-22 | 2007-06-27 | 매그나칩 반도체 유한회사 | Method of forming copper wiring in semiconductor device |
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