KR20080060721A - A shift register - Google Patents

Abstract

A shift register is provided to prevent the multi-output accompanied with the coupling phenomenon by discharging the node periodically for improving the quality of picture. Plural stages(ST) receive at least two clock pulses(CLK) having the phase difference and outputs the scan pulse(Vout) in turn. A pull-up switching device(Trpu) is turned-on or turned-off according to the logical state of the node. In case of turn-on, the pull-up switching device receives the first clock pulse(CLK1) and outputs the scan pulse. A node control part controls the logical state of the node. A shift register includes the clock transmission line for supplying the second clock pulse(CLK2) and the capacitor connected among nodes. The first and the second clock pulses have a phase difference of one clock pulse width. The first clock pulse is outputted earlier than the second clock pulse.

Description

A shift register

1 shows one stage in a conventional shift register.

2 illustrates a shift register according to an embodiment of the present invention.

3 is a timing diagram of various signals supplied or output to each stage of FIG.

4 is a diagram illustrating a circuit configuration of a second stage of FIG. 2.

5 is a view illustrating the first to third stages of FIG.

FIG. 6 illustrates another circuit configuration of the second stage of FIG. 2.

7 is a timing diagram of first to fourth clock pulses.

8A and 8B are diagrams for comparing the output from the shift register according to the present invention with the output from the shift register according to the prior art.

* Explanation of symbols on the main parts of the drawings

Vout: Scan pulse VDD: Voltage source for charging

VSS: Voltage source for discharge Vst: Start pulse

Trpu: Pull-up Switching Device Trpd: Pull-down Switching Device

ST: Stage CLK: Clock Pulse

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register of a liquid crystal display, and more particularly, to a shift register capable of preventing multiple outputs due to a coupling phenomenon.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Here, the gate lines are sequentially driven by a scan pulse, which is generated by a shift register.

1 is a diagram illustrating one stage in a conventional shift register.

The conventional stage includes a node control unit 101 for controlling the charging and discharging states of the first node n1 and the second node n2, and the scan pulse Vout according to the signal state of the first node n1. And a pull-down switching device Trpd for outputting a discharge voltage source VSS according to the signal state of the second node n2.

Here, the first node n1 and the second node n2 are alternately charged and discharged. Specifically, when the first node n1 is charged, the second node n2 is charged. The discharged state is maintained, and when the second node n2 is in a charged state, the first node n1 is maintained in a discharged state.

In this case, the scan pulse Vout is output from the pull-up switching device Trpu when the first node n1 is in a charged state, and the pull-down switching device of the output unit when the second node n2 is in a charged state. The discharge voltage source VSS is output from Trpd.

The scan pulse Vout output from the pull-up switching device Trpu and the discharge voltage source VSS output from the pull-down switching device Trpd are supplied to the corresponding gate line.

Here, the gate terminal of the pull-up switching device Trpu is connected to the first node n1, the drain terminal is connected to the clock transmission line to which the clock pulse CLK is applied, and the source terminal is connected to the gate line. do. The clock pulse CLK has a high state and a low state periodically and is supplied to the drain terminal of the pull-up switching device Trpu. In this case, the pull-up switching device Trpu outputs any one of the clock pulses CLK in the high state input every cycle. The clock pulse CLK output at this particular time point is the scan pulse Vout for driving the gate line.

This specific time point means a time point after the first node n1 is charged. That is, the pull-up switching device Trpu is at the specific time point (ie, the time point at which the first node n1 is charged) among the clock pulses CLK which are continuously input to its drain terminal periodically. The input clock pulse CLK of the high state is output as the scan pulse Vout. After the output of the scan pulse Vout, the first node n1 is maintained in a discharge state until the next frame period starts, so that the pull-up switching device Trpu has one scan pulse Vout per frame. ) Will be printed. However, since the clock pulse CLK is output several times in one frame period, the clock pulse even when the pull-up switching device Trpu is turned off, that is, even when the first node n1 is discharged. CLK is continuously input to the drain terminal of the pull-up switching element Trpu.

In other words, the pull-up switching device Trpu is turned on only once for one frame, and outputs the clock pulse CLK input to its drain terminal as a scan pulse Vout during this turn-on period. .

Thereafter, the pull-up switching device Trpu is turned off until the start of the next frame period, so that the pull-up switching device Trpu is clock pulse CLK at its drain terminal no matter how long it is turned off. Is input, it cannot be output as a scan pulse (Vout). However, as the clock pulse CLK is periodically applied to the drain terminal of the pull-up switching device Trpu, the first node n1 and the pull-up to which the gate terminal of the pull-up switching device Trpu is connected are connected. Coupling occurs between the drain terminals of the switching element Trpu. Due to such a coupling phenomenon, the first node n1 is continuously charged with a predetermined voltage corresponding to the clock pulse CLK.

Then, the first node n1 may be maintained in a charged state at any moment. That is, the first node n1 may be maintained in a charged state at an unwanted timing. In this case, the first node n1 may be maintained in the charging state more than once in one frame period, whereby the pull-up switching device Trpu may be turned on more than once in one frame period. As a result, a multi-output phenomenon in which one stage outputs two or more scan pulses Vout in one frame period may occur due to the coupling phenomenon as described above.

As such, when one stage outputs two or more scan pulses Vout during one frame period, the quality of an image displayed on the liquid crystal panel is degraded.

The present invention has been made to solve the above problems, by supplying the clock pulse of the low state passing through the capacitor to the node every time the clock pulse is output, by periodically discharging the node, it is possible to prevent the multi-output The purpose is to provide a shift register.

The shift register according to the present invention for achieving the above object includes a plurality of stages that receive at least two clock pulses having a phase difference from each other and sequentially outputs scan pulses; Each stage is turned on or off in accordance with the logic state of the node, the pull-up switching device for receiving a first clock pulse when the turn-on outputs a scan pulse; A node controller for controlling a logical state of the node; And a capacitor connected between the clock transmission line supplying the second clock pulse and the node.

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a shift register according to an exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating a timing diagram of various signals supplied or output to each stage of FIG. 2.

The shift register according to the embodiment of the present invention includes n stages ST1 to STn and one dummy stage STn + 1 as shown in FIG. 2. Here, each of the stages ST1 to STn outputs one scan pulse Vout1 to Voutn + 1 for one frame period, in which case the scan pulses are sequentially sequentially from the first stage ST1 to the dummy stage STn + 1. Outputs

Here, scan pulses Vout1 to Voutn output from the stages ST1 to STn except for the dummy stage STn + 1 are sequentially supplied to gate lines of the liquid crystal panel (not shown). The gate lines are sequentially scanned.

That is, first, the first stage ST1 outputs the first scan pulse Vout1, and then the second stage ST2 outputs the second scan pulse Vout2, and then, the third stage ST3. Outputs the third scan pulse Vout3, and finally, the nth stage STn outputs the nth scan pulse Voutn.

Meanwhile, after the n-th stage STn outputs the n-th scan pulse Voutn, the dummy stage STn + 1 outputs the n + 1-th scan pulse Voutn + 1, wherein the dummy stage The nth + 1th scan pulse Voutn + 1 output from (STn + 1) is not supplied to the gate line but is supplied only to the nth stage STn.

This shift register is built in the liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion. The shift register is built in the non-display portion.

The entire stages ST1 to STn + 1 of the shift registers configured as described above are charged voltage sources VDD, discharge voltage sources VSS, and the first and second clock pulses CLK1 to CLK2 circulating with sequential phase differences. ) Is authorized.

The charging voltage source VDD and the discharging voltage source VSS are both DC voltage sources, the charging voltage source VDD exhibits positive polarity, and the discharging voltage source VSS exhibits negative polarity. Meanwhile, the discharge voltage source VSS may be a ground voltage.

The first and second clock pulses CLK1 and CLK2 are output with phase differences from each other. That is, the second clock pulse CLK2 is phase-delayed by one pulse width than the first clock pulse CLK1 and output. Here, the first clock pulse CLK1 and the second clock pulse CLK2 are inverted in phase with each other. Accordingly, the second clock pulse CLK2 indicates a low state when the first clock pulse CLK1 is high and the second clock pulse CLK2 when the first clock pulse CLK1 is low. Indicates a high state.

The first and second clock pulses CLK1 and CLK2 are sequentially output, and are also output in a circular manner. That is, after the first clock pulse CLK1 to the second clock pulse CLK2 are sequentially output, the first clock pulse CLK1 to the second clock pulse CLK2 are sequentially output.

According to the circuit configuration of the stage, the number of clock pulses supplied to one stage may vary.

The first stage ST1 located on the uppermost side of the stages ST1 to STn + 1 may include the above-described charging voltage source VDD, the discharge voltage source VSS, and the first and second clock pulses CLK1. , In addition to CLK2), is further supplied with a start pulse Vst.

The clock pulses CLK1 and CLK2 are output several times in one frame period, but the start pulse Vst is output only once in one frame period.

In other words, each clock pulse CLK1 and CLK2 periodically shows several active states (high states) during one frame period, but the start pulse Vst shows only one active state during one frame period.

In this case, the second clock pulse CLK2 and the start pulse Vst may be output in synchronization with each other. In this case, the second clock pulse CLK2 is first outputted among the first and second clock pulses CLK1 and CLK2.

In order for each stage ST1 to STn + 1 to output a scan pulse, an enable operation of each stage ST1 to STn + 1 must be preceded. The stage being enabled means that the stage is set to a state capable of outputting, that is, a state capable of outputting a clock pulse supplied thereto as a scan pulse. To this end, each stage ST1 to STn + 1 is enabled by receiving scan pulses from the stage located at the front end thereof.

For example, the k th stage is enabled in response to the scan pulse from the k-1 st stage.

Since the stage does not exist in front of the first stage ST1 positioned at the uppermost side, the first stage ST1 is enabled in response to the start pulse Vst from the timing controller.

In addition, each stage ST1 to STn + 1 is disabled in response to the scan pulse from the next stage. When the stage is disabled, it means that the stage is reset to a state in which the output is impossible, that is, the clock pulse supplied to the stage cannot be output as a scan pulse.

For example, the kth stage is disabled in response to the scan pulse from the k + 1th stage.

The configuration of each stage ST1 to STn + 2 in the shift register configured as described above will be described in more detail as follows.

Since the configurations of the stages ST1 to STn + 2 are the same, only the second stage ST2 will be described as an example.

4 is a diagram illustrating a circuit configuration of the second stage of FIG. 2.

As illustrated in FIG. 4, the second stage ST2 includes a node n, a node controller NC, a pull-up switching device Trpu, a pull-down switching device Trpd, and a capacitor C. As shown in FIG.

The node controller NC controls the signal state of the node n. In other words, the node controller NC makes the node n in a charged state or in a discharged state.

The pull-up switching device Trpd is turned on when the node n is in a charged state, and then outputs a clock pulse input to the node n in the turned-on state. The clock pulse output from this turned on pull-up switching element is a scan pulse.

The pull-up switching device Trpu provided in the k-th stage outputs a clock pulse in response to the charging voltage source VDD supplied to the node of the k-th stage, and the k-th gate line, the k + 1 stage, and It supplies to a k-1st stage. To this end, the gate terminal of the pull-up switching device (Trpu) is connected to the node n, the drain terminal is connected to the clock pulse supply line, the source terminal is the k-th gate line, the k + 1 stage, It is connected to the k-1st stage.

For example, the pull-up switching device Trpu provided in the second stage ST2 of FIG. 4 outputs the second scan pulse Vout2, and the second gate line, the third stage ST3, and the first stage ST3 are output. It supplies to stage ST1.

The pull-down switching device Trpd is turned on in response to a clock pulse. In this turned-on state, the discharge voltage source VSS inputted thereto is output.

The pull-down switching device Trpd included in the k-th stage outputs a discharge voltage source in response to a clock pulse, and supplies it to the k-th gate line, the k + 1th stage, and the k-1st stage. To this end, the gate terminal of the pull-down switching device (Trpd) is connected to the clock pulse supply line, the source terminal is connected to the power supply line for discharge, and the drain terminal is the k-th gate line, k + 1 stage and Is connected to the k-th stage.

For example, the pull-down switching device Trpd provided in the second stage ST2 of FIG. 4 outputs the discharge voltage source VSS, and the second gate line GL2, the third stage ST3, And the first stage ST1.

The gate line is charged by the scan pulse output from the pull-up switching device Trpu, and is discharged by the discharge voltage source VSS output from the pull-down switching device Trpd.

The capacitor C is connected between the clock transmission line for transmitting the clock pulse and the node n. The clock pulse is supplied to the node n through the capacitor C, wherein the clock pulse supplied to the node n and the clock pulse supplied to the pull-up switching device Trpu have a different phase. Pulse.

For example, as shown in FIG. 4, the first clock pulse CLK1 is supplied to the capacitor C provided in the second stage ST2, and the second clock pulse CLK2 is supplied to the pull-up switching device Trpu. ) Is supplied.

The node controller NC includes first and second switching devices Tr1 and Tr2.

The first switching device Tr1 included in the node control unit NC of the kth stage responds to the k-1th scan pulse output from the pull-up switching device Trpu of the k-1st stage, thereby providing a charging voltage source ( VDD1) is supplied to the node n of the kth stage. To this end, the gate terminal of the first switching device Tr1 provided in the k-th stage is connected to the source terminal of the pull-up switching device Trpu provided in the k-th stage, and the drain terminal is supplied with a charging power supply. Is connected to the line, and the source terminal is connected to the node n of the k-th stage.

For example, the first switching device Tr1 included in the second stage ST2 of FIG. 4 may be configured to respond to the first scan pulse Vout1 from the first stage ST1 of the second stage ST2. The node n is charged with the charging voltage source VDD.

Meanwhile, the first switching device Tr1 may be turned on by the scan pulse from the front stage to supply the scan pulse from the front stage to the node. That is, the first switching device Tr1 provided in the kth stage is turned on by receiving the k-1th scan pulse from the k-1st stage, and transmits the k-1th scan pulse to node n. The node may be charged by supplying it.

The second switching device Tr2 provided in the node controller NC of the kth stage is configured to discharge the voltage source (in response to the k + 1th scan pulse output from the pull-up switching device Trpu of the k + 1st stage). VSS) is supplied to the node n of the kth stage. To this end, the gate terminal of the second switching device Tr2 provided in the k-th stage is connected to the source terminal of the pull-up switching device Trpu provided in the k + 1th stage, and the source terminal supplies a power supply for discharging. The drain terminal is connected to the node n of the kth stage.

For example, the second switching device Tr2 provided in the second stage ST2 may respond to the node n of the second stage ST2 in response to the third scan pulse Vout3 from the third stage ST3. ) Is discharged to the discharge voltage source VSS.

The operation of the shift register according to the embodiment of the present invention configured as described above is as follows.

FIG. 5 is a diagram illustrating the first to third stages of FIG. 2.

First, the operation during the initial period T0 will be described.

During the initial period TO, as shown in FIG. 3, only the start pulse Vst and the second clock pulse CLK2 are kept high and the first clock pulse CLK1 is kept low.

The start pulse Vst is input to the first stage ST1. Specifically, the start pulse Vst is supplied to the gate terminal of the first switching device Tr1 provided in the first stage ST1.

Then, the first switching device Tr1 of the first stage ST1 is turned on, and at this time, the charging voltage source VDD is turned on through the turned-on first switching device Tr1. It is supplied to the node n of ST1). In addition, the second clock pulse CLK2 in the high state is supplied to the node n of the first stage ST1 through the capacitor C.

Accordingly, the node n of the first stage ST1 is charged by the charging voltage source VDD and the second clock pulse CLK2 in a high state, and a gate terminal of the charged node n is charged. The connected pull-up switching device Trpu is turned on.

On the other hand, since there is no output from the second stage ST2 in this initial period T0, the second switching element Tr2 of the first stage ST1 is turned off. In addition, since the second clock pulse CLK2 is low in this initial period T0, the pull-down switching device Trpd of the first stage ST1 is turned off.

Next, the operation during the first period T1 will be described.

During the first period T1, as shown in FIG. 3, only the first clock pulse CLK1 is kept high, and the start pulse Vst and the second clock pulse CLK2 are kept low. .

Therefore, the first switching device Tr1 of the first stage ST1 is turned off in response to the start pulse Vst in the low state.

At this time, as the first switching device Tr1 is turned off, the node n of the first stage ST1 is maintained in a floating state.

Therefore, the node n of the first stage ST1 is kept in the charged state by the charging voltage source VDD which has been applied during the initial period T0.

Here, although the second clock pulse CLK2 in a low state is supplied to the node n through the capacitor C, the voltage of the node n may decrease slightly, but the second clock pulse CLK2 may be reduced. Since N is supplied directly to the node n through the capacitor C rather than directly supplied to the node n, the amount of reduction in the voltage of the node n is minimal. Therefore, in this first period T1, the node n is kept in a charged state.

Accordingly, the pull-up switching device Trpu of the first stage ST1 having the gate terminal connected to the node n is turned on.

In this case, the first clock pulse CLK1 is supplied to the drain terminal of the turned-on pull-up switching device Trpu. Then, the charging voltage source VDD charged in the node n of the first stage ST1 is amplified (bootstrapping phenomenon bootstrapping). Since the voltage of the node n is amplified by this bootstrapping phenomenon, the amount of voltage reduction of the node n described above is sufficiently compensated.

Therefore, the first clock pulse CLK1 supplied to the drain terminal of the pull-up switching device Trpu provided in the first stage ST1 is stably output through the source terminal of the pull-up switching device Trpu. The first clock pulse CLK1 output from the pull-up switching device Trpu is the first scan pulse Vout1.

The output first scan pulse Vout1 is supplied to the first gate line GL1 and serves as a scan pulse for driving the first gate line GL1.

In addition, the first scan pulse Vout1 output from the pull-up switching device Trpu of the first stage ST1 is supplied to the second stage ST2 to supply the node n of the second stage ST2. It acts as a start pulse Vst for charging.

That is, in the first period T1, the first scan pulse Vout1 output from the first stage ST1 is supplied to the gate terminal of the first switching element Tr1 provided in the second stage ST2. .

Accordingly, the node n of the second stage ST2 is charged by the charging voltage source VDD.

Next, the operation during the second period T2 will be described.

During the second period T2, as shown in FIG. 3, only the second clock pulse CLK2 remains high. On the other hand, the start pulse Vst, the first clock pulse CLK1, and the first scan pulse Vout1 are kept low.

Accordingly, the first switching device Tr1 of the second stage ST2 is turned off in response to the first scan pulse Vout1 in the low state.

At this time, as the first switching device Tr1 is turned off, the node n of the second stage ST2 is maintained in a floating state.

Therefore, the node n of the second stage ST2 is continuously maintained in the charging state by the charging voltage source VDD applied during the first period T1.

Here, although the first clock pulse CLK1 in a low state is supplied to the node n through the capacitor C, the voltage of the node n may decrease slightly, but the first clock pulse CLK1 may be reduced. Since N is supplied directly to the node n through the capacitor C rather than directly supplied to the node n, the amount of reduction in the voltage of the node n is minimal. Therefore, in this second period T2, the node n is kept in a charged state.

Accordingly, the pull-up switching device Trpu of the second stage ST2 having the gate terminal connected to the node n is turned on.

Accordingly, the node n of the second stage ST2 is kept in a charged state by the charging voltage source VDD applied during the first period T1, and a gate terminal is connected to the node n. The pull-up switching device Trpu of the second stage ST2 is turned on.

In this case, the second clock pulse CLK2 is supplied to the drain terminal of the turned-on pull-up switching device Trpu. Then, the charging voltage source VDD charged in the node n of the second stage ST2 is amplified (bootstrapping phenomenon bootstrapping). Since the voltage of the node n is amplified by this bootstrapping phenomenon, the amount of voltage reduction of the node n described above is sufficiently compensated.

Therefore, the second clock pulse CLK2 supplied to the drain terminal of the pull-up switching device Trpu provided in the second stage ST2 is stably output through the source terminal of the pull-up switching device Trpu. The second clock pulse CLK2 output from the pull-up switching device Trpu is the second scan pulse Vout2.

The second scan pulse Vout2 output from the second stage ST2 acts as a scan pulse supplied to the second gate line GL2 to drive the second gate line GL2, and the third stage. It is supplied to ST3 and acts as a start pulse Vst for charging the node n of the third stage ST3.

In addition, the second scan pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the first stage ST1 to supply the node n of the first stage ST1. It serves to discharge. That is, the first stage ST1 is disabled in response to the second scan pulse Vout2 from the second stage ST2. If this is explained in more detail as follows.

The second scan pulse Vout2 output from the second stage ST2 in the second period T2 is supplied to the gate terminal of the second switching element Tr2 provided in the first stage ST1.

Then, the second switching device Tr2 is turned on, and the discharge voltage source VSS is connected to the node n of the first stage ST1 through the turned-on second switching device Tr2. Supplied. Then, the node n is discharged, and the pull-up switching device Trpu having a gate terminal connected to the discharged node n is turned off.

In addition, the second clock pulse CLK2 output in the second period T2 is supplied to the pull-down switching device Trpd provided in the first stage ST1. As a result, the pull-down switching device is turned on. The discharge voltage source VSS is supplied to the first gate line through the turned on pull-down switching device Trpd. As a result, the first gate line is discharged.

In addition, the second clock pulse CLK2 in the high state output in the second period T2 is supplied to the node n of the first stage ST1 through the capacitor C.

In this case, as described above, since the second switching device Tr2 of the first stage supplies the discharge voltage source VSS to the node n of the first stage ST1, the node n is charged. It is maintained in a discharged state.

In this manner, in the third period T3, the third stage ST3 outputs the third scan pulse Vout3.

At this time, the first clock pulse CLK1 is kept high and the second clock pulse CLK2 is kept low in the third period T3.

The first clock pulse CLK1 in the high state and the second clock pulse CLK2 in the low state, which are output in the third period T3, are also supplied to the first stage ST1.

That is, the first clock pulse CLK1 is supplied to the pull-up switching device Trpu provided in the first stage ST1, and the second clock pulse CLK2 is supplied to the first stage through a capacitor C. It is supplied to the node n of ST1.

During the period other than the initial period T0 and the first period T1, that is, during the non-output period, the node n of the first stage ST1 should be kept in a discharged state. A coupling phenomenon may occur because the first clock pulse CLK1 in a state is periodically supplied to the pull-up switching device Trpu provided in the first stage ST1.

However, whenever the first clock pulse CLK1 remains high, a second clock pulse CLK2 maintaining a low state is connected to the node n of the first stage ST1 through the capacitor C. Supplied. Accordingly, the voltage due to the coupling phenomenon may be prevented from accumulating at the node n of the first stage ST1.

That is, the second clock pulse CLK2 in the low state is periodically supplied to the node n in the non-output period.

As described above, in the present invention, the clock pulse is supplied to the node n through the capacitor C, so that the node of the stage is kept charged during the output period, and the node n of the stage is periodically discharged during the non-output period. By doing so, the multi output due to the coupling phenomenon can be prevented.

FIG. 6 is a diagram illustrating another circuit configuration of the second stage of FIG. 2.

The configuration of the stage shown in FIG. 6 is the same as the stage of FIG. 4 described above, only the pull-down switching element is turned on in response to the scan pulse from the next stage.

The pull-down switching device Trpu included in the k-th stage outputs the discharge voltage source VSS in response to the k + 1 scan pulse output from the pull-up switching device Trpu of the k + 1th stage, and It supplies to a kth gate line, a k + 1th stage, and a k-1st stage. To this end, the gate terminal of the pull-down switching device (Trpd) is connected to the source terminal of the pull-up switching device (Trpu) provided in the k + 1 stage, the source terminal is connected to the power supply line for discharge, and drain The terminal is connected to the kth gate line, the k + 1th stage, and the k-1st stage.

For example, the pull-down switching device Trpd included in the second stage ST2 of FIG. 6 outputs the discharge voltage source VSS, and the second gate line GL2, the third stage ST3, and It supplies to the 1st stage ST1.

Meanwhile, the shift register according to the embodiment of the present invention may receive first to fourth clock pulses.

7 is a diagram illustrating timing diagrams of the first to fourth clock pulses.

The first to fourth clock pulses CLK1 to CLK4 are output with phase differences from each other. That is, the second clock pulse CLK2 is output by being phase-delayed by one pulse width than the first clock pulse CLK1, and the third clock pulse CLK3 is one pulse than the second clock pulse CLK2. Phase delayed by a width is output, the fourth clock pulse (CLK4) is phase-delayed by one pulse width than the third clock pulse (CLK3) and output, and the first clock pulse (CLK1) is the fourth clock pulse Phase delayed by one pulse width from (CLK4) is output.

The first to fourth clock pulses CLK1 to CLK4 are sequentially output, and are also output in a circular manner. That is, after the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output, the first clock pulse CLK1 to the fourth clock pulse CLK4 are sequentially output. Therefore, the first clock pulse CLK1 is output in a period corresponding to the fourth clock pulse CLK4 and the second clock pulse CLK2.

In this case, the pull-up switching device Trpu included in the fourth m + 1 stage (m is a natural number including 0) receives the first clock pulse CLK1 and the pull-up switching device included in the fourth m + 2 stage ( The Trpu receives the second clock pulse CLK2 and the pull-up switching device included in the 4m + 3 stage receives the third clock pulse CLK3 and the pull-up switching device included in the 4m + 4 stage Trpu is supplied with a fourth clock pulse CLK4.

Each stage is further supplied with a clock pulse for supplying its own node through a capacitor, which may be any clock pulse having a phase different from that supplied to the pull-up switching device provided therein. none.

For example, if the first clock pulse CLK1 is supplied to the pull-up switching device of the first stage ST1, the remaining second to fourth clock pulses CLK2 to CLK4 are supplied to the capacitor C of the first stage ST1. Any one may be supplied.

In this case, the clock pulse supplied to the capacitor C and the clock pulse supplied to the pull-up switching device Trpu are preferably output in a period adjacent to each other, and the clock pulse supplied to the capacitor is supplied to the pull-up switching device. It is desirable to output faster than the supplied clock pulse.

On the other hand, between the clock pulses (CLK1 to CLK4, or CLK1 and CLK2) output in a period adjacent to each other, their high period may partially overlap. In this case, the scan pulses Vout1 to Voutn + 1 output from the stages ST1 to STn + 1 also partially overlap their high intervals.

Of course, the start pulse Vst may also be output to overlap the clock pulses CLK1 to CLK4, or CLK1 and CLK2.

In this case, the kth stage is enabled by the k-1th scan pulse from the k-1st stage, and the kth stage is disabled by the k + 2th scan pulse from the k + 2th stage.

That is, the second switching device Tr2 and the second pull-down switching device Trpd2 provided in the kth stage operate by the k + 2th scan pulse from the k + 2th stage.

8A and 8B are diagrams for comparing the output from the shift register according to the present invention with the output from the shift register according to the prior art.

8A is a diagram illustrating a node voltage and an output voltage of a shift register according to the related art. As shown in the figure, a voltage of a node increases with time according to a coupling phenomenon, and accordingly, an output voltage, that is, a gate It can be seen that the voltage magnitude of the scan pulse supplied to the line increases with time.

When the size of the scan pulse is continuously increased to have a certain size or more, a thin film transistor (a switching element for supplying a data signal to a pixel of a liquid crystal display device) connected to the gate line is turned on in a non-output period. Can be.

FIG. 8B is a view showing the node voltage and the output voltage of the shift register according to the present invention. As shown in the figure, it can be seen that the node voltage and the output voltage are maintained at a constant level without increasing over time. . This is because the node is periodically discharged by the clock pulse supplied through the capacitor.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The shift register according to the present invention as described above has the following effects.

The shift register of the present invention includes a capacitor connected between the node and the clock transmission line for transmitting the clock pulse.

The clock pulse passing through the capacitor discharges the node periodically in the non-output period, thereby preventing the multi output due to the coupling phenomenon.

Claims (9)

A plurality of stages that are supplied with at least two clock pulses having a phase difference from each other and sequentially output scan pulses; Each stage, A pull-up switching device which is turned on or turned off according to a logic state of a node and receives a first clock pulse and outputs a scan pulse when the node is turned on; A node controller for controlling a logical state of the node; And, And a capacitor connected between the clock transmission line supplying a second clock pulse and the node. The method of claim 1, And the first clock pulse and the second clock pulse have a phase difference of at least one clock pulse width. The method of claim 2, And the second clock pulse is output faster in time than the first clock pulse. The method of claim 2, Each stage is supplied with two clock pulses having a phase difference from each other. And the first clock pulse and the second clock pulse have a phase difference of one pulse width. The method of claim 2, Each stage is supplied with four clock pulses having a phase difference from each other. And the first clock pulse and the second clock pulse have a phase difference of at least one clock pulse width. The method of claim 1, The node control unit of each stage is A first switching device for supplying a first voltage source to the node in response to a scan pulse from a front end stage; A second switching element for supplying a second voltage source to the node in response to a scan pulse from a next stage; And, And a pull-down switching device for supplying the second voltage source to an output terminal of the pull-up switching device in response to a control signal. The method of claim 6, And the first voltage source is a scan pulse from a front stage or a charging voltage source supplied from the outside. The method of claim 6, And the control signal is a third clock pulse or a scan pulse from a next stage. The method of claim 8, And the third clock pulse is a clock pulse having the same phase as the second clock pulse.

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