KR20080056954A - 박막 트랜지스터 제조방법 - Google Patents
박막 트랜지스터 제조방법 Download PDFInfo
- Publication number
- KR20080056954A KR20080056954A KR1020060130180A KR20060130180A KR20080056954A KR 20080056954 A KR20080056954 A KR 20080056954A KR 1020060130180 A KR1020060130180 A KR 1020060130180A KR 20060130180 A KR20060130180 A KR 20060130180A KR 20080056954 A KR20080056954 A KR 20080056954A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor layer
- thin film
- film transistor
- polycrystalline silicon
- source
- Prior art date
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- 239000010409 thin film Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000004381 surface treatment Methods 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 2
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 22
- 238000002425 crystallisation Methods 0.000 description 12
- 239000010408 film Substances 0.000 description 11
- 230000008025 crystallization Effects 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3063—Electrolytic etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
Claims (5)
- 기판을 제공하고;상기 기판상에 비정질 실리콘을 형성하고;상기 비정질 실리콘을 열처리하여 다결정 실리콘을 형성하고;상기 다결정 실리콘을 표면처리하고;상기 다결정 실리콘을 패터닝하여 반도체층을 형성하고;상기 반도체층과 절연되면서 중첩되는 게이트 전극을 형성하고;상기 반도체층에 불순물을 주입하여 소스/드레인 영역을 형성하고;상기 게이트 전극과 절연되면서, 상기 소스/드레인 영역과 연결되는 소스/드레인 전극을 형성하는 것을 포함하는 박막 트랜지스터 제조방법.
- 제1항에 있어서,상기 열처리는 H2O 분위기에서 진행하는 것을 특징으로 하는 박막 트랜지스터 제조방법.
- 제2항에 있어서,상기 열처리는 550 내지 750 ℃의 온도 및 10,000 내지 2 MPa 압력으로 진행하는 것을 특징으로 하는 박막 트랜지스터 제조방법.
- 제1항에 있어서,상기 표면처리는 습식식각인 것을 특징으로 하는 박막 트랜지스터 제조방법.
- 제4항에 있어서,상기 습식식각은 NH4F 17%, HF 0.7%로 구성되는 BOE를 사용하는 것을 특징으로 하는 박막 트랜지스터 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060130180A KR100841370B1 (ko) | 2006-12-19 | 2006-12-19 | 박막 트랜지스터 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060130180A KR100841370B1 (ko) | 2006-12-19 | 2006-12-19 | 박막 트랜지스터 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20080056954A true KR20080056954A (ko) | 2008-06-24 |
KR100841370B1 KR100841370B1 (ko) | 2008-06-26 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020060130180A KR100841370B1 (ko) | 2006-12-19 | 2006-12-19 | 박막 트랜지스터 제조방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100841370B1 (ko) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100482164B1 (ko) * | 2002-10-25 | 2005-04-14 | 엘지.필립스 엘시디 주식회사 | 폴리실리콘 박막트랜지스터의 제조방법 |
KR100623687B1 (ko) * | 2004-05-18 | 2006-09-19 | 삼성에스디아이 주식회사 | 반도체 소자 형성 방법 |
-
2006
- 2006-12-19 KR KR1020060130180A patent/KR100841370B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
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KR100841370B1 (ko) | 2008-06-26 |
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