KR20080021389A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20080021389A KR20080021389A KR1020060084754A KR20060084754A KR20080021389A KR 20080021389 A KR20080021389 A KR 20080021389A KR 1020060084754 A KR1020060084754 A KR 1020060084754A KR 20060084754 A KR20060084754 A KR 20060084754A KR 20080021389 A KR20080021389 A KR 20080021389A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 62
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000007517 polishing process Methods 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims abstract description 5
- 238000001039 wet etching Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 5
- 238000005429 filling process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
Description
도 1a 내지 도 1f는 본 발명의 일 실시 예에 따른 반도체 소자의 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A through 1F are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
100 : 반도체 기판 102 : 터널 산화막100 semiconductor substrate 102 tunnel oxide film
104 : 제1 폴리실리콘막 106 : 제1 하드 마스크막104: first polysilicon film 106: first hard mask film
108 : 제2 하드 마스크막 110 : 트렌치 108: second hard mask film 110: trench
112 : 제1 절연막 114 : 희생막112: first insulating film 114: sacrificial film
116 : 제2 절연막 118 : 소자 분리막 116: second insulating film 118: device isolation film
120 : 유전체막 122 : 제2 폴리실리콘막120 dielectric film 122 second polysilicon film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 매립 물질로 HDP(High Density Plasma) 산화막을 이용하여 보이드(void) 없이 트렌치를 완전히 매립하기 위한 반도체 소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for completely filling a trench without voids by using an HDP (High Density Plasma) oxide film as a buried material.
일반적인 반도체 소자의 제조방법에 대해 설명하면 다음과 같다.The manufacturing method of a general semiconductor device is as follows.
반도체 기판 상부에 적층된 터널 산화막, 제1 폴리실리콘막, 하드 마스크막 및 반도체 기판의 일부를 식각하여 트렌치를 형성한 후 이를 매립하기 위해 전체 구조 상부에 제1 절연막을 증착한다. 이때, 제1 절연막은 HDP 산화막으로 증착한다. 습식 식각 공정을 실시하여 제1 절연막을 일부 제거하고, 트렌치가 완전히 매립되도록 전체 구조 상부에 제2 절연막을 증착한 후 연마 공정을 실시하여 소자분리막을 형성한다. A tunnel oxide layer, a first polysilicon layer, a hard mask layer, and a portion of the semiconductor substrate that are stacked on the semiconductor substrate are etched to form a trench, and then a first insulating layer is deposited on the entire structure to fill the trench. At this time, the first insulating film is deposited by the HDP oxide film. A part of the first insulating film is removed by a wet etching process, a second insulating film is deposited on the entire structure so that the trench is completely filled, and a polishing process is performed to form the device isolation film.
그러나, 소자가 점점 더 고집적화되어감에 따라 기존에 사용하였던 트렌치 매립 방법인 DWD(Deposition-Wet etch-Deposition) 방법을 사용하게 되면, 습식 식각 공정시 터널 산화막 측면이 노출되어 습식 식각시 사용되는 식각 용액에 데미지(damage)를 받아 험프(hump)가 발생되고, 터널 산화막이 붕괴(degradation)되어 소자 특성을 저하시킨다. 노출된 터널 산화막의 데미지를 최소화하기 위해 트렌치를 매립하기 위해 사용되는 제1 절연막의 두께를 더 두껍게 하면, 트렌치 매립 마진이 부족하여 보이드 문제를 유발시킨다. 또한, 트렌치 매립 마진을 확보하기 위해 습식 식각량을 증가시키면, 터널 산화막 측면이 노출되어 터널 산화막 측면에 데미지를 유발하게 된다. 이와 같이 제1 절연막 증착 두께와 습식 식각량의 상관 관계로 인하여 소자가 미세화될수록 트렌치 매립 마진은 더 악화한다. However, as the device is becoming more and more highly integrated, when the DWD (Deposition-Wet etch-Deposition) method, which is a conventional trench filling method, is used, the etching surface is exposed during the wet etching process because the tunnel oxide layer is exposed. The solution is damaged due to damage and a hump is generated, and the tunnel oxide film is degraded to degrade device characteristics. If the thickness of the first insulating film used to fill the trench is further thickened to minimize the damage of the exposed tunnel oxide film, the trench filling margin is insufficient to cause a voiding problem. In addition, when the wet etching amount is increased to secure the trench filling margin, the tunnel oxide side surface is exposed to damage the tunnel oxide layer side. As a result of the correlation between the first insulating layer deposition thickness and the wet etching amount, the trench filling margin worsens as the device becomes finer.
또한, 소자가 고집적화되어감에 따라 일반적으로 종래에 많이 사용되던 로코스(LOCOS)형 소자 분리막 형성 공정을 사용하고 있었으나, 지금은 액티브 영역의 면적을 늘릴 수 있는 STI(Shallow Trench Isolation) 공정이 많이 사용되고 있다. STI 공정은 반도체 기판 상부에 적층된 터널 산화막, 제1 폴리실리콘막, 하드 마스크막용 질화막과 산화막 및 반도체 기판의 일부를 순차적으로 식각하여 트렌치를 형성한 후 트렌치를 매립하기 위해 전체 구조 상부에 절연막을 형성하는 것이다.In addition, as the device is highly integrated, a LOCOS type isolation layer forming process, which is generally used in the past, has been used. However, many STI (Shallow Trench Isolation) processes can increase the area of the active region. It is used. In the STI process, a tunnel oxide film, a first polysilicon film, a hard mask film nitride film, an oxide film, and a portion of the semiconductor substrate are sequentially etched to form a trench, and then an insulating film is formed on the entire structure to fill the trench. To form.
그러나, 상기와 같이 트렌치 매립 공정을 실시할 경우, 액티브 영역 상부 가장 자리의 산화막이 전세정(pre-cleaning) 공정과 습식 식각 공정시 빨리 식각되어 과도하게 침식되는 모트(moat)가 형성된다. 이를 해결하기 위해 현재 가장 많이 사용하고 있는 트렌치 매립 물질이 HDP 산화막이다. However, when the trench filling process is performed as described above, a moat is formed in which the oxide film in the upper edge of the active region is rapidly etched and excessively eroded during the pre-cleaning process and the wet etching process. In order to solve this problem, the most commonly used trench filling material is HDP oxide.
그러나, 소자가 축소화되어감에 따라 트렌치 매립 물질로 HDP 산화막을 사용할 경우, 액티브 상부 영역에 HDP 산화막이 두껍게 증착되어 트렌치 내에 보이드가 형성된다. 이러한 보이드의 형성으로 인하여 소자 특성이 열화된다. 보이드 없이 트렌치를 매립하기 위해 매립 특성이 좋은 SOG(Spin On Glass) 계열의 산화막을 사용하는 방법이 있다. However, as the device shrinks, when the HDP oxide film is used as the trench filling material, a thick HDP oxide film is deposited on the active upper region to form voids in the trench. The formation of these voids causes deterioration of device characteristics. There is a method using a SOG (Spin On Glass) -based oxide film with good buried characteristics to fill the trench without voids.
그러나, SOG(Spin On Glass) 계열의 산화막을 사용할 경우, SOG의 특성이 HDP 산화막의 특성보다 좋지 않아 SOG 계열의 산화막으로 매립된 소자 분리막은 소자 분리막 역할을 하지 못하고 결국 소자 특성을 열화시킨다. However, when the SOG (Spin On Glass) oxide film is used, the SOG characteristics are not as good as those of the HDP oxide film. Thus, the device isolation layer embedded with the SOG oxide oxide does not function as a device isolation film and eventually degrades device characteristics.
상술한 문제점을 해결하기 위해 안출된 본 발명의 목적은 매립 물질로 HDP 산화막을 이용하여 보이드 없이 트렌치를 완전히 매립하기 위한 반도체 소자의 제조방법을 제공하는 데 있다. An object of the present invention devised to solve the above-described problem is to provide a method for manufacturing a semiconductor device for completely filling the trench without voids using the HDP oxide film as a buried material.
본 발명의 일 실시 예에 따른 반도체 소자의 제조방법은, 반도체 기판 상부에 적층된 터널 산화막, 폴리실리콘막, 하드 마스크막 및 상기 반도체 기판의 일부를 순차적으로 식각하여 트렌치를 형성하는 단계와, 상기 트렌치의 일부가 매립되도록 상기 트렌치를 포함한 전체 구조 상부에 제1 절연막을 형성하는 단계와, 상기 트렌치가 완전히 매립되도록 전체 구조 상부에 스트레스와 밀도가 상기 제1 절연막과 다른 희생막을 형성한 후 연마 공정을 실시하는 단계와, 식각 공정을 실시하여 상기 트렌치 내에 매립된 상기 제1 절연막과 희생막을 일정 두께 정도 제거하는 단계와, 식각 공정을 실시하여 상기 트렌치 내에 매립된 상기 희생막을 완전히 제거하는 단계와, 상기 트렌치가 완전히 매립되도록 전체 구조 상부에 상기 제1 절연막과 동일한 물질인 제2 절연막을 형성한 후 상기 제1 하드 마스크막 상부가 노출될 때까지 연마 공정을 실시하여 소자 분리막을 형성하는 단계를 포함하는 반도체 소자의 제조방법을 제공한다.A method of manufacturing a semiconductor device according to an embodiment of the present invention may include forming a trench by sequentially etching a tunnel oxide layer, a polysilicon layer, a hard mask layer, and a portion of the semiconductor substrate stacked on the semiconductor substrate; Forming a first insulating film on the entire structure including the trench so that a portion of the trench is buried, and forming a sacrificial film different from the first insulating film having a stress and a density on the entire structure so that the trench is completely embedded Performing an etching process, removing the first insulating film and the sacrificial film embedded in the trench by a predetermined thickness, and performing an etching process to completely remove the sacrificial film embedded in the trench; A second material of the same material as the first insulating film on the entire structure so that the trench is completely buried After the insulating film is formed, performing a polishing process until the upper portion of the first hard mask film is exposed to provide a method for manufacturing a semiconductor device comprising the step of forming an isolation layer.
상기에서, 하드 마스크막은 질화막 및 산화막으로 구성된다.In the above, the hard mask film is composed of a nitride film and an oxide film.
트렌치를 형성한 후 트렌치 내에 열 산화 공정을 실시하는 단계를 더 포함한 다.And forming a trench and then performing a thermal oxidation process in the trench.
제1 절연막은 HDP 산화막으로 형성하되, 바이어스를 사용하지 않거나, 낮은 바이어스를 사용한다.The first insulating film is formed of an HDP oxide film but does not use a bias or uses a low bias.
희생막은 SOG 산화막, PSG막, BPSG막 또는 포토레지스트막으로 형성된다.The sacrificial film is formed of an SOG oxide film, a PSG film, a BPSG film or a photoresist film.
희생막을 형성한 후 열처리 공정을 실시하는 단계를 더 포함한다.After forming the sacrificial film further comprises the step of performing a heat treatment process.
제1 절연막과 희생막을 일정 두께 제거 공정시 건식 식각 공정을 실시한다.The dry etching process is performed during the process of removing the thickness of the first insulating film and the sacrificial film.
희생막 제거 공정시 습식 식각 공정을 실시하고, 습식 식각 공정시 제1 절연막과 식각 선택비가 다른 용액을 사용한다.A wet etching process is performed during the sacrificial film removal process, and a solution having a different etching selectivity from the first insulating film is used during the wet etching process.
제2 절연막은 HDP 산화막으로 형성하되, 높은 바이어스를 이용한다.The second insulating film is formed of an HDP oxide film, but uses a high bias.
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 일 실시 예에 따른 반도체 소자의 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A through 1F are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(100) 내에 웰 이온 주입 공정 및 문턱 전압(Vt) 조절 이온 주입 공정을 실시한다. 반도체 기판(100) 상부에 터널 산화막(102), 플로팅 게이트용 제1 폴리실리콘막(104), 제1 하드 마스크막(106) 및 제2 하드 마스크막(108)을 순차적으로 형성한 후 제2 하드 마스크막(108), 제1 하드 마스크막(106), 제1 폴리실리콘막(104), 터널 산화막(102) 및 반도체 기판(100)의 일부를 순차적으로 식각하여 트렌치(110)를 형성한다. 이때, 제1 하드 마스크막(106) 은 질화막으로 형성하고, 제2 하드 마스크막(108)은 산화막으로 형성한다.Referring to FIG. 1A, a well ion implantation process and a threshold voltage (Vt) controlled ion implantation process are performed in the semiconductor substrate 100. After the tunnel oxide film 102, the first polysilicon film 104 for floating gate, the first hard mask film 106, and the second hard mask film 108 are sequentially formed on the semiconductor substrate 100, a second The trench 110 is formed by sequentially etching the hard mask film 108, the first hard mask film 106, the first polysilicon film 104, the tunnel oxide film 102, and a portion of the semiconductor substrate 100. . At this time, the first hard mask film 106 is formed of a nitride film, and the second hard mask film 108 is formed of an oxide film.
도 1b를 참조하면, 트렌치(110) 내에 열 산화 공정을 실시한 후 트렌치(110)의 일부가 매립되도록 전체 구조 상부에 제1 절연막(112)을 형성한다. 이때, 제1 절연막(112)은 HDP 산화막으로 형성하되, 바이어스를 인가하지 않거나, 낮은 바이어스를 인가한다. 트렌치(110)가 완전히 매립되도록 전체 구조 상부에 스트레스(stress)와 밀도가 제1 절연막(112)과 다른 희생막(114)을 형성한다. 이때, 희생막(114)은 SOG 산화막, PSG막, BPSG막 또는 포토레지스트막으로 형성한다. Referring to FIG. 1B, after the thermal oxidation process is performed in the trench 110, a first insulating layer 112 is formed on the entire structure such that a portion of the trench 110 is buried. In this case, the first insulating layer 112 is formed of an HDP oxide layer, but does not apply a bias, or applies a low bias. A sacrificial layer 114 having a different stress and density from the first insulating layer 112 is formed on the entire structure so that the trench 110 is completely buried. In this case, the sacrificial film 114 is formed of an SOG oxide film, a PSG film, a BPSG film, or a photoresist film.
도 1c를 참조하면, 제1 절연막(112)과 희생막(114)의 밀도를 높이기 위해 열처리 공정을 실시한 후 제1 하드 마스크막(106) 상부가 노출될 때까지 연마 공정을 실시한다. Referring to FIG. 1C, after the heat treatment process is performed to increase the density of the first insulating film 112 and the sacrificial film 114, the polishing process is performed until the upper portion of the first hard mask film 106 is exposed.
도 1d를 참조하면, 건식 식각 공정을 실시하여 트렌치(110) 내에 매립된 제1 절연막(112)과 희생막(114)을 일정 두께 정도 제거한 후 습식 식각 공정을 실시하여 트렌치(110) 내에 매립된 희생막(114)을 완전히 제거한다. 이때, 희생막(114)을 제거하기 위한 습식 식각 공정시 제1 절연막(112)과 식각 선택비가 다른 용액을 사용한다. Referring to FIG. 1D, the first insulating layer 112 and the sacrificial layer 114 embedded in the trench 110 are removed by a dry etching process, and a wet etching process is performed to fill the trench 110. The sacrificial layer 114 is completely removed. In this case, a solution having a different etching selectivity from the first insulating layer 112 is used in the wet etching process for removing the sacrificial layer 114.
도 1e를 참조하면, 트렌치(110)가 완전히 매립되도록 전체 구조 상부에 제1 절연막(112)과 동일한 물질인 제2 절연막(116)을 형성한 후 제1 하드 마스크막(106) 상부가 노출될 때까지 연마 공정을 실시하여 소자 분리막(118)을 형성한다. 이때, 제2 절연막(116)은 HDP 산화막으로 형성하되, 높은 바이어스를 인가한다.Referring to FIG. 1E, the second insulating layer 116 made of the same material as the first insulating layer 112 is formed on the entire structure such that the trench 110 is completely filled, and then the upper portion of the first hard mask layer 106 may be exposed. The polishing process is performed until the device isolation layer 118 is formed. At this time, the second insulating film 116 is formed of an HDP oxide film, but a high bias is applied.
도 1f를 참조하면, 제1 하드 마스크막(106)을 제거한 후 소자 분리막(118) 상부를 식각하여 소자 분리막(118)의 EFH(Effective Field Height)를 조절한다. 전체 구조 상부에 유전체막(120) 및 컨트롤 게이트용 제2 폴리실리콘막(122)을 순차적으로 형성한다. Referring to FIG. 1F, after removing the first hard mask layer 106, the upper portion of the isolation layer 118 is etched to adjust the effective field height (EFH) of the isolation layer 118. The dielectric film 120 and the second polysilicon film 122 for the control gate are sequentially formed on the entire structure.
트렌치(110) 매립 공정시 에스펙트 비(Aspect Ratio; AR)로 인하여 트렌치(110) 내에 발생하는 보이드를 제거하기 위하여 상기와 같이 HDP 산화막이 트렌치(110) 내에 일부 매립된 상태에서 SOG를 이용하여 트렌치(110)를 완전히 매립한 후 건식 식각 공정 및 습식 식각 공정을 실시하여 SOG를 완전히 제거함으로써 트렌치(110) 내에 보이드 없이 HDP 산화막을 매립할 수 있다. 또한, 상기와 같은 방법은 STI 매립 공정시에만 국한된 것이 아니라, PMD(Poly to Metal Dielectric)층과 IMD(Inter Metal Dielectric)층에서도 적용가능하다. In order to remove voids generated in the trench 110 due to an aspect ratio (AR) during the filling process of the trench 110, as described above, the HDP oxide layer is partially embedded in the trench 110 using SOG. After completely filling the trench 110, a dry etching process and a wet etching process may be performed to completely remove the SOG, thereby filling the HDP oxide layer without the voids in the trench 110. In addition, the above method is not limited to the STI buried process, but is also applicable to a poly to metal dielectric (PMD) layer and an inter metal dielectric (IMD) layer.
본 발명의 기술 사상은 상기 바람직한 실시 예에 따라 구체적으로 기술되었으나, 상기한 실시 예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시 예가 가능함을 이해할 수 있을 것이다. Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같이 본 발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.
첫째, HDP 산화막이 트렌치 내에 일부 매립된 상태에서 SOG를 이용하여 트렌 치를 완전히 매립한 후 건식 식각 공정 및 습식 식각 공정을 실시하여 SOG를 완전히 제거함으로써 트렌치 내에 보이드 없이 HDP 산화막을 매립할 수 있다. First, in a state in which the HDP oxide is partially embedded in the trench, the trench is completely filled with SOG, followed by a dry etching process and a wet etching process to completely remove the SOG, thereby filling the HDP oxide layer without voids in the trench.
둘째, 트렌치 매립 공정시 기존에 사용하던 HDP 산화막을 이용함으로써 개발 기간 단축 및 타사와의 경쟁력에서 우수할 수 있다.Second, by using the HDP oxide film used in the trench filling process, it can be shortened the development period and excellent in competitiveness with other companies.
셋째, 본 발명은 STI 매립 공정시에만 국한된 것이 아니라, PMD층과 IMD층에서도 적용가능하다. Third, the present invention is not only limited to the STI buried process but also applicable to the PMD layer and the IMD layer.
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