KR100874429B1 - Gap filling method in semiconductor device manufacturing - Google Patents

Gap filling method in semiconductor device manufacturing Download PDF

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KR100874429B1
KR100874429B1 KR1020020086433A KR20020086433A KR100874429B1 KR 100874429 B1 KR100874429 B1 KR 100874429B1 KR 1020020086433 A KR1020020086433 A KR 1020020086433A KR 20020086433 A KR20020086433 A KR 20020086433A KR 100874429 B1 KR100874429 B1 KR 100874429B1
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hdp oxide
oxide film
film
gap
hdp
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KR20040059928A (en
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김한민
김진웅
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means

Abstract

본 발명은 소정의 갭이 형성된 반도체기판 전면에 HDP-CVD방식으로 상기 갭이 매립되도록 제1HDP산화막을 증착하는 단계와 상기 제1HDP산화막상에 갭 매립능력이 우수한 낮은 점성을 갖는 물질을 증착하는 단계, 상기 증착된 물질층 및 제1HDP산화막을 에치백하거나 CMP에 의해 연마하여 기판 표면을 평탄화하는 단계, 상기 제1HDP산화막위에 남아 있는 물질층을 전부 제거하는 단계 및 기판 전면에 제2HDP산화막을 증착한 후, CMP공정을 진행하는 단계를 포함하여 이루어지는 반도체소자 제조시의 갭 매립방법을 제공한다. 본 발명에 의하면, 보이드의 발생없이 기존의 HDP절연막의 특성을 그대로 이용함으로써 향후 100nm 이하급 소자에서의 소자분리막 형성공정을 안정적으로 진행할 수 있다. 따라서 신규장비의 투자를 감소시킬 수 있으며, 보이드 없는 갭 매립을 통해 안정적인 수율을 확보할 수 있다.
The present invention comprises the steps of depositing a first HDP oxide film so as to fill the gap by the HDP-CVD method on the entire surface of the semiconductor substrate having a predetermined gap and the step of depositing a material having a low gap excellent excellent gap filling capability on the first HDP oxide film Etching the backed material layer and the first HDP oxide layer or polishing by CMP to planarize the surface of the substrate, removing all remaining material layers on the first HDP oxide layer, and depositing the second HDP oxide layer on the entire surface of the substrate. Thereafter, a method of filling gaps in manufacturing a semiconductor device, which includes performing a CMP process, is provided. According to the present invention, by using the characteristics of the existing HDP insulating film as it is without the generation of voids, it is possible to reliably proceed with the device isolation film forming process in the device below 100nm class. Therefore, investment in new equipment can be reduced, and stable yield can be secured by voidless gap filling.

Description

반도체소자 제조시의 갭 매립방법{Method for filling gap in fabrication of semiconductor device} Method for filling gap in fabrication of semiconductor device             

도1a 내지 도1f는 본 발명의 일실시예에 의한 반도체소자의 소자분리막 형성공정을 나타낸 단면도.1A to 1F are cross-sectional views illustrating a device isolation film forming process of a semiconductor device according to an embodiment of the present invention.

도2는 기존의 HDP-CVD 방식에 의한 소자분리막 공정에서의 증착두께에 따른 프로파일을 변화를 나타낸 도면.Figure 2 is a view showing a change in profile according to the deposition thickness in the device isolation film process by the conventional HDP-CVD method.

도3은 기존의 HDP-CVD 방식에 의한 소자분리막 공정에 있어서 애스펙트비 4.5 이상 되는 곳에서 발생하는 보이드를 나타낸 도면.
3 is a view showing voids generated at an aspect ratio of 4.5 or more in a device isolation film process by a conventional HDP-CVD method.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 실리콘기판 12 : 패드산화막, 패드질화막11 silicon substrate 12 pad oxide film, pad nitride film

13 : 제1HDP산화막 14 : SOG 13: first HDP oxide film 14: SOG

16 : 제2HDP산화막
16: second HDP oxide film

본 발명은 절연막의 갭 매립방법에 관한 것으로, 특히 HDP-CVD 산화막과 낮은 점성(viscosity)을 갖는 물질을 이용하여 절연막의 갭을 매립하는 방법에 관한 것이다.The present invention relates to a gap filling method of an insulating film, and more particularly, to a method of filling a gap of an insulating film by using a material having a low viscosity and a HDP-CVD oxide film.

반도체소자의 고집적화에 따라 소자분리막의 갭 매립공정이 한층 어려워지고 있다. 현재 사용중인 HDP-CVD방식으로는 100nm 이하급 소자에 대해서는 적용이 어려워지리가 예상된다. 이는 HDP-CVD 공정의 특성에 의한 것으로, 패턴의 바닥부분에서는 스퍼터링이 이루어지고, 동시에 패턴의 윗부분에 대해서는 증착과 스퍼터링이 동시에 이루어져 삼각형 모양이 형성된다. 또한, 일정 두께 이하로 증착이 이루어지는 동안 삼각형이 형성되는 패턴 상부의 어깨 부분의 위치는 거의 변화가 없고 바닥부분이 차 올라오게 된다. 이때, 패턴의 윗부분에서 스퍼터링된 원자나 분자들이 이웃한 패턴의 어깨 부분에 재증착됨으로써 증착 프로파일이 기울어지게 된다. HDP-CVD공정에서는 일단 프로파일이 기울어지게 되면 보이드(void)가 발생하게 된다. 이러한 보이드는 소자의 신뢰성에 문제를 야기한다.BACKGROUND With the high integration of semiconductor devices, the gap filling process of device isolation films has become more difficult. The HDP-CVD method currently in use is expected to be difficult to apply to devices below the 100nm class. This is due to the characteristics of the HDP-CVD process, and sputtering is performed at the bottom of the pattern, and at the same time, deposition and sputtering are simultaneously performed on the upper part of the pattern to form a triangular shape. In addition, while the deposition is performed below a certain thickness, the position of the shoulder portion of the upper portion of the pattern where the triangle is formed is almost unchanged and the bottom portion is raised. At this time, the deposition profile is inclined as the atoms or molecules sputtered at the upper portion of the pattern are redeposited on the shoulder portion of the neighboring pattern. In the HDP-CVD process, once the profile is tilted, voids are generated. These voids cause problems in the reliability of the device.

도2는 소자분리막 형성공정에서 기존의 HDP-CVD방식에서의 증착두께에 따른 프로파일의 변화를 보인 것이고, 도3은 애스펙트비 4.5이상이 되는 곳에서 발생한 보이드를 나타낸 것이다.
Figure 2 shows the change of the profile according to the deposition thickness in the conventional HDP-CVD method in the device isolation film forming process, Figure 3 shows the voids generated at an aspect ratio of 4.5 or more.

본 발명은 상기 문제점을 해결하기 위한 것으로써, 막질을 향상시킬 수 있는 HDP공정과 갭 매립능력이 우수한 낮은 점성을 갖는 물질을 이용하여 보이드의 발생없이 절연막의 갭을 매립하는 방법을 제공하는데 목적이 있다.
An object of the present invention is to provide a method for filling gaps in an insulating film without generating voids by using an HDP process capable of improving film quality and a material having a low viscosity having excellent gap filling ability. have.

상기 목적을 달성하기 위한 본 발명의 절연막의 갭 매립방법은, 소정의 갭이 형성된 반도체기판 전면에 HDP-CVD방식으로 상기 갭이 매립되도록 제1HDP산화막을 증착하는 단계와 상기 제1HDP산화막상에 갭 매립능력이 우수한 낮은 점성을 갖는 물질을 증착하는 단계, 상기 증착된 물질층 및 제1HDP산화막을 에치백하거나 CMP에 의해 연마하여 기판 표면을 평탄화하는 단계, 상기 제1HDP산화막위에 남아 있는 물질층을 전부 제거하는 단계 및 기판 전면에 제2HDP산화막을 증착한 후, CMP공정을 진행하는 단계를 포함하여 이루어지는 것을 특징으로 한다.
The gap filling method of the insulating film of the present invention for achieving the above object comprises the step of depositing a first HDP oxide film so as to fill the gap by the HDP-CVD method on the entire surface of the semiconductor substrate having a predetermined gap and a gap on the first HDP oxide film Depositing a low viscosity material having excellent buried capability, etching the deposited material layer and the first HDP oxide film or polishing by CMP to planarize the substrate surface, and completely removing the material layer remaining on the first HDP oxide film. And removing the second HDP oxide film on the entire surface of the substrate and then performing a CMP process.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도1a 내지 도1f에 본 발명의 일실시예에 의한 소자분리막 형성공정을 공정순서에 따라 도시하였다. 1A to 1F illustrate a process of forming an isolation layer in accordance with an embodiment of the present invention.

먼저, 도1a에 나타낸 바와 같이 실리콘기판(11)상에 소자분리를 위한 패드산화막과 패드질화막(12)을 적층하고, 소자분리막 형성용 마스크(도시하지 않음)를 이용하여 노광 및 식각을 진행하여 실리콘기판(11)에 약 2500Å 깊이의 트렌치를 형성한다. 이어서 HDP-CVD방식으로 트렌치내에 보잉(bowing)이 생기지 않을 정도로 최대한 두껍게, 예를 들면 1000~2500Å 두께로 제1HDP산화막(13)을 증착한다. First, as shown in FIG. 1A, a pad oxide film and a pad nitride film 12 for device isolation are stacked on a silicon substrate 11, and exposure and etching are performed using a device isolation film forming mask (not shown). A trench about 2500 microns deep is formed in the silicon substrate 11. Subsequently, the first HDP oxide film 13 is deposited to be as thick as possible so as not to cause bowing in the trench by HDP-CVD.

다음에 도1b에 나타낸 바와 같이 갭 매립능력이 뛰어난 낮은 점성을 갖는 절연막으로서 SOG공정을 이용하여 HSQ(hydrogen silsequioxane)계열의 무기 SOG(14)를 코팅하고 베이킹(baking) 처리한 후, 200℃~1000℃ 이하의 온도에서 큐어링(curing)한다. 이때, 유기계열의 SOG(polysiloxane)를 이용할 수 있으며, 이 경우 SOG 큐어링은 200℃~600℃ 에서 진행하거나 생략한다.Next, as shown in Fig. 1B, an insulating film having a low viscosity having excellent gap filling ability is coated with an inorganic SOG 14 of HSQ (hydrogen silsequioxane) series using an SOG process, and then baked, and then subjected to baking. Curing at a temperature of 1000 ° C. or less. At this time, the organic series of SOG (polysiloxane) can be used, in this case SOG curing is carried out or omitted at 200 ℃ ~ 600 ℃.

또한, SOG 대신에 포토레지스트나 유기 BARC(bottom anti-reflective coating) 또는 APL(advanced planarization layer, SiH4+H2O2 반응막)을 이용할 수도 있다. 이 경우, 플로우 매립(flow fill)을 하기 위해 N2 또는 Ar등의 불활성 기체 분위기에서 증착된 막에 압력을 가한다. APL막을 이용하는 경우에는 기판온도 -20℃~100℃ 범위에서 증착한다.In addition, a photoresist, an organic bottom anti-reflective coating (BARC) or an advanced planarization layer (SiH 4 + H 2 O 2 reaction film) may be used instead of SOG. In this case, pressure is applied to the film deposited in an inert gas atmosphere such as N 2 or Ar to flow fill. In the case of using an APL film, it is deposited at a substrate temperature of -20 ° C to 100 ° C.

이어서 도1c에 나타낸 바와 같이 상기 SOG막(14)을 에치백하거나 CMP에 의해 연마하여 제1HDP산화막(13)의 갭내에 매립된 포켓형태를 갖도록 만든다. 이때, SOG의 에치백공정은 HDP산화막과 SOG막에 대한 식각률이 패드질화막에 비해 빠른 선택비로 실시한다. HDP산화막과 SOG막은 1:1 정도의 선택비를 갖도록 SOG막을 에치백한다. Subsequently, as shown in FIG. 1C, the SOG film 14 is etched back or polished by CMP to have a pocket shape embedded in the gap of the first HDP oxide film 13. At this time, the etch back process of the SOG is carried out with the selectivity of the etching rate for the HDP oxide film and SOG film faster than the pad nitride film. The HDP oxide film and the SOG film etch back the SOG film to have a selectivity of about 1: 1.

다음에 도1d에 나타낸 바와 같이 포켓형태로 남아 있는 SOG를 전부 습식식각에 의해 제거한다. 이때, SOG의 경우에는 산 계열의 에쳔트로 제거하고, 포토레지 스트 또는 BARC막을 사용한 경우에는 산 또는 유기용제로 제거한다. Next, as shown in FIG. 1D, all SOG remaining in the pocket form is removed by wet etching. At this time, in the case of SOG, it is removed with an acid-based etchant, and when a photoresist or BARC film is used, it is removed with an acid or an organic solvent.

이어서 도1e에 나타낸 바와 같이 기판 전면에 다시 제2HDP산화막(16)을 증착한 후, CMP공정을 진행하고 패드질화막을 인산으로 벗겨내면 도1f에 나타낸 바와 같이 제2HDP산화막(16)도 포켓형태로 제1HDP산화막(13)의 갭에 남게 된다.Subsequently, as shown in FIG. 1E, the second HDP oxide film 16 is deposited on the entire surface of the substrate, and then the CMP process is performed and the pad nitride film is peeled off with phosphoric acid. As shown in FIG. 1F, the second HDP oxide film 16 also has a pocket shape. It remains in the gap of the first HDP oxide film 13.

상기와 같이 함으로써 보이드의 발생없이 HDP산화막으로 이루어진 소자분리막을 형성할 수 있다. As described above, the device isolation film made of the HDP oxide film can be formed without generating voids.

한편, 본 발명의 다른 실시예로서 상기와 같이 낮은 점성을 갖는 절연막을 이용하지 않고 제1HDP산화막을 부분 증착한 후, 곧바로 CMP공정을 진행하여 HDP산화막 윗부분의 산 모양을 완전히 제거하면서 하지층위에서 연마 정지가 일어나도록 한다. CMP공정후에는 트렌치내의 슬러리를 제거하기 위해 메가소닉(megasonic) 세정 및/또는 NH4OH/H2O2/H2O의 용액을 이용한 세정을 행한다. Meanwhile, as another embodiment of the present invention, after partially depositing the first HDP oxide film without using an insulating film having a low viscosity as described above, the CMP process is immediately performed to completely remove the acid shape on the HDP oxide film and polish it on the underlying layer. Allow a stop to occur. After the CMP process, a megasonic wash and / or a solution of NH 4 OH / H 2 O 2 / H 2 O are performed to remove the slurry in the trench.

상기 제1HDP산화막과 제2HDP산화막 증착시 O2, SiH4 등의 반응성가스와 Ar 및/또는 He 등의 비활성 가스를 이용하여 압력 30mTorr 이하, 전체 가스유량 100sccm~500sccm, O2/SiH4 가스비율 1.2~4.0, 플라즈마 발생파워 1500W~6000W, 플라즈마내의 이온 바이어스 파워 500W~4000W 범위에서 증착하는 것이 바람직하다.When the first HDP oxide film and the second HDP oxide film are deposited, a reactive gas such as O 2 , SiH 4 , and an inert gas such as Ar and / or He are used at a pressure of 30 mTorr or less, and the total gas flow rate of 100 sccm to 500 sccm and O 2 / SiH 4 gas ratio. It is preferable to deposit in 1.2-4.0, plasma generation power 1500W-6000W, and ion bias power 500W-4000W in plasma.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명에 의하면, 보이드의 발생없이 기존의 HDP절연막의 특성을 그대로 이용함으로써 향후 100nm 이하급 소자에서의 소자분리막 형성공정을 안정적으로 진행할 수 있다. 따라서 신규장비의 투자를 감소시킬 수 있으며, 보이드 없는 갭 매립을 통해 안정적인 수율을 확보할 수 있다.According to the present invention, by using the characteristics of the existing HDP insulating film as it is without the generation of voids, it is possible to reliably proceed with the device isolation film forming process in the device below 100nm class. Therefore, investment in new equipment can be reduced, and stable yield can be secured by voidless gap filling.

Claims (13)

반도체기판 상에 패드질화막을 형성하는 단계;Forming a pad nitride film on the semiconductor substrate; 노광 및 식각을 진행하여 상기 반도체기판에 소정의 갭을 형성하는 단계;Forming a predetermined gap in the semiconductor substrate by performing exposure and etching; 상기 반도체기판 전면에 HDP-CVD방식으로 상기 갭이 매립되도록 제1HDP산화막을 증착하는 단계;Depositing a first HDP oxide layer on the entire surface of the semiconductor substrate such that the gap is buried in the HDP-CVD method; 상기 제1HDP산화막 상에 절연막을 증착하는 단계;Depositing an insulating film on the first HDP oxide film; 증착된 상기 절연막 및 제1HDP산화막을 에치백하거나 CMP에 의해 연마하는 단계;Etching back the deposited insulating film and the first HDP oxide film or polishing by CMP; 상기 제1HDP산화막 위에 남아 있는 절연막을 전부 제거하는 단계; 및Removing all of the insulating film remaining on the first HDP oxide film; And 상기 반도체기판 전면에 제2HDP산화막을 증착한 후, CMP공정을 진행하는 단계Depositing a second HDP oxide film on the entire surface of the semiconductor substrate, and then performing a CMP process 를 포함하는 반도체소자 제조시의 갭 매립방법.A gap filling method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 소정의 갭은 실리콘기판에 소자분리를 위한 트렌치임을 특징으로 하는 반도체소자 제조시의 갭 매립방법.Wherein the predetermined gap is a trench for device isolation on a silicon substrate. 제1항에 있어서,The method of claim 1, 상기 제1HDP산화막은 1000∼2500Å 두께로 증착하는 것을 특징으로 하는 반도체소자 제조시의 갭 매립방법.The first HDP oxide film is deposited to a thickness of 1000 to 2500 GPa. 제1항에 있어서,The method of claim 1, 상기 절연막은 SOG, 포토레지스트, 유기 BARC 또는 APL을 이용하는 것을 특징으로 하는 반도체소자 제조시의 갭 매립방법.The insulating film is SOG, photoresist, organic BARC or APL gap gap filling method for manufacturing a semiconductor device, characterized in that. 제4항에 있어서,The method of claim 4, wherein 상기 SOG는 무기계열의 SOG HSQ를 이용하거나 유기계열의 SOG를 이용하는 것을 특징으로 하는 반도체소자 제조시의 갭 매립방법.The SOG is a gap filling method for manufacturing a semiconductor device, characterized in that using an inorganic SOG HSQ or an organic SOG. 제1항에 있어서,The method of claim 1, 상기 절연막으로 SOG를 사용할 경우, 제1HDP산화막 위에 SOG를 코팅하고 베이킹 처리한 후, 큐어링하여 SOG막을 형성하는 것을 특징으로 하는 반도체소자 제조시의 갭 매립방법.In the case of using the SOG as the insulating film, a gap filling method for manufacturing a semiconductor device, characterized in that after the SOG is coated on the first HDP oxide film, baked, and cured to form an SOG film. 제1항에 있어서,The method of claim 1, 상기 절연막으로 포토레지스트나 유기 BARC 또는 APL을 이용할 경우, N2 또는 Ar의 불활성 기체 분위기에서 증착된 막에 압력을 가하는 것을 특징으로 하는 반도체소자 제조시의 갭 매립방법.When using a photoresist, organic BARC or APL as the insulating film, a gap filling method for manufacturing a semiconductor device, characterized in that the pressure applied to the film deposited in an inert gas atmosphere of N2 or Ar. 제1항에 있어서,The method of claim 1, 상기 절연막으로 APL을 이용하는 경우에는 기판온도 -20~100℃ 범위에서 증착하는 것을 특징으로 하는 반도체소자 제조시의 갭 매립방법.In the case of using APL as the insulating film, the gap filling method for manufacturing a semiconductor device, characterized in that the deposition at a substrate temperature of -20 ~ 100 ℃ range. 제1항에 있어서,The method of claim 1, 상기 에치백은 제1HDP산화막과 절연막의 선택비를 1:1 로 하여 실시하는 것을 특징으로 하는 반도체소자 제조시의 갭 매립방법.Wherein the etch back is made with a selectivity ratio of the first HDP oxide film and the insulating film to be 1: 1. 삭제delete 삭제delete 삭제delete 제1항에 있어서,The method of claim 1, 상기 제1HDP산화막과 제2HDP산화막 증착시 O2, SiH4 의 반응성가스와 Ar 및/또는 He 의 비활성 가스를 이용하여 압력 30mTorr 이하, 전체 가스유량 100~500sccm, O2/SiH4 가스비율 1.2~4.0, 플라즈마 발생파워 1500~6000W, 플라즈마내의 이온 바이어스 파워 500~4000W 범위에서 증착하는 것을 특징으로 하는 반도체소자 제조시의 갭 매립방법.Deposition of the first HDP oxide film and the second HDP oxide film by using a reactive gas of O2, SiH4 and an inert gas of Ar and / or He below 30 mTorr, total gas flow rate of 100 to 500 sccm, O2 / SiH4 gas ratio of 1.2 to 4.0, and plasma generation A gap filling method for fabricating a semiconductor device, characterized in that deposition is performed at a power of 1500 to 6000 W and an ion bias power of 500 to 4000 W in plasma.
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