KR20080002607A - Method for manufacturing semiconductor device having bulb-type recessed channel - Google Patents

Abstract

A method for fabricating a semiconductor device having a bulb-type recess channel is provided to remove a leakage current generated in an adjacent junction region by a passing gate by minimizing the loss of an isolation layer. A first trench(106) is formed in a semiconductor substrate(100). A buffer layer and a hard mask layer for filling the trench are sequentially stacked on the front surface of the semiconductor substrate. The hard mask layer is patterned to form a hard mask layer pattern exposing an isolation region of the semiconductor substrate. An isolation trench is formed in the semiconductor substrate by using the hard mask layer pattern as a mask. An isolation layer(118) is formed to fill the isolation trench. The hard mask layer pattern is removed. An etch process is performed by using the buffer layer as an etch barrier layer to form a second trench(120) of a spherical type so that a bulb-type trench(122) for a recess channel is formed which is composed of the first and second trenches. A gate stack(132) is formed which overlaps the bulb-type trench for the recess channel. The buffer layer can include an oxide layer. The hard mask can include a nitride layer.

Description

Method for manufacturing semiconductor device having bulb type recess channel {Method for manufacturing semiconductor device having bulb-type recessed channel}

1 is a schematic view of a semiconductor device having a bulb type recess channel according to the prior art.

2A to 10 are views illustrating a method of manufacturing a semiconductor device having a bulb type recess channel according to the present invention.

The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a bulb type recess channel.

Recently, as the degree of integration of integrated circuit semiconductor devices has increased and design rules have sharply decreased, it is increasingly difficult to secure stable operation of transistors. In particular, as the design rules of semiconductor devices are reduced to 70 nm or less, the size of transistors is also reduced, leading to a threshold of cell threshold voltage (Vt) and refresh characteristics. In particular, high-speed DDR2 (Double Data Rate) DRAM products, which are currently commercially available, have dramatically reduced data retention time by setting test conditions at high temperatures compared to conventional DDR DRAM products.

Accordingly, various methods for securing the effective channel length without increasing the design rule have been studied in various ways. As a method of securing the effective channel length as described above, the length of the channel is further extended for the limited gate line width. Attempts have been made to further extend the length of the channels.

1 is a schematic view of a semiconductor device having a bulb type recess channel according to the prior art.

Referring to FIG. 1, in a semiconductor device having a bulb type recess channel, an upper end portion 20a has a neck shape in a semiconductor substrate 10 in which an active region is set by an isolation layer 12, and a lower end portion ( A bulb type recess channel 20 having a sphere shape 20b is disposed. The gate stack 18 including the gate insulating layer 14 and the gate electrode 16 overlaps the bulb type recess channel 20.

The bulb type recess channel 20 is implemented by dividing the etching process in two stages. This two-step etching increases the effective channel length by forming a sphere in the shape of a sphere while keeping the critical dimension (CD) of the upper portion the same. The increase of the effective channel increases the cell threshold voltage, thereby adjusting the appropriate cell threshold voltage required for normal cell transistor operation to the dose amount of the cell channel ion. When the cell threshold voltage is adjusted by the dose of cell channel ions, there is an electric field reduction effect at the cell junction, thereby improving the refresh characteristics.

Meanwhile, high thermal oxide (HTO) is used as a barrier layer in the etching process for implementing the lower portion in the form of a sphere. The barrier film serves to protect the silicon on the sidewalls of the neck formation of the upper end. However, when the margin of the barrier layer is insufficient, the silicon on the trench region may be exposed during the etching process, and thus may be exposed to the risk of attack. In particular, the largest loss of the oxide film of the device isolation layer in the region A in which the neck of the upper end is formed occurs, and thus the possibility of silicon attack is the highest.

In addition, the loss of the device isolation layer 12 also increases during the one-step etching and the two-step etching, thereby reducing the step between the device isolation layer and the active region. As a result, a gate formed on the device isolation layer to control a neighboring active region is partially formed to pass through the next active region, and an electric field is formed in an adjacent junction region by a passing gate. May be concentrated and the junction leakage current may increase. Accordingly, there is a demand for a method of improving refresh characteristics by securing a margin of a cell threshold voltage together with advantages of a transistor including a bulb type recess channel.

The technical problem to be achieved by the present invention is to minimize the loss of the device isolation film to eliminate the leakage current generated in the adjacent junction region by the passing gate, and at the same time, the bulb type recess that can prevent the silicon attack of the active region There is provided a method for manufacturing a semiconductor device having a channel.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a bulb type recess channel according to the present invention, forming a first trench in the semiconductor substrate; Sequentially depositing a buffer layer and a hard mask layer filling the first trench on the semiconductor substrate; Patterning the hard mask layer to form a hard mask layer pattern exposing the device isolation region of the semiconductor substrate; Forming a device isolation trench in the semiconductor substrate using the hard mask layer pattern as a mask; Forming a device isolation film to fill the device isolation trench; Removing the hard mask layer pattern; Etching the buffer layer using an etch barrier layer to form a spherical second trench in the lower end of the first trench to form a bulb type trench channel trench formed of the first trench and the second trench; And forming a gate stack overlapping the bulb type trench channel trench.

In the present invention, the buffer film may include an oxide film, and the hard mask film may include a nitride film.

The forming of the first trench may include forming an etch mask layer on a semiconductor substrate; Forming a photoresist pattern exposing a first trench formation region on the etch mask layer; Etching the etching mask layer exposing the photoresist pattern as a mask to form an etching mask layer pattern; And forming a first trench in the semiconductor substrate using the etching mask layer pattern as a mask.

The etching mask layer is formed by including an oxide layer formed using a thermal oxide film (HTO) or chemical vapor deposition (CVD).

The first trench may be etched to a depth of 1000-1200Å.

The hard mask film pattern is preferably removed by using a phosphoric acid solution by increasing 20-30% than the normal removal time.

The second trench may be formed using isotropic etching, and preferably, the second trench may be formed to have a diameter of 600-800 mm 3.

The method may further include performing FN cleaning for 250-300 seconds after the forming of the bulb type trench channel trench.

The FN cleaning may be performed by sequentially washing F using a first solution containing diluted hydrofluoric acid (HF), using N cleaning using a second solution including a mixture of ammonia (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ). Proceed to

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

2A through 10 are views illustrating a method of manufacturing a semiconductor device having a bulb type recess channel according to an exemplary embodiment of the present invention. 2B, 3B, and 4B are cross-sectional views of FIGS. 2A, 3A, and 4A taken along the line X-X '.

First, referring to FIGS. 2A and 2B, an etch mask layer 102 is formed on the semiconductor substrate 100 to act as a mask in an etching process for forming a neck-shaped upper end of a bulb type recess trench. do. The etching mask layer 102 may be formed to a thickness of 500-700 kPa using a high thermal oxide (HTO) or chemical vapor deposition (CVD).

Next, a photoresist is applied on the etch mask layer 102 and patterned by using a photolithography process to form a photoresist pattern 104 selectively exposing the surface of the etch mask layer 102. The photoresist pattern 104 may be formed in the form of a line crossing the region where the trench is to be formed. In addition, the photoresist pattern 104 may be formed in an island shape to selectively expose only the region where the trench is to be formed.

Subsequently, the etching mask layer 102 having the photoresist pattern 104 as a mask is etched to form an etching mask layer pattern 102 ′ exposing the semiconductor substrate 100.

3A and 3B, the first trench 106 may be formed by etching the semiconductor substrate 100 exposed by the photoresist pattern 104 and the etching mask layer pattern 102 ′ as a mask. Form. The first trench 106 corresponds to the neck portion of the bulb type recess channel trench. At this time, the first trench 106 is formed to have a suitable depth, for example, a depth of 1000-1200 mm in consideration of the size of the bulb to be formed later. The photoresist pattern 104 is stripped and removed. Here, the hard mask layer pattern 102 ′ may also be etched during the first etching.

4A and 4B, a buffer film 108 is formed on the semiconductor substrate 100 and the first trench 106. Subsequently, a hard mask film 110 filling the first trench 106 is formed on the buffer film 108. The buffer film 108 is formed of an oxide film having a thickness of approximately 50-150 GPa, and serves to relieve stress of the semiconductor substrate 100 due to the attraction of the hard mask film 110. In addition, the buffer layer 108 is deposited on the etch mask layer pattern 102 ′ to increase its thickness, and is then used as a barrier layer in an etching process for forming a bulb type trench channel trench. And the hard mask film 110 is formed to have a thickness of 600-700Å. The hard mask film 110 serves as a mask in an etching process for forming a device isolation film, and then serves as a polishing stop film in a subsequent planarization process.

Next, a photoresist is applied on the hard mask film 110, and a photoresist pattern 112 for selectively exposing the hard mask film 110 is formed to form an isolation region using photolithography. As shown in FIG. 4A, the active region of the semiconductor substrate 100 is blocked by the photoresist pattern 112, and the device isolation region is exposed.

Referring to FIG. 5, the hard mask layer pattern exposing the device isolation region of the semiconductor substrate 100 by selectively removing the hard mask layer 110 and the buffer layer 108 exposed by the photoresist pattern 112 as a mask. And a buffer film pattern 108 '. Subsequently, an etching process is performed on the exposed portion of the semiconductor substrate 100 using the hard mask layer pattern 110 ′ and the buffer layer pattern 108 ′ as an etch mask, for example, a predetermined depth, for example, 3000, in the semiconductor substrate 100. A device isolation trench 114 having a depth of -4000 Å is formed. In this case, since the first trench 106 is buried in the hard mask layer, the first trench 106 is not affected by the etching, thereby minimizing Si-attack.

Although not shown in the drawings, a sidewall oxide film, a liner nitride film, or a liner oxide film is formed in the isolation trench 114.

Referring to FIG. 6, a buried insulating film 116 is formed to fill the device isolation trench 114. The buried insulating film 116 may be formed of a high density plasma oxide (HDP) film having a thickness of 4000-5000 Å.

Referring to FIG. 7, a planarization process, for example, chemical mechanical polishing (CMP), is performed on a semiconductor substrate 100 including a buried insulating layer 116 to form an isolation layer 118. In this case, the device isolation layer 118 may be configured to proceed by setting a target such that the thickness of the hard mask layer pattern 110 ′ is about 450-600 μs. In this case, the planarization process may be performed using an etch back.

Referring to FIG. 8, the hard mask layer pattern 110 ′ is removed by performing a strip process on the semiconductor substrate. The strip process may be performed longer than the normal removal time to completely remove the hard mask film pattern 110 ′ embedded in the first trench 106. This strip process is preferably carried out using a phosphoric acid (H ₃ PO ₄ ) solution by 20-30% increase than the conventional removal time. The buffer layer pattern 108 ′ is not removed, and then serves as a barrier layer when forming trenches for forming bulb type recess channels.

Next, although not shown in the figure, a threshold voltage screen (Vt screen) oxide film to be used as a pad in the ion implantation process for adjusting the threshold voltage is formed on the surface of the active region, and the well and Channel ion implantation is performed. In this case, the threshold voltage screen oxide film may be replaced with a buffer film pattern.

Referring to FIG. 9, a second trench having a sphere shape on a lower end portion of the first trench 106 may be formed by the second etching using the buffer layer pattern 108 ′ remaining on the first trench 106 as a barrier layer. 120 to form a bulb type trench channel trench 122 including the first trench 106 and the second trench 120. Here, the second trench 120 is preferably formed to have a diameter of 600-800 mm from the bottom surface of the first trench 106. At this time, the etching process of forming the spherical second trench 120 is etched at the same speed in all directions to proceed to isotropic etching having a curved surface after etching.

Thereafter, the FN cleaning is performed for 250-300 seconds to remove the oxide film remaining in the trench 122 for the bulb type recess channel.

This FN cleaning is sequentially performed with F cleaning using a first solution containing diluted hydrofluoric acid (HF), N cleaning using a second solution including a mixture of ammonia (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ). It can be understood to proceed.

Referring to FIG. 10, a gate oxide layer 124 is formed on the exposed surface of the active region as a dielectric film having a thickness of approximately 30-50 kHz. Next, a gate stack 132 is formed on the gate oxide film 124.

Specifically, the polysilicon film 126 is deposited on the gate oxide film 124 with a thickness of 400-700 kPa, and the tungsten silicide film (WSix) 128 is formed to a thickness of 1000-1500 kPa through the deposition and heat treatment of the tungsten layer. do. Subsequently, a gate hard mask film 130 including a silicon nitride film is formed on the tungsten silicide film 128 to a thickness of 2000-2500 kPa. Next, the gate stack 132 is formed by performing a selective etching process for gate patterning.

As described above, according to the method of manufacturing a semiconductor device having a bulb type recess channel according to the present invention, a first trench corresponding to a neck portion of a bulb type trench channel trench is provided. By dispersing and rearranging the formation process prior to forming the device isolation layer, it is possible to minimize the loss of the device isolation layer and the silicon attack by the conventional first and second etchings. In addition, it is possible to minimize the loss of the device isolation film while increasing the margin of the remaining oxide film.

Claims (11)

Forming a first trench in the semiconductor substrate; Sequentially depositing a buffer layer and a hard mask layer filling the first trench on the semiconductor substrate; Patterning the hard mask layer to form a hard mask layer pattern exposing the device isolation region of the semiconductor substrate; Forming a device isolation trench in the semiconductor substrate using the hard mask layer pattern as a mask; Forming a device isolation film to fill the device isolation trench; Removing the hard mask layer pattern; Etching the buffer layer using an etch barrier layer to form a spherical second trench in the lower end of the first trench to form a bulb type trench channel trench formed of the first trench and the second trench; And And forming a gate stack overlapping the trench of the bulb type recess channel. The method of claim 1, And a buffer type recess channel, wherein the buffer layer comprises an oxide layer. The method of claim 1, And the hard mask film comprises a nitride film. The method of claim 1, wherein forming a first trench comprises: Forming an etching mask layer on the semiconductor substrate; Forming a photoresist pattern exposing a first trench formation region on the etch mask layer; Etching the hard mask layer having the photoresist pattern as a mask to form an etching mask layer pattern; And forming a first trench in the semiconductor substrate using the etch mask layer pattern as a mask. The method of claim 4, wherein The etching mask layer may include an oxide film formed using a thermal oxide film (HTO) or chemical vapor deposition (CVD). The method of claim 1, And the first trenches are etched to a depth of 1000-1200 microns. The method of claim 1, The hard mask film pattern is a semiconductor device forming method comprising a bulb type recess channel, characterized in that for removing 20-30% increase than the normal removal time using a phosphoric acid solution. The method of claim 1, And the second trench is formed using an isotropic etching process. The method of claim 1, And the second trench is formed to have a diameter of 600-800 Å. The method of claim 1, And performing a FN cleaning for 250-300 seconds after forming the trench for trenching the bulb type recess channel. The method of claim 10, The FN cleaning may be performed by sequentially washing F using a first solution containing diluted hydrofluoric acid (HF), using N cleaning using a second solution including a mixture of ammonia (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ). A method of forming a semiconductor device comprising a bulb channel recess channel, characterized in that proceeding to.

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