KR100909635B1 - Transistor Formation Method of Semiconductor Device - Google Patents

Abstract

A method of forming a transistor of a semiconductor device of the present invention comprises the steps of: forming an etch stop layer pattern on a semiconductor substrate; Forming a trench in the semiconductor substrate at a position spaced a predetermined distance from one side of the etch stop layer pattern; Forming a buried insulating film filling the trench and the etch stop film pattern; Etching the buried insulating layer to expose the etch stop layer pattern and a portion of the surface of the semiconductor substrate; Forming a semiconductor layer filling the exposed etch stop layer pattern; Forming an isolation layer to planarize the semiconductor layer and the buried insulating film to separate the semiconductor layer; Forming a mask layer pattern on the semiconductor layer and the isolation layer; Etching the semiconductor layer using the mask layer pattern as an etch mask to form a recess trench; Removing the etch stop layer pattern in the recess trench; And forming a gate stack overlapping the recess trench.

Recess trench, etch stop, recess trench depth

Description

Method for fabricating transistor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a transistor of a semiconductor device capable of uniformly forming a depth of a recess trench and maintaining a cell threshold voltage uniformly.

As the degree of integration of semiconductor devices increases, the design rules of the devices also decrease. As the design rule decreases, the size of the transistor is reduced, and accordingly, the length of a channel disposed between the source and the drain of the transistor is also shortened. In the case of a general transistor, a transistor having a planar typed channel in which electrons flow along a surface of the semiconductor substrate while a gate stack is formed on the semiconductor substrate is applied.

1 illustrates a transistor having a general planar channel.

Referring to FIG. 1, a transistor having a planar channel includes a gate insulating layer 110, a conductive layer 115, a metal layer 120, and a semiconductor layer 100 on an active region defined by an isolation layer 105. The gate stack 130 having a structure in which the hard mask layers 125 are stacked is disposed. An impurity region 135 including a source and a drain region is disposed in the semiconductor substrate 100 between the gate stack 130. The channel a of the transistor of this structure is formed along the impurity region 135, and the length of the channel a is determined along the width of the gate stack.

However, as the device is highly integrated, the size of the transistors disposed in the device is reduced, and accordingly, the channel length of the transistor is also shortened. If the channel length of the transistor is shortened, a short channel effect occurs that causes a decrease in threshold voltage, an increase in leakage current, and a decrease in refresh characteristics. When such a short channel effect occurs, punch-through may occur seriously between the source and the drain of the transistor, which is recognized as a major cause of device malfunction. In particular, as the channel length of the transistor is shortened, the threshold voltage control margin is rapidly weakened, and thus the threshold voltage may be changed. As such, when the threshold voltage is changed, the operation of the semiconductor device may not be stably performed, and thus the device characteristics may be degraded. Accordingly, there is a need for a method of forming a transistor having a structure that further extends a channel length for a limited gate line width.

In an embodiment, a method of forming a transistor of a semiconductor device may include forming an etch stop layer pattern on a semiconductor substrate; Forming a trench in the semiconductor substrate at a position spaced a predetermined distance from one side of the etch stop layer pattern; Forming a buried insulating film filling the trench and the etch stop film pattern; Etching the buried insulating layer to expose the etch stop layer pattern and a portion of a surface of the semiconductor substrate; Forming a semiconductor layer to fill the exposed etch stop layer pattern; Forming an isolation layer to planarize the semiconductor layer and the buried insulating layer to separate the semiconductor layer; Forming a mask layer pattern on the semiconductor layer and the device isolation layer; Etching the semiconductor layer using the mask layer pattern as an etch mask to form a recess trench; Removing an etch stop layer pattern in the recess trench; And forming a gate stack overlapping the recess trench.

In the present invention, the etch stop layer pattern may be formed of a material having a different etching selectivity from the semiconductor layer. The etch stop layer pattern may be formed to have a thickness of about 30 kPa to about 300 kPa including a nitride film.

The semiconductor layer may be formed to include a polysilicon layer or an amorphous silicon (amorphous-Si) layer, and may be formed to a target depth thickness of the recess trench by a chemical vapor deposition method or an epitaxial growth method. In this case, the semiconductor layer is preferably formed to have a thickness of 1000 GPa to 1500 GPa when the target depth of the recess trench is 1000 GPa to 1500 GPa.

When the etch stop layer pattern is formed of a nitride layer, it is preferable to remove the phosphate (H ₃ PO ₄ ) solution.

In another embodiment, a method of forming a transistor of a semiconductor device may include forming an etch stop layer pattern on a semiconductor substrate; Forming a semiconductor layer on the etch stop layer pattern and the semiconductor substrate; Forming a mask layer pattern on the semiconductor layer; Etching the semiconductor layer and the semiconductor substrate using the mask layer pattern as an etch mask to form a trench in the semiconductor substrate; Forming an isolation layer filling all of the trenches; Forming a sidewall oxide film and a liner film on the exposed surface of the trench; Selectively etching the semiconductor layer to form a recess trench for exposing the etch stop layer pattern; Removing the etch stop layer pattern in the recess trench; And forming a gate stack overlapping the recess trench.

The etch stop layer pattern may be formed including a PSG (Phosphorus silicate glass) film or a BPSG (Boron phosphorus silicate glass) film.

The etch stop layer pattern may be removed with a hydrofluoric acid (HF) solution or a BOE solution.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

2 to 13 are views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, an etch stop layer 205 is deposited on the semiconductor substrate 200. The etch stop layer 205 serves as a barrier to prevent the semiconductor substrate 200 from being excessively etched in an etching process for forming a recess trench. The etch stop layer 205 may include a nitride layer. In this case, the etch stop layer 205 may have a thickness, for example, 30-min, in which a dip time is minimized in the process of forming the recess trench and then removing it using the wet etching solution. It is formed to a thickness of 300Å. Next, a photoresist layer is applied and patterned on the etch stop layer 205 to form a photoresist layer pattern 210 that defines an area in which the recess trench is to be formed.

Referring to FIG. 3, the etch stop layer 205 is etched using the photoresist layer pattern 210 as an etch mask to form an etch stop layer pattern 215. The portion blocked by the etch stop layer pattern 215 defines a region where a recess trench is to be formed later. The portion blocked by the etch stop layer pattern 215 serves as a barrier to prevent over-etching of the semiconductor substrate 200 in an etching process for forming a subsequent recess trench. Next, the photoresist film pattern 210 is removed using an ashing process.

Referring to FIG. 4, the first mask layer pattern 220 exposing a predetermined surface of the semiconductor substrate 200 is formed while blocking an area where the etch stop layer pattern 215 is formed on the semiconductor substrate 200. The first mask layer pattern 220 may be formed as a photoresist layer. The region exposed by the first mask layer pattern 220 is a region where the device isolation layer is to be formed later.

Referring to FIG. 5, the trench 225 is formed by etching the exposed portion of the semiconductor substrate 200 by a predetermined depth using the first mask layer pattern 220 as an etching mask. The trench 225 may be formed at a depth of 500 kV to 1500 kV from the surface of the semiconductor substrate 200. The first mask layer pattern 220 is removed.

Referring to FIG. 6, a buried insulating layer 230 is formed to fill the trench 225 and the etch stop layer pattern 215 formed in the semiconductor substrate 200. Specifically, although not shown, a sidewall oxide film, a liner nitride film, and a liner oxide film are formed on the exposed surface of the trench 225. Next, the buried insulating film 230 is formed on the semiconductor substrate 200 to fill the trench 225 and the etch stop film pattern 215. The buried insulating film 230 may be formed using a chemical vapor deposition (CVD) method or a high density plasma (HDP) process. The buried insulating film 230 formed on the trench 225 and the etch stop film pattern 215 may be formed of an oxide film. In this case, the buried insulating film 230 is preferably deposited to a thickness of 2500 to 5000 도록 so that the device isolation film to be formed on the semiconductor substrate 200 after the device isolation process has a height of 1500 Å to 3000 Å. Next, a second mask layer pattern 235 is formed to selectively expose the buried insulating layer 230 in the region where the etch stop layer pattern 215 is formed.

Referring to FIG. 7, an opening portion 240 exposing the etch stop layer pattern 215 is formed by etching the exposed portion of the buried insulating layer 230 by an etching process using the second mask layer pattern 235 as a mask. . The etching process may be performed until the surface of the semiconductor substrate 200 in the region where the etch stop layer pattern 215 is not formed in the opening 240 is exposed. The region in which the semiconductor substrate 200 and the etch stop layer pattern 215 are exposed by the etching process is disposed after the active region, and the region that is blocked by the second mask layer pattern 235 is the device isolation region thereafter. Becomes The second mask layer pattern 235 is removed using an ashing process.

Referring to FIG. 8, the opening 240 is buried using the semiconductor layer 245. The semiconductor layer 245 serves to control the depth of the recess trench to be formed later. The semiconductor layer 245 may include a polysilicon layer or an amorphous silicon (amorphous-Si) layer. The semiconductor layer 245 may be deposited using a low pressure chemical vapor deposition (LPCVD) method or may be formed using an epitaxial growth method. At this time, the semiconductor layer 245 filling the opening 240 is preferably formed to a thickness of 1000-1500Å to control the depth of the recess trench to be formed later.

Referring to FIG. 9, a planarization process is performed on the semiconductor layer 245 and the buried insulating layer 230 (see FIG. 8) to form an isolation layer 250 that separates the isolation region from the active region. The planarization process may be performed using an etch back or chemical mechanical polishing (CMP) method.

Referring to FIG. 10, a third mask layer pattern 255 may be formed to selectively expose the semiconductor layer 245 in the region where the etch stop layer pattern 215 is formed. The third mask layer pattern 255 blocks the semiconductor layer 245 in a portion where the device isolation layer 250 and the etch stop layer pattern 215 are not disposed. Next, a recess trench 260 exposing the etch stop layer pattern 215 is formed by etching the semiconductor layer 245 using the third mask layer pattern 255 as an etch mask. The recess trench 260 is formed on the target region to form the recess trench 260 as the formation and etching of the semiconductor layer 245 is performed while the etch stop layer pattern 215 is formed on the semiconductor substrate 200. Can be aligned correctly. In addition, instead of designating the depth of the recess trench 260 later, it is possible to prevent the depth distribution of the trench from being formed by adjusting the depth in advance.

Referring to FIG. 11, after removing the third mask layer pattern 255, the etch stop layer pattern 215 in the recess trench 260 is removed. In detail, the semiconductor substrate 200 is immersed in a wet etching solution. The wet etching solution may be used as a phosphoric acid (H ₃ PO ₄ ) solution when the etching stop layer pattern 215 is formed of a nitride film. In this case, the etch stop layer pattern 215 is formed to a thickness that minimizes the time to be immersed in the wet etching solution, for example, a thickness of 30 to 300 Å so that the etch stop layer pattern 215 is affected by the wet etching solution of the semiconductor substrate 200 and the device isolation layer 250. Can be minimized. The etching stop layer pattern 215 is removed by the wet etching process to form a recess trench 260 having a depth of 1000 to 1500 mW on the semiconductor substrate 200.

Referring to FIG. 12, a gate forming material is deposited on the semiconductor substrate 200 on which the recess trench 260 is formed. In detail, the semiconductor substrate 200 on which the recess trench 260 is formed may be cleaned to remove residues remaining on the recess trench 260 and the device isolation layer 250. Next, a gate forming material including the gate insulating film 265, the gate conductive film 270, the metal film 275, and the hard mask film 280 is sequentially formed.

Referring to FIG. 13, the hard mask layer 280, the metal layer 275, the gate conductive layer 270, and the gate insulating layer 265 are patterned to form a gate stack 310. Specifically, a gate mask (not shown) defining a region in which the gate stack is to be formed is formed on the hard mask layer 280. Next, the hard mask layer 280 is etched using the gate mask as an etch mask to form a hard mask layer pattern 290. The gate mask is then removed using an ashing process. Next, the gate stack 310 is formed by etching the metal layer 275 to the gate insulating layer 265 using the hard mask layer pattern 290 as an etching mask. The gate stack 310 may include a gate insulating layer pattern 305, a gate conductive layer pattern 300, a metal layer pattern 295, and a hard mask layer pattern 290.

In the method of fabricating a transistor of a semiconductor device according to an embodiment of the present invention, the recess trench is positioned in advance using an etch stop layer pattern, and thereafter, a device isolation layer and a recess trench are formed to form a uniform trench throughout the wafer. It is possible to form a gate stack having a width and a depth. Accordingly, when the width and depth of the recess trench are non-uniform, it is possible to prevent the phenomenon that the threshold voltage is unevenly distributed.

14 to 23 illustrate a method of forming a transistor of a semiconductor device in accordance with another embodiment of the present invention. FIG. 24 is a table illustrating etching rates of oxidized thin films.

Referring to FIG. 14, an etch stop layer 405 is deposited on the semiconductor substrate 400. The etch stop layer 405 serves as a barrier to prevent excessive etching of the semiconductor substrate 400 in an etching process for forming a recess trench. The etch stop layer 405 may be formed of a Phosphorus silicate glass (PSG) film or a Boron phosphorus silicate glass (BPSG) film. In this case, the etch stop layer 405 is then formed to form a recess trench, the thickness to minimize the dip time in the wet etching solution in the process of removing using a wet etching solution (for example, 30Å) It is formed to a thickness of 300 Å.

Referring to FIG. 15, an etch stop layer (refer to FIG. 14 and 405) is patterned to form an etch stop layer pattern 410 defining a region in which a recess trench is to be formed. Next, a semiconductor layer 415 is formed on the etch stop layer pattern 410 and the semiconductor substrate 400. The semiconductor layer 415 serves to control the depth of the recess trench to be formed later. The semiconductor layer 415 may be formed of a silicon film. In this case, the semiconductor layer 415 may be deposited using a low pressure chemical vapor deposition (LPCVD) method or may be formed using an epitaxial growth method. In this case, the semiconductor layer 415 is formed to have a thickness of 1000 Å to 1500 Å in order to control the depth of the recess trench.

Referring to FIG. 16, a first mask layer pattern 430 is formed on the semiconductor layer 415. The first mask layer pattern 430 selectively exposes the semiconductor layer 415 in the region where the device isolation layer is to be formed. The first mask layer pattern 430 may include the pad oxide layer pattern 420 and the pad nitride layer pattern 425.

Referring to FIG. 17, the exposed portion of the semiconductor layer 415 is etched using the first mask layer pattern 430 as an etch mask to expose a portion of the surface of the semiconductor substrate 400. Subsequently, the exposed semiconductor substrate 400 is etched to form trenches 435 having a predetermined depth. Next, a sidewall oxide film 440 and a liner film 445 are formed on the exposed surface of the trench 435 to prevent leakage current and to improve refresh characteristics. The liner layer 445 may include a nitride layer or an oxide layer.

Referring to FIG. 18, an isolation layer 450 filling the trench 435 is formed. Specifically, the buried insulating film is formed on the semiconductor substrate 400 on which the trench 435 is formed to fill both the trench 435 and the first mask layer pattern (see FIG. 17 and 430). Next, a planarization process is performed until the surface of the first mask layer pattern 430 is exposed on the buried insulating layer to separate the active region and the device isolation region. The planarization process is carried out by chemical mechanical polishing (CMP) method. Next, the pad nitride layer pattern 425 of the exposed first mask layer pattern 430 is removed using a phosphoric acid (H ₃ PO ₄ ) solution. In addition, the pad nitride layer pattern 425 is removed to planarize the device isolation layer 450 protruding from the height of the semiconductor layer 415.

Referring to FIG. 19, a second mask layer pattern 455 may be formed on the device isolation layer 450 to selectively expose the pad oxide layer pattern 420 in the region where the etch stop layer pattern 410 is formed. The second mask layer pattern 455 may be formed to have a thickness of 500 to 1500 mV in consideration of the thickness of the semiconductor layer 415.

Referring to FIG. 20, a recess trench 460 exposing the etch stop layer pattern 410 by etching the pad oxide layer pattern 420 and the semiconductor layer 415 using the second mask layer pattern 455 as an etch mask is shown. Form. Here, the second mask layer pattern 455 is aligned with the etch stop layer pattern 410 so as to minimize misalignment with the etch stop layer pattern 410. Next, the pad oxide film pattern 420 remaining on the second mask film pattern 455 and the semiconductor layer 415 is removed.

Referring to FIG. 21, the etch stop layer pattern 410 in the recess trench 460 is removed. In detail, the semiconductor substrate 400 is immersed in a wet etching solution. In the wet etching solution, when the etch stop layer pattern 410 is formed of a PSG film or a BPSG film, a hydrofluoric acid (HF) solution or a buffered oxidant etchant (BOE) solution is used. As shown in FIG. 24, the PSG film or the BPSG film has a higher etching rate in a hydrofluoric acid solution or a BOE solution than other oxide materials such as a thermal oxide film or an oxide film using a high density plasma process. In addition, the etch stop layer pattern 410 is formed to a thickness that minimizes the time to be immersed in the wet etching solution, for example, a thickness of 30 kPa to 300 kPa. Accordingly, the device isolation layer 450 and the liner layer 445 may be prevented from being lost by the wet etching solution. The etching stop layer pattern 410 is removed by the wet etching process, and thus, a recess trench 460 having a depth of 1000 Å to 1500 Å is formed on the semiconductor substrate 400. The recess trench 460 may be formed to have a uniform width and depth throughout the wafer by presetting the position and depth by the etch stop layer pattern 410 and the semiconductor layer 415. Accordingly, in the case where the depth of the recess trench 460 is nonuniform, it is possible to fundamentally prevent the dispersion of the cell threshold voltage.

Referring to FIG. 22, a gate forming material is deposited on the semiconductor substrate 400 on which the recess trench 460 is formed. Specifically, cleaning is performed on the semiconductor substrate 400 on which the recess trench 460 is formed to remove residues remaining on the recess trench 460 and the device isolation layer 450 while each process is performed. Next, a gate forming material including a gate insulating film 465, a gate conductive film 470, a metal film 475, and a hard mask film 480 is sequentially formed on the semiconductor substrate 400.

Referring to FIG. 23, the hard mask film 480, the metal film 475, the gate conductive film 470, and the gate insulating film 465 are patterned to form a gate stack 505. Specifically, a resist film pattern (not shown) defining a region where a gate stack is to be formed is formed on the hard mask film 480. Next, the hard mask film 480 is etched using the resist film pattern as an etch mask to form a hard mask film pattern 485. Next, the resist film pattern is removed using an ashing process. Next, the gate stack 505 is formed by an etching process using the hard mask layer pattern 485 as an etching mask. The gate stack 505 may include a gate insulating film pattern 500, a gate conductive film pattern 495, a metal film pattern 490, and a hard mask film pattern 485.

According to another exemplary embodiment of the present inventive concept, a method of manufacturing a semiconductor device having a recess gate may include setting a recess trench in advance using an etch stop layer pattern, and then using a hard mask layer to increase the depth of the recess trench. By specifying in advance, it is possible to form a gate stack having a uniform width and depth throughout the wafer. Accordingly, when the width and depth of the recess trench are non-uniform, it is possible to prevent the phenomenon that the threshold voltage is unevenly distributed. Also, by forming the etch stop film pattern as the PSG film or the BPSG film, it is possible to prevent loss of the device isolation film and the liner film.

1 illustrates a transistor having a general planar channel.

2 to 13 are views illustrating a method of forming a transistor of a semiconductor device according to an embodiment of the present invention.

14 to 23 are views illustrating a method of forming a transistor of a semiconductor device according to another embodiment of the present invention.

24 is a table showing the etching rate of the oxidized thin film.

Claims (15)

Forming an etch stop layer pattern on the semiconductor substrate; Forming a trench in the semiconductor substrate at a position spaced a predetermined distance from one side of the etch stop layer pattern; Forming a buried insulating film filling the trench and the etch stop film pattern; Etching the buried insulating layer to expose the etch stop layer pattern and a portion of a surface of the semiconductor substrate; Forming a semiconductor layer to fill the exposed etch stop layer pattern; Forming an isolation layer to planarize the semiconductor layer and the buried insulating layer to separate the semiconductor layer; Forming a mask layer pattern on the semiconductor layer and the device isolation layer; Etching the semiconductor layer using the mask layer pattern as an etch mask to form a recess trench; Removing an etch stop layer pattern in the recess trench; And Forming a gate stack overlapping the recess trench. The method of claim 1, And the etching stop layer pattern is formed of a material having a different etching selectivity from the semiconductor layer. The method of claim 1, The etching stop layer pattern is a transistor forming method of a semiconductor device to form a thickness of 30 ~ 300Å including a nitride film. The method of claim 1, And the semiconductor layer comprises a polysilicon film or an amorphous silicon (amorphous-Si) film. The method of claim 1, And the semiconductor layer is formed by a chemical vapor deposition method or an epitaxial growth method. The method of claim 1, And the semiconductor layer is formed to a target depth thickness of the recess trench. The method of claim 1, And wherein the semiconductor layer is formed to a thickness of 1000 kW to 1500 kW when the target depth of the recess trench is 1000 kW to 1500 kW. The method of claim 1, The etching stop layer pattern is a transistor forming method of a semiconductor device which is removed by a phosphoric acid (H ₃ PO ₄ ) solution when formed as a nitride film. Forming an etch stop layer pattern on the semiconductor substrate; Forming a semiconductor layer on the etch stop layer pattern and the semiconductor substrate; Forming a mask layer pattern on the semiconductor layer; Etching the semiconductor layer and the semiconductor substrate using the mask layer pattern as an etch mask to form a trench in the semiconductor substrate; Forming an isolation layer filling all of the trenches; Forming a sidewall oxide film and a liner film on the exposed surface of the trench; Selectively etching the semiconductor layer to form a recess trench for exposing the etch stop layer pattern; Removing the etch stop layer pattern in the recess trench; And Forming a gate stack overlapping the recess trench. The method of claim 9, The etch stop layer pattern may include a phosphorus silicate glass (PSG) film or a boron phosphorus silicate glass (BPSG) film. The method of claim 9, And the semiconductor layer comprises a silicon film. The method of claim 9, And the semiconductor layer is formed to a target depth thickness of the recess trench. The method of claim 9, And wherein the semiconductor layer is formed to a thickness of 1000 kW to 1500 kW when the target depth of the recess trench is 1000 kW to 1500 kW. The method of claim 9, And the liner layer includes a nitride layer or an oxide layer. The method of claim 9, The etching stop layer pattern is a transistor forming method of a semiconductor device to remove with a hydrofluoric acid (HF) solution or BOE solution.

Images