KR20080002612A - Method for manufacturing semiconductor device having bulb-type recessed channel - Google Patents

Abstract

A method for fabricating a semiconductor device having bulb-type recess channel is provided to easily adjust the profile of a hard mask layer by forming a hard mask layer made of a silicon nitride layer or a silicon oxynitride layer. An isolation layer for defining an active region is formed on a semiconductor substrate(100). A hard mask layer having a higher etch selectivity than that of an oxide layer is formed on the semiconductor substrate. The active region of the semiconductor substrate is selectively exposed wherein a hard mask layer pattern having a profile of a slope type is formed. A first trench(114) is formed in the semiconductor substrate by using the hard mask layer pattern as an etch mask. A barrier layer is formed on the sidewall of the first trench. The hard mask layer pattern is removed. A second trench(120) of a spherical type is formed under the first trench by using the barrier layer as an etch mask to form a bulb-type trench for a recess channel such that the bulb-type trench is composed of the first and second trenches. A gate stack(132) is formed which overlaps the bulb-type trench for the recess channel. The hard mask layer can be made of a stack structure composed of an oxide layer/a silicon nitride layer or an oxide layer/a silicon oxynitride layer.

Description

Method for manufacturing semiconductor device having bulb type recess channel {Method for manufacturing semiconductor device having bulb-type recessed channel}

1 is a schematic view of a semiconductor device having a bulb type recess channel according to the prior art.

2 and 3 are diagrams for explaining a problem occurring in the bulb type recess channel according to the prior art.

4 to 14 illustrate a method of manufacturing a semiconductor device having a bulb type recess channel according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 112 hard mask film

114: first trench 120: second trench

132: gate stack

The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a bulb type recess channel.

Recently, as the degree of integration of integrated circuit semiconductor devices has increased and design rules have sharply decreased, it is increasingly difficult to secure stable operation of transistors. In particular, as the design rules of semiconductor devices are reduced to 70 nm or less, the size of transistors is also reduced, leading to a threshold of cell threshold voltage (Vt) and refresh characteristics. In particular, high-speed DDR2 (Double Data Rate) DRAM products, which are currently commercially available, have dramatically reduced data retention time by setting test conditions at high temperatures compared to conventional DDR DRAM products.

Accordingly, various methods for securing the effective channel length without increasing the design rule have been studied in various ways. As a method of securing the effective channel length as described above, the length of the channel is further extended for the limited gate line width. Attempts have been made to further extend the length of the channels.

1 is a schematic view of a semiconductor device having a bulb type recess channel according to the prior art. 2 and 3 are diagrams for explaining a problem occurring in a bulb type recess channel according to the related art.

Referring to FIG. 1, in a semiconductor device having a bulb type recess channel, an upper end portion 20a has a neck shape in a semiconductor substrate 10 in which an active region is set by an isolation layer 12, and a lower end portion ( A bulb type recess channel 20 having a sphere shape 20b is disposed. The gate stack 18 including the gate insulating layer 14 and the gate electrode 16 overlaps the bulb type recess channel 20.

The bulb type recess channel 20 is implemented by dividing the etching process in two stages. This two-step etching increases the effective channel length by forming a sphere in the shape of a sphere while keeping the critical dimension (CD) of the upper portion the same. The increase of the effective channel increases the cell threshold voltage, thereby adjusting the appropriate cell threshold voltage required for normal cell transistor operation to the dose amount of the cell channel ion. When the cell threshold voltage is adjusted by the dose of cell channel ions, there is an electric field reduction effect at the cell junction, thereby improving the refresh characteristics.

Meanwhile, in the etching process for implementing the bulb type recess channel 20, a hard mask layer (not shown) having a structure in which an oxide layer and a polysilicon layer are stacked is used. However, when the etching process for forming the recess channel using the hard mask film of this type is performed, the upper end of the neck shape of the recess channel 20 due to the insufficient etching selectivity margin of the polycrystalline silicon film and the oxide film ( It is difficult to control the critical dimension (CD) in the etching process to form 20a). For this reason, referring to FIG. 2, in the case of the gate 30 passing through the adjacent active region, an attack A may occur in the long axis direction of the active region as the critical dimension increases. In addition, due to the lack of selectivity margin between the polycrystalline silicon film and the oxide film, the oxide film 40 of the hard mask film remains in a shoulder shape at the neck-shaped upper end portion 20a of the recess channel 20. In the etching process for forming the sphere-shaped lower end portion 20b of the channel 20, as shown in FIG. 3, the silicon (Si) at the corner of the neck-shaped upper end portion 20a is attacked. 40 is generated.

As described above, when an attack occurs on silicon, the leakage current may increase, which may affect device characteristics. Accordingly, there is a demand for a hard mask film having excellent selectivity to silicon and oxide films.

The technical problem to be achieved by the present invention, by controlling the profile of the hard mask film can prevent the silicon attack of the active region by securing a critical critical dimension of the upper end of the trench, and with the bulb type of which can prevent the attack on the upper portion of the trench There is provided a method of manufacturing a semiconductor device having a recess channel.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a bulb type recess channel according to the present invention, forming a device isolation film for setting an active region on the semiconductor substrate; Forming a hard mask layer having a higher etching selectivity than the oxide layer on the semiconductor substrate; Selectively exposing an active region of the semiconductor substrate to form a hard mask layer pattern having a slope profile; Forming a first trench in the semiconductor substrate using the hard mask layer pattern as an etch mask; Forming a barrier layer on the sidewalls of the first trenches; Removing the hard mask layer pattern; Forming a spherical second trench at a lower end of the first trench by using the barrier layer as an etch mask to form a bulb channel trench formed of the first trench and the second trench; And forming a gate stack overlapping the bulb type trench channel trench.

In the present invention, it is preferable that the hard mask layer has a structure in which an oxide layer and a silicon nitride layer (Si _X N _Y ) or an oxide layer and a silicon oxynitride layer (SION) are stacked.

At this time, the oxide film is formed to a thickness of 200-300 kPa, and the silicon nitride film (Si _X N _Y ) or the silicon oxy nitride film (SION) is preferably formed to a thickness of 300-500 kPa.

The first trench may be formed to a depth of 1000-1500Å.

The forming of the barrier film may include depositing an oxide film on the first trench; And removing an oxide layer on an upper portion of the hard mask layer and a bottom surface of the first trench to leave a barrier layer on the sidewalls of the first trench, and the barrier layer may be formed using anisotropic etching.

The hard mask film pattern may be removed using a phosphoric acid (H ₃ PO ₄ ) solution.

The second trench has a diameter of 500-900 mm 3 and is preferably formed using isotropic etching.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

4 to 14 illustrate a method of manufacturing a semiconductor device having a bulb type recess channel according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a trench isolation layer 102 is formed on the semiconductor substrate 100 to set an active region. Specifically, the pad oxide film and the pad nitride film are sequentially deposited and then selectively removed to expose the device isolation region of the semiconductor substrate 100. Subsequently, the device isolation region of the exposed semiconductor substrate 100 is etched to form a trench having a predetermined depth. Next, a buried insulating film is formed on the entire surface to fill the trench, and after the planarization process is performed, the trench isolation film 102 is formed by removing the pad nitride film and the pad oxide film.

Next, a threshold voltage screen (Vt screen) oxide film 104 to be used as a pad in the ion implantation process for adjusting the threshold voltage on the surface of the active region is formed by an oxidation process, and ion implantation is performed in the cell region and the ferry region. do.

Referring to FIG. 5, an oxide film 106 is formed on a semiconductor substrate 100, and then a hard mask film 108 having an etching selectivity higher than that of the oxide film 106 is formed. The hard mask layer 108 is then used as an etching mask in the etching process for forming the upper trench of the bulb type recess channel, and it is preferable to form the film to facilitate stable profile control. In this case, the hard mask film 108 may include a material having an etching selectivity with respect to an oxide film or a silicon oxide film, for example, a silicon nitride film (Si _X N _Y ) or a structure in which an oxide film and a silicon oxy nitride film (SION) are stacked. Can be formed. The oxide film 106 may include a high thermal oxide film (HTO) and may be formed to a thickness of 300 to 500 kPa, and the silicon nitride film (Si _X N _Y ) or the silicon oxy nitride film (SION) may be 300-. It can be formed with a thickness of 500 kPa.

At this time, the hard mask film 108 has a threshold voltage screen oxide film 104 disposed on the active region as a lower film, and a silicon nitride film (Si _X N _Y ) or a silicon oxy nitride film (SION) on the screen oxide film 104. ) May be deposited to a thickness of 500-700 mm 3. In this case, the oxide film 106 can be omitted.

Referring to FIG. 6, a photoresist is applied on the hard mask film 108, and a photoresist pattern 110 is formed to selectively expose the hard mask film 108 by using a photolithography process.

Referring to FIG. 7, the hard mask film 108 exposed through the photoresist pattern 110 as an etch mask is etched to form a hard mask film pattern 112 for selectively exposing an active region of the semiconductor substrate 100. . The hard mask film pattern 112 may include a structure in which the hard mask film 108 'and the oxide film 106' are stacked.

At this time, the hard mask film pattern 112 is etched to have a slope for controlling the critical dimension (CD) of the neck-shaped trench to be formed in a subsequent process.

Referring to FIG. 8, a first trench 114 is formed by etching the active region of the semiconductor substrate 100 exposed by the hard mask layer pattern 112 as an etching mask. The first trench 114 corresponds to a neck portion of a bulb type recess channel trench. At this time, the first trench 114 is formed to have a suitable depth, for example, 1000-1500Å in consideration of the size of the bulb to be formed later. The photoresist pattern 110 is stripped and removed. During the first etching process, the exposed hard mask layer 108 ′ may be etched to become thinner.

Referring to FIG. 9, an oxide film 116 is formed on the hard mask pattern 112 and in the first trench 114 to have a thickness of 40 to 70 μm. The oxide layer 116 may be a semiconductor substrate that may be caused by excessive etching of the side surface of the first trench 114 in an etching process for forming a sphere portion of a bulb channel trench. 100) prevents damage.

Referring to FIG. 10, the barrier layer 118 is formed on the sidewalls of the first trenches 114 by selectively removing the oxide layer 116.

Specifically, a BT (Black Through) etching process (or anisotropic etching) is applied to form a bulb type trench channel trench. By the BT (Black Through) etching process, the oxide layer 116 covering the upper surface of the hard mask layer pattern 112 and the bottom surface of the first trench 114 is removed to remove the semiconductor substrate on the bottom surface of the first trench 114. The active area of 100 is exposed. At this time, the oxide film on the sidewall of the first trench 114 is not removed by the BT (Black Through) etching process, and the barrier film 118 is formed.

The barrier layer 118 prevents excessive side etching of the sidewalls of the first trenches 114 during the etching process to form a spherical trench lower end portion, thereby exposing silicon (Si) of the semiconductor substrate 100. It prevents it from becoming.

Referring to FIG. 11, a strip process is performed on the semiconductor substrate 100 to remove the silicon nitride film Si _X N _Y or the silicon oxy nitride film SION remaining on the oxide film 106 ′. This stripping process is removed using a solution of phosphoric acid (H ₃ PO ₄ ). At this time, a portion of the active region of the exposed semiconductor substrate 100 on the bottom surface of the first trench 114 may be damaged by the phosphoric acid (H ₃ PO ₄ ) solution during the strip process, but subsequent spheres ) It does not affect the process because it is removed during the etching process to form the bottom of trench.

Referring to FIG. 12, a second etching process is performed using the barrier layer 118 as an etching mask to form a second trench 120 having a sphere shape in the lower end portion of the first trench 114, thereby forming the first trench ( A bulb-type recess channel trench 122 consisting of a 114 and a spherical second trench 120 is formed. Here, the spherical second trench 122 is preferably formed to have a diameter of 500-900 mm from the bottom surface of the first trench 114. The etching process of forming the spherical second trench 120 may be etched at the same speed in all directions to proceed to isotropic etching having a curved surface after etching.

In this case, the barrier layer 118 prevents damage to the semiconductor substrate 120 that may be caused by excessive etching of the side surface of the trench type trench channel 122 for the isotropic etching.

Referring to FIG. 13, FN or BFN cleaning is performed on the semiconductor substrate 100 for 250-350 seconds.

Here, BFN cleaning is B cleaning using a first solution of sulfuric acid (H ₂ O ₄ ) and fruit water (H ₂ O ₂ ), F cleaning using a second solution containing dilute hydrofluoric acid (HF), ammonia ( N cleaning using a third solution containing a mixture of NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) is performed sequentially, and FN cleaning is performed by using F solution using a solution containing diluted hydrofluoric acid (HF), ammonia ( N-washing using a solution containing a mixture of NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) is carried out sequentially. The barrier layer 118 and the impurities remaining in the sidewall portion of the trench channel trench 122 of the bulb type can be removed.

Referring to FIG. 14, although not shown in the drawing, a threshold voltage screen (Vt screen) oxide film to be used as a pad in an ion implantation process for adjusting the threshold voltage is formed on the surface of the active region by oxidation, and Well and channel ion implantation is performed. Thereafter, the screen oxide film and the like are removed, and the gate oxide film 124 is formed as a dielectric film having a thickness of approximately 30-50 kHz on the exposed active region surface.

Next, a gate stack 132 is formed on the gate oxide film 124.

Specifically, the polysilicon film 126 is deposited on the gate oxide film 124 to a thickness of 600-800 kPa, and the tungsten silicide film (WSix) 128 is formed to a thickness of 1000-1500 kPa through the deposition and heat treatment of the tungsten layer. do. Subsequently, a gate hard mask film 130 including a silicon nitride film is formed on the tungsten silicide film 128 to a thickness of 2000-2500 kPa. Next, the gate stack 132 is formed by performing a selective etching process for gate patterning.

Thus, according to the embodiment of the present invention, by forming a hard mask film used in the etching process for forming a trench type trench channel trench formed of silicon nitride film (Si _X N _Y ) or silicon oxy nitride film (SION) The profile of the hard mask film can be easily adjusted. As a result, the change in the critical dimension (CD) of the neck-shaped trench upper end of the bulb type trench channel trench can be minimized, and the critical dimension required by the device can be secured. By securing such a critical dimension, it is possible to prevent the loss of the corner of the upper end of the trench in the long axis direction of the active region generated in the region where the critical dimension increases in the conventional case. In addition, it is possible to prevent the silicon (Si) attack of the trench upper corner.

As described above, according to the method for manufacturing a semiconductor device having a bulb type recess channel according to the present invention, the hard mask film is formed by forming a silicon nitride film (Si _X N _Y ) or a silicon oxy nitride film (SION). The profile of the mask film can be easily adjusted. As a result, the critical dimension required by the device can be secured, and the loss of the trench upper corner and the silicon (Si) attack can be prevented.

Claims (9)

Forming an isolation layer for setting an active region on the semiconductor substrate; Forming a hard mask layer having a higher etching selectivity than the oxide layer on the semiconductor substrate; Selectively exposing an active region of the semiconductor substrate to form a hard mask layer pattern having a slope profile; Forming a first trench in the semiconductor substrate using the hard mask layer pattern as an etch mask; Forming a barrier layer on the sidewalls of the first trenches; Removing the hard mask layer pattern; Forming a second trench in the lower portion of the first trench by using the barrier layer as an etch mask to form a bulb channel trench formed of the first trench and the second trench; And And forming a gate stack overlapping the trench of the bulb type recess channel. The method of claim 1, The hard mask film is a semiconductor device forming method comprising a bulb type recess channel, characterized in that the oxide film and the silicon nitride film (Si _X N _Y ) or the oxide film and the silicon oxy nitride film (SION) laminated structure. The method of claim 2, The oxide film may be formed to a thickness of 200-300 GPa, and the silicon nitride film (Si _X N _Y ) or the silicon oxynitride film (SION) may be formed to have a bulb type recess channel. Method for forming a semiconductor device comprising. The method of claim 1, And the first trench is formed to a depth of 1000-1500 Å. The method of claim 1, wherein the forming of the barrier layer comprises: Depositing an oxide film on the first trench; And And removing an oxide layer on the top of the hard mask layer and the bottom surface of the first trench to leave a barrier layer on the sidewalls of the first trench. The method of claim 1, And the barrier layer is formed using anisotropic etching. The method of claim 1, The hard mask film pattern, the method of forming a semiconductor device comprising a bulb type recess channel, characterized in that for removing using a phosphoric acid (H ₃ PO ₄ ) solution. The method of claim 1, And the second trench is formed to have a diameter of 500-900 Å. The method of claim 1, And the second trench is formed using an isotropic etching process.

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