KR20080064496A - Method for manufacturing semiconductor device having bulb-type recessed channel - Google Patents

Abstract

A method for manufacturing a semiconductor device having a recess channel of valve type is provided to prevent deterioration of the characteristics of a cell device by preventing movement of void and change of the threshold voltage of a cell. A method for manufacturing a semiconductor device includes: forming a trench(220) of valve type in a semiconductor substrate; forming a gate insulation layer extending from the inner surface of a value in the trench; depositing a first semiconductor layer(224) formed on the gate insulation layer and extending into the valve; flowing PH3 on the first semiconductor layer; depositing a tungsten based barrier layer(226) formed on the first semiconductor layer and extending into the valve; depositing a second semiconductor layer on the tungsten based barrier layer; depositing a metal layer(230) and a hard mask layer(232) on the second semiconductor layer; and forming a gate stack overlapping the trench by patterning the hard mask layer, the metal layer, the second semiconductor layer, the tungsten based barrier layer, the first semiconductor layer, and the gate insulation layer.

Description

Method for manufacturing semiconductor device having bulb type recess channel {Method for manufacturing semiconductor device having bulb-type recessed channel}

1 is a diagram illustrating a semiconductor device having a bulb type recess channel according to the related art.

2A to 2K are views illustrating a method of manufacturing a semiconductor device having a bulb type recess channel according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a bulb type recess channel capable of improving on-off characteristics of a cell transistor.

Recently, as the degree of integration of integrated circuit semiconductor devices has increased and design rules have sharply decreased, it is increasingly difficult to secure stable operation of transistors. Therefore, various methods for securing channel lengths without increasing design rules have been studied. In particular, a semiconductor device having a bulb-type recess channel using a two-step etching process has been proposed as a structure for extending the channel length to a limited gate line width.

1 is a diagram illustrating a semiconductor device having a bulb type recess channel according to the related art.

Referring to FIG. 1, in the semiconductor device having a conventional bulb type recess channel, an isolation layer 102 defining an active region is disposed in the semiconductor substrate 100. Next, a bulb type trench channel trench 103 having a bottom surface in the form of a bulb is formed in the semiconductor substrate 100. Next, the gate stack 112 is formed to overlap with the trench type trench channel 103. The gate stack 112 may include a gate insulating film pattern 104, a conductive film pattern 106, a metal film pattern 108, and a hard mask film pattern 110.

In the semiconductor device formed as described above, a channel is formed along the trench channel trench 103 of the bulb type, and the effective channel length is increased compared to the semiconductor device having a planar channel. As the effective channel length increases, the cell threshold voltage (Vth) increases accordingly. As the cell threshold voltage rises, the amount of electric field decreases, which reduces junction leakage current and gate induced drain leakage (GIDL), improving the device's refresh characteristics.

Meanwhile, in the process of forming a bulb type trench channel trench 103 in the semiconductor substrate 100 and then depositing a gate conductive film to fill the trench 103, a void type seam (void) is formed in the gate conductive film. Seam, 114) may occur. This is because the bottom of the trench is formed in a sphere structure. However, a problem in which the seam formed in the gate conductive layer moves in the direction of the gate insulating layer 104 in the heat treatment process performed in the process of manufacturing the semiconductor device is caused. This may be understood as the diffusion of silicon (Si) of polysilicon according to the difference in impurity concentration. As described above, it is recognized that the silicon insulating film becomes thick in part while the silicon Si moves toward the gate insulating film 104. As a result, an increase in cell threshold voltage Vth occurs at a portion of the channel forming region where seam is moved, and a current drop occurs according to the write recovery time (tWR). The problem is that the characteristics of the same cell element deteriorate. Therefore, there is a need for a method capable of improving on-off characteristics of the cell transistor while minimizing the phenomenon of silicon (Si) movement.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device having a bulb type recess channel capable of improving the electrical characteristics of a cell transistor while minimizing the phenomenon of silicon migration.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a bulb type recess channel according to the present invention, forming a bulb type trench in the semiconductor substrate; Forming a gate insulating film extending on the bulb inner surface in the bulb type trench; Depositing a first semiconductor film formed on the gate insulating film and extending into the bulb; Flowing a phosphine (PH ₃ ) gas on the first semiconductor film; Depositing a tungsten (W) -based barrier film formed on the first semiconductor film and extending into the bulb; Depositing a second semiconductor film on the tungsten-based barrier film; Depositing a metal film and a hard mask film on the second semiconductor film; And patterning the hard mask film, the metal film, the second semiconductor film, the tungsten-based barrier film, the first semiconductor film, and the gate insulating film to form a gate stack overlapping the bulb type trench. .

The forming of the bulb type trench may include forming a hard mask layer pattern on the semiconductor substrate to expose an active region of the semiconductor substrate on which the bulb type trench is to be formed; Etching the semiconductor substrate exposing the hard mask layer pattern as a mask to form a first trench; Forming a barrier layer on the sidewalls of the first trenches; And forming a spherical second trench from the bottom of the first trench using the barrier layer as a mask to form a bulb type trench comprising the first trench and the second trench.

The hard mask film is preferably trapped in a structure in which an oxide film and an amorphous carbon film are laminated.

It is preferable that the said barrier film contains an oxide film.

The second trench may be formed to have a diameter of 500-900Å.

The first semiconductor film may be formed including doped polysilicon.

The depositing of the first semiconductor film and the flowing of the phosphine (PH ₃ ) gas on the first semiconductor film may be performed in an in-situ process.

The tungsten (W) -based barrier film may be formed by selecting any one or more materials from a group of tungsten (W), tungsten silicide (WSix) film, and tungsten nitride (WN) film.

It is preferable that the said 2nd semiconductor film consists of a structure by which doped polysilicon and undoped polysilicon were laminated | stacked.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

2A to 2K are views illustrating a method of manufacturing a semiconductor device having a bulb type recess channel according to an embodiment of the present invention.

Referring to FIG. 2A, a trench isolation layer 202 defining an active region is formed on the semiconductor substrate 200.

Specifically, the pad oxide film and the pad nitride film are sequentially deposited and then selectively removed to expose the device isolation region of the semiconductor substrate 200. Subsequently, the device isolation region of the exposed semiconductor substrate 200 is etched to form a trench having a predetermined depth. Next, a buried insulating film is formed on the entire surface to fill the trench, and after the planarization process is performed, the trench isolation film 202 is formed by removing the pad nitride film and the pad oxide film. Next, a threshold voltage screen oxide film (Vt screen) 204 to be used as a pad in the ion implantation process for adjusting the threshold voltage on the surface of the active region is formed to a thickness of 50-100 kV, and the cell region and the peripheral circuit region are formed. Perform ion implantation on.

Referring to FIG. 2B, the first hard mask film 206 and the second hard mask film 208 are sequentially deposited on the semiconductor substrate 200 including the screen oxide film 204.

The first and second hard mask layers 206 and 208 are then used as etching masks in the etching process to form upper trenches of the bulb type recess channels. Here, the primary hard mask film 206 may be formed of an oxide film or a nitride film having a thickness of 200-400 GPa, and the secondary hard mask film 208 is a film containing amorphous carbon, having a thickness of 1500-2000 GPa. It can be formed as.

Subsequently, a photoresist layer is applied and patterned on the second hard mask layer 208 to expose a predetermined region of the secondary hard mask layer 208, for example, a region where a bulb type trench channel trench is to be formed. Form 210. In this case, the photoresist pattern 210 may be formed to include an anti-reflection film (not shown).

 Referring to FIG. 2C, the secondary hard mask layer 206 is etched using the photoresist layer pattern 210 as a mask to form a secondary hard mask layer pattern 208 ′ that selectively exposes the primary hard mask layer 208. do. Subsequently, the primary hard mask layer pattern 206 is selectively etched by etching the primary hard mask layer 206 and the screen oxide layer 204 using the secondary hard mask layer 208 'as a mask. ) And an oxide film pattern 204 '. The exposed region of the semiconductor substrate 200 is a region where a bulb type trench channel trench is to be formed.

Referring to FIG. 2D, the semiconductor substrate 200 exposing the photosensitive film pattern 210, the second hard mask film pattern 208 ′, the first hard mask film pattern 206 ′ and the oxide film pattern 204 ′ as a mask. The first trench 214 is formed by etching the active region of the trench.

Here, the first trench 214 corresponds to a neck portion of a bulb type bulb. The first trench 214 is formed to a suitable depth, for example, 1000-1500 mm in consideration of the size of the bulb to be formed later. Next, the photoresist pattern 210 is removed using a strip process. In this case, the second hard mask film pattern 208 ′ is removed together in the process of removing the photoresist pattern 210. Afterwards, the cleaning process is performed to remove foreign substances on the semiconductor substrate 200 generated in the etching process.

Subsequently, a barrier film 216 is formed on the sidewalls of the first trench 214.

Specifically, an oxide film is formed on the entire surface of the semiconductor substrate 200. Next, an oxide film of the upper portion, the bottom surface of the first trench 214, and a portion of the trench sidewall is selectively etched to form a barrier layer 216. Then, the silicon layer Si of the bottom surface of the first trench 214 and a portion of the trench sidewall is exposed. Here, the barrier film 216 may be formed to a thickness of 40-70-.

Referring to FIG. 2E, a spherical second trench 218 is formed in the lower end of the first trench 214 using the first hard mask layer pattern 206 ′ and the barrier layer 216 as an etch mask. Then, the bulb type trench 220 including the first trench 214 and the spherical second trench 218 is formed. Here, the spherical second trench 218 is preferably etched from the bottom surface of the first trench 214. The etching process of forming the spherical second trench 218 may be etched at the same speed in all directions to proceed to isotropic etching having a curved surface after etching. In this case, the spherical second trench 218 may be formed to have a diameter of 500-900 mm.

In this case, the barrier layer 218 may prevent damage to the semiconductor substrate 200, which may occur due to excessive etching of the bulb type trench 220 side during the isotropic etching. Next, the primary hard mask film pattern 206 'and the barrier film 216 are removed.

Referring to FIG. 2F, the BFN cleaning is performed on the semiconductor substrate 200 for 250-350 seconds to remove the oxide film remaining on the active region of the semiconductor substrate 200.

BFN cleaning includes B cleaning using a first solution of sulfuric acid (H ₂ O ₄ ) and fruit water (H ₂ O ₂ ), F cleaning using a second solution containing dilute hydrofluoric acid (HF), and ammonia (NH). N-washing using a third solution containing a mixture of ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) is carried out sequentially. During the cleaning process, the barrier layer 216 and the impurities remaining in the bulb type trench 220 may be removed.

Referring to FIG. 2G, a gate insulating film 222 is formed that extends on the inner surface of the bulb in the bulb type trench 220, for example, the second trench 218. Subsequently, a first semiconductor layer 224 is formed on the gate insulating layer 222 and extends into the bulb in the bulb type trench 220. Here, the gate insulating layer 222 may be formed to have a thickness of 30 to 50 kV including an oxide film. The first semiconductor film 224 may include a doped polysilicon film and have a thickness of 50-100 μs. In this case, disilane (Si ₂ H ₆ ) may be supplied at a flow rate of 5-20 sccm in the process of depositing the first semiconductor film 224.

Referring to FIG. 2H, after depositing the first semiconductor layer 224, a phosphine (PH ₃ ) gas is supplied onto the semiconductor substrate 200 to form a first semiconductor layer 224 having a high doped surface. do. Here, the deposition process of the first semiconductor film 224 and the process of supplying and flowing the phosphine (PH ₃ ) gas on the first semiconductor film 224 may be performed in an in-situ process. . Then, a large amount of phosphine (PH ₃ ) is injected into the surface of the first semiconductor film 224, the first semiconductor film 224 is formed of a high-doped polysilicon film (High doped level poly-silicon). In this case, the impurity concentration implanted on the surface of the first semiconductor film 224 may be implanted at a concentration of 1.0E20 to 4.0E20 atm / cm 3. As described above, when a large amount of phosphine (PH ₃ ) is injected into the surface of the first semiconductor film 224, the first semiconductor film 224 maintains a doped polysilicon state with a high impurity concentration. In this process, movement of seams in the semiconductor film may be minimized.

Referring to FIG. 2I, a tungsten (W) based barrier film 226 is formed on the first semiconductor film 224 and extends into the bulb. The tungsten (W) -based barrier film 226 may be formed to a thickness of 50-100 kPa by selecting any one or more materials from the group of tungsten (W), tungsten silicide (WSix) film, and tungsten nitride (WN) film. . The tungsten-based barrier layer 226 serves to minimize seam dml movement in the semiconductor layer deposited in a subsequent process together with the first semiconductor layer 224.

Referring to FIG. 2J, a bulb type trench 220 is buried by depositing a second semiconductor layer 228 on the tungsten (W) -based barrier layer 226. The second semiconductor film 228 may have a structure in which doped polysilicon and undoped polysilicon are stacked to have a thickness of 400 to 600 Å. In this case, disilane (Si ₂ H ₆ ) may be supplied at a flow rate of 5-20 sccm in the process of depositing the second semiconductor film 228.

A sphere-shaped second portion formed at a lower end of the first trench 214 in contrast to a critical dimension (CD) of the first trench 214 corresponding to the neck portion of the bulb type trench 220. The critical dimension of trench 218 is relatively large. Accordingly, in the process of depositing the second semiconductor layer 288, the first trench 214 is filled first, and thus, the inside of the second trench 218 is not buried, and a void-like seam is generated. In the conventional case, the seam generated in this manner was generated as the silicon (Si) particles were diffused to the center by the concentration gradient of impurities and moved in the direction of the gate insulating film.

Accordingly, in the present invention, the first semiconductor film 224 is deposited in the bulb type trench 220 and the phosphine (PH ₃ ) gas is supplied to the first semiconductor film 224 to minimize the movement of silicon (Si). It is maintained in a high concentration of doped polysilicon state. In addition, by depositing the tungsten-based barrier film 226 on the first semiconductor film 224, it is possible to suppress the movement of silicon (Si) and to prevent the void from moving in the direction of the gate insulating film. By preventing the movement of the void in this manner, it is possible to prevent the cell threshold voltage from changing, thereby preventing the cell element characteristics from deteriorating. In addition, by depositing the tungsten-based barrier film 226 in the form of a buffer film between the first semiconductor film 224 and the second semiconductor film 228, the swing characteristics of the transistor are improved, thereby turning on the transistors. -off) property can be improved. In addition, by inserting a tungsten-based barrier film 226 having a low sheet resistance (Rs) value, the resistance can be lowered.

Subsequently, the metal film 230 and the hard mask film 232 are deposited on the second semiconductor film 228. Here, the metal film 230 may deposit a tungsten silicide (WSix) film at a thickness of 1000-1500 Å. In this case, the metal film 230 may have a structure in which a tungsten film, a tungsten nitride film, and a tungsten silicide film (W / WN / WSix) are stacked to have a thickness of 500 to 600 Å. In addition, the hard mask film 232 may be formed of a nitride film.

Next, a photoresist film is applied and patterned on the hard mask film 232 to form a photoresist film pattern 234 for selectively exposing the hard mask film 232.

Referring to FIG. 2K, an etching process is performed using the photoresist pattern 234 as a mask to form a gate stack 248 on the semiconductor substrate 200. The gate stack 248 has a structure in which a gate insulating film pattern 236, a first semiconductor film pattern 238, a barrier metal film pattern 240, a second semiconductor film pattern 242, and a hard mask film pattern 244 are stacked. Is made of.

As described above, according to the method for manufacturing a semiconductor device having a bulb type recess channel according to the present invention, a first semiconductor film having a high concentration of doped polysilicon is deposited in a bulb type trench, and a tungsten barrier film is deposited. The voids can be prevented from moving by depositing a second semiconductor film after deposition. By preventing the movement of the voids, the cell threshold voltage can be prevented from changing so that the cell element characteristics can be prevented from deteriorating.

In addition, by depositing a tungsten-based barrier film in the form of a buffer film between the first semiconductor film and the second semiconductor film, the resistance value is lowered, and the swing characteristics of the transistor are improved to improve on-off characteristics of the transistor. Can be improved.

Claims (9)

Forming a bulb type trench in the semiconductor substrate; Forming a gate insulating film extending on the bulb inner surface in the bulb type trench; Depositing a first semiconductor film formed on the gate insulating film and extending into the bulb; Flowing a phosphine (PH ₃ ) gas on the first semiconductor film; Depositing a tungsten (W) -based barrier film formed on the first semiconductor film and extending into the bulb; Depositing a second semiconductor film on the tungsten-based barrier film; Depositing a metal film and a hard mask film on the second semiconductor film; And And patterning the hard mask film, the metal film, the second semiconductor film, the tungsten barrier film, the first semiconductor film, and the gate insulating film to form a gate stack overlapping the bulb type trench. A method for manufacturing a semiconductor device having a recess channel of the type. The method of claim 1, wherein the forming of the bulb type trench comprises: Forming a hard mask layer pattern on the semiconductor substrate to expose an active region of the semiconductor substrate on which a bulb type trench is to be formed; Etching the semiconductor substrate exposing the hard mask layer pattern as a mask to form a first trench; Forming a barrier layer on the sidewalls of the first trenches; And Forming a bulb-type trench comprising a first trench and a second trench by forming a spherical second trench from the bottom of the first trench using the barrier layer as a mask; A method for manufacturing a semiconductor device having a set channel. The method of claim 2, The hard mask film is a semiconductor device manufacturing method having a bulb type recess channel, characterized in that the oxide film and the amorphous carbon film laminated structure. The method of claim 2, And said barrier film comprises an oxide film. The method of claim 2, The second trench is a manufacturing method of a semiconductor device having a bulb type recess channel, characterized in that formed to have a diameter of 500-900Å. The method of claim 1, And the doped polysilicon layer comprises a doped polysilicon layer. The method of claim 1, The deposition of the first semiconductor layer and the flow of the phosphine (PH ₃ ) gas on the first semiconductor layer may be performed in an in-situ process. Method for manufacturing a semiconductor device having a. The method of claim 1, The tungsten (W) -based barrier film is a semiconductor having a bulb type recess channel, wherein at least one material selected from the group consisting of tungsten (W), tungsten silicide (WSix) and tungsten nitride (WN) is selected. Method of manufacturing the device. The method of claim 1, The second semiconductor film is a semiconductor device manufacturing method having a bulb type recess channel, characterized in that the doped polysilicon and the undoped polysilicon structure laminated.

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