KR20070118349A - Formation method of plating line for printed circuit board - Google Patents

Formation method of plating line for printed circuit board Download PDF

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Publication number
KR20070118349A
KR20070118349A KR1020060052368A KR20060052368A KR20070118349A KR 20070118349 A KR20070118349 A KR 20070118349A KR 1020060052368 A KR1020060052368 A KR 1020060052368A KR 20060052368 A KR20060052368 A KR 20060052368A KR 20070118349 A KR20070118349 A KR 20070118349A
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South Korea
Prior art keywords
printed circuit
circuit board
plating
forming
plating line
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KR1020060052368A
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Korean (ko)
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KR100797670B1 (en
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강태혁
박상갑
홍석창
황규일
전성일
김원희
오화섭
최봉규
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삼성전기주식회사
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
    • H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

A method for forming a plating line of a PCB is provided to decrease a variation of a thickness of a plating layer by providing an equal current for the PCB by equally forming length of the plating line formed between a plating connection point and the PCB. A method for forming a plating line of a PCB(Printed Circuit Board) includes the step of: forming the plating line(58) in a dummy area so as to have equal connection length between a plating contact point connected with a cathode of an outside power unit and a unit of the PCB in the PCB panel including a plurality of strips(54) formed by a plurality of the PCB units(52) and a dummy area(62) formed between the plurality of strips and an outside of the strips to divide the strips.

Description

인쇄회로기판의 도금선 형성 방법{Formation Method of Plating Line for Printed Circuit Board}Formation Line of Printed Circuit Board {Formation Method of Plating Line for Printed Circuit Board}

도 1은 종래의 기술에 따른 인쇄회로기판 패널을 나타내는 도면이다.1 is a view showing a printed circuit board panel according to the prior art.

도 2는 본 발명의 일 실시 예에 따른 인쇄회로기판의 도금선 형성 방법에 의해 형성된 인쇄회로기판 패널을 나타내는 도면이다.2 is a view showing a printed circuit board panel formed by a plating line forming method of a printed circuit board according to an embodiment of the present invention.

도 3은 본 발명의 다른 실시 예에 따른 인쇄회로기판의 도금선 형성 방법에 의해 형성된 인쇄회로기판 패널을 나타내는 도면이다.3 is a view showing a printed circuit board panel formed by a plating line forming method of a printed circuit board according to another embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

2, 52 : 인쇄회로기판 유닛 4, 54 : 스트립2, 52: PCB 4, 54: strip

6, 56 : 도금 접점 8, 58 : 도금선6, 56: plating contact 8, 58: plating wire

10, 60 : 인쇄회로기판 패널 12, 62 : 더미 영역10, 60: printed circuit board panel 12, 62: dummy area

58a, 58b : 배선 66 : 접점58a, 58b: wiring 66: contact

본 발명은 인쇄회로기판의 도금선 형성 방법에 관한 것으로, 특히 도금선의 길이를 동일하게 하여 도금 두께의 편차를 줄임으로써 양품 확률을 향상시켜 생산성을 향상시킴과 아울러 공정비용을 줄일 수 있는 인쇄회로기판의 도금선 형성 방법에 관한 것이다.The present invention relates to a method for forming a plated line of a printed circuit board, and in particular, by reducing the variation in plating thickness by making the length of the plated line the same, improving the probability of yield and improving productivity and reducing the process cost. It relates to a plating line forming method.

인쇄회로기판(Printed Circuit Borad; PCB)이란 전자부품 상호 간의 전기배선을 회로설계에 기초하여, 절연기판 위에 도체를 형성하는 프린트 배선판으로 PCB기판, 프린트회로판 또는 인쇄배선기판(Printed Wiring Board)이라고 한다.Printed Circuit Board (PCB) is a printed wiring board that forms conductors on insulating boards based on circuit design. The electrical wiring between electronic components is called a PCB board, printed circuit board, or printed wiring board. .

일반적으로 인쇄회로기판은 페놀수지 절연판 또는 에폭시수지 절연판 등의 표면에 구리 박판을 부착시킨 후, 회로의 배선패턴에 따라 에칭하여 필요한 회로를 구성하고 그 위에 IC, 콘덴서, 저항 등의 여러 가지 전기전자부품을 조밀하게 탑재할 수 있게 하는 절연평판이다.In general, a printed circuit board is formed by attaching a copper thin plate to a surface of a phenol resin insulator or an epoxy resin insulator, and then etching it according to the wiring pattern of the circuit to form a necessary circuit, and various electrical and electronic devices such as IC, capacitor, and resistor thereon. It is an insulating flat plate that allows compact mounting of parts.

즉, 각 전자부품 상호 간을 연결하는 회로를 절연판의 표면에 배선모양으로 형성시킨 것이다. 인쇄회로기판은 배선회로판의 면수에 따라 단면기판, 양면기판, 다층기판 등으로 분류되고 있으며, 층수가 많을수록 부품의 실장력이 우수하고 고정밀제품에 사용된다.That is, a circuit for connecting the electronic components with each other is formed in the shape of a wiring on the surface of the insulating plate. Printed circuit boards are classified into single-sided boards, double-sided boards, and multilayer boards according to the number of printed circuit boards. The higher the number of layers, the better the mounting force of the parts and the high-precision products.

이러한, 인쇄회로기판의 제조방법은 홀을 가공하는 드릴(Drill) 공정, 가공된 홀의 전도성을 부여하는 동도금 공정 및 회로를 형성하는 회로공정으로 나누어진다.The method of manufacturing a printed circuit board is divided into a drill process for processing holes, a copper plating process for imparting conductivity of the processed holes, and a circuit process for forming a circuit.

이중 동도금 공정은 무전해 도금 공정과 전해 도금 공정으로 나누어진다. 여 기서, 무전해 도금 공정은 촉매를 이용하여 절연체에 도전성을 부여하는 공정이고, 전해 도금 공정은 도전성이 부여된 기판에 전류를 인가하여 동도금층을 형성하는 공정이다.The double copper plating process is divided into an electroless plating process and an electrolytic plating process. Here, the electroless plating process is a process of imparting conductivity to the insulator using a catalyst, and the electrolytic plating process is a process of applying a current to a substrate to which conductivity is applied to form a copper plating layer.

도 1은 전해 도금을 위해 사용되는 종래의 인쇄회로기판 패널을 나타내는 도면이다.1 is a view showing a conventional printed circuit board panel used for electroplating.

도 1을 참조하면, 종래의 인쇄회로기판 패널은 다수의 인쇄회로기판 유닛(2)이 형성된 스트립(4), 외부로부터 입력되는 전압을 다수의 인쇄회로기판 유닛(2)에 공급하기 위한 도금 접점(6) 및 도금 접점(6)과 인쇄회로기판 유닛(2) 사이에 형성된 다수의 도금선(8)을 포함한다.Referring to FIG. 1, a conventional printed circuit board panel includes a strip 4 on which a plurality of printed circuit board units 2 are formed, and a plating contact for supplying a voltage input from the outside to the plurality of printed circuit board units 2. (6) and a plurality of plated wires 8 formed between the plated contacts 6 and the printed circuit board unit 2.

스트립(4)은 인쇄회로기판 패널(10)에 다수 개가 형성되고, 다수의 스트립(4) 각각에는 다수의 인쇄회로기판 유닛(2)이 형성되어 있다. 이에 따라, 전해 도금 공정 시 많은 인쇄회로기판에 전해 도금을 동시에 할 수 있게 된다. 이러한, 스트립(4)은 회로가 형성되어 있지 않은 더미 영역(2)에 의해 인접하는 스트립(4)과 구분되어 진다.A plurality of strips 4 are formed in the printed circuit board panel 10, and a plurality of printed circuit board units 2 are formed in each of the plurality of strips 4. Accordingly, during the electroplating process, electroplating can be simultaneously performed on many printed circuit boards. This strip 4 is distinguished from the adjacent strip 4 by a dummy region 2 in which no circuit is formed.

도금 접점(6)은 더미 영역(2)에 다수 개가 형성되어 외부 전원장치(도시하지 않음)의 음극(-)에 연결된다.A plurality of plating contacts 6 are formed in the dummy region 2 and connected to the negative electrode (−) of an external power supply (not shown).

도금선(8)은 도금 접점(6)과 인쇄회로기판 유닛(2) 사이에 형성되어 도금 접점(6)을 통해 외부 전원장치(도시하지 않음)의 음극(-)과 인쇄회로기판 유닛(2)에 도금을 할 부분을 연결하는 역할을 한다.The plating line 8 is formed between the plating contact 6 and the printed circuit board unit 2 so that the cathode (-) of the external power supply (not shown) and the printed circuit board unit 2 are formed through the plating contact 6. ) To connect the part to be plated.

이러한, 도금선(8)은 표1에 도시된 바와 같이 기준 도금 접점(6)과 스트 립(4) 내에 형성된 다수의 인쇄회로기판 유닛(2) 사이에 서로 다른 길이를 갖도록 형성된다.The plating line 8 is formed to have a different length between the reference plating contact 6 and the plurality of printed circuit board units 2 formed in the strip 4, as shown in Table 1.

PointPoint 도금선 길이Plating wire length PointPoint 도금선 길이Plating wire length PointPoint 도금선 길이Plating wire length PointPoint 도금선 길이Plating wire length A=>AAA => AA 1㎜1 mm A=>BAA => BA 6㎜6 mm A=>CAA => CA 12㎜12 mm A=>DAA => DA 17㎜17 mm A=>A1A => A1 2㎜2 mm A=>B1A => B1 7㎜7 mm A=>C1A => C1 13㎜13 mm A=>D1A => D1 18㎜18 mm A=>A2A => A2 3㎜3 mm A=>B2A => B2 8㎜8 mm A=>C2A => C2 14㎜14 mm A=>D2A => D2 19㎜19 mm A=>A3A => A3 4㎜4 mm A=>B3A => B3 9㎜9 mm A=>C3A => C3 15㎜15 mm A=>D3A => D3 20㎜20 mm A=>A4A => A4 5㎜5 mm A=>B4A => B4 10㎜10 mm A=>C4A => C4 16㎜16 mm A=>D4A => D4 21㎜21 mm A=>A5A => A5 6㎜6 mm A=>B5A => B5 11㎜11 mm A=>C5A => C5 17㎜17 mm A=>D5A => D5 22㎜22 mm A=>A6A => A6 7㎜7 mm A=>B6A => B6 12㎜12 mm A=>C6A => C6 18㎜18 mm A=>D6A => D6 23㎜23 mm A=>A7A => A7 8㎜8 mm A=>B7A => B7 13㎜13 mm A=>C7A => C7 19㎜19 mm A=>D7A => D7 24㎜24 mm A=>A8A => A8 9㎜9 mm A=>B8A => B8 14㎜14 mm A=>C8A => C8 20㎜20 mm A=>D8A => D8 25㎜25 mm A=>A9A => A9 10㎜10 mm A=>B9A => B9 15㎜15 mm A=>C9A => C9 21㎜21 mm A=>D9A => D9 26㎜26 mm

여기서, 기준 도금 접점(6)과 각각의 인쇄회로기판 유닛 사이의 도금선(8) 길이는 정확한 측정에 의한 길이가 아니라 대략적인 길이를 나타내는 것이다.Here, the length of the plating line 8 between the reference plating contact 6 and each printed circuit board unit indicates the approximate length, not the length by accurate measurement.

이와 같은 구성을 갖는 인쇄회로기판 패널은 도금 접점(6)을 외부 전원장치(도시하지 않음)의 음극(-)에 연결한 후 전해액이 충전되어 있는 탱크에 침지 시킨다. 이때, 전해액 속에는 외부 전원장치(도시하지 않음)의 양극(+)과 연결된 금, 은, 동, 니켈 등과 같은 소재가 함유된다.The printed circuit board panel having such a configuration is connected to the negative electrode (-) of the external power supply device (not shown) and then immersed in the tank filled with the electrolyte. At this time, the electrolyte contains a material such as gold, silver, copper, nickel and the like connected to the positive electrode (+) of the external power supply (not shown).

이에 따라, 인쇄회로기판 유닛(2)에 도금층이 형성된다.As a result, a plating layer is formed on the printed circuit board unit 2.

그러나, 이와 같은 종래 기술은 도금 접점(6)과 다수의 인쇄회로기판 유닛(2) 사이에 형성된 도금선(8)의 길이가 서로 다르기 때문에 전해 도금 공정 시 각각의 인쇄회로기판 유닛(2)에 균일한 전류가 공급되지 않아 전해 도금 공정 시 인쇄회로기판에 형성되는 도금층이 균일하게 형성되지 않는 문제가 있다.However, such a prior art has different lengths of the plating lines 8 formed between the plating contacts 6 and the plurality of printed circuit board units 2, so that the respective printed circuit board units 2 may be different in the electroplating process. Since a uniform current is not supplied, a plating layer formed on the printed circuit board may not be uniformly formed during the electroplating process.

다시 말해, 종래의 인쇄회로기판의 도금선 형성 방법에서는 전해액이 충전된 탱크에 침지 시킨 후 외부 전원장치(도시하지 않음)로부터 전압을 인가하면 도금 접점(6)과 인쇄회로기판 유닛(2) 사이에 형성된 서로 다른 길이의 도금선(8)이 가지는 저항 차이로 인해 각각의 인쇄회로기판 유닛(2)에 공급되는 전류의 편차가 발생하게 된다. 이에 따라, 전해 도금 공정 시 인쇄회로기판 유닛(2)에 형성되는 도금층이 균일하게 형성되지 않게 된다.In other words, in the conventional method for forming a plating line of a printed circuit board, when a voltage is applied from an external power supply device (not shown) after immersing in a tank filled with electrolyte, the plating contact 6 and the printed circuit board unit 2 are separated. Due to the resistance difference between the plating wires 8 having different lengths, the current difference supplied to each printed circuit board unit 2 is generated. Accordingly, the plating layer formed on the printed circuit board unit 2 is not uniformly formed during the electroplating process.

이로 인해, 스트립(4) 내에 다수 형성된 인쇄회로기판 유닛(2)의 양품 확률이 저하되어 생산성이 저하될 뿐만 아니라 공정비용이 증가하는 문제가 있다.For this reason, there is a problem that the yield probability of the printed circuit board unit 2 formed in the strip 4 is lowered, thereby lowering productivity and increasing process cost.

따라서, 본 발명은 도금선의 길이를 동일하게 하여 도금 두께의 편차를 줄임으로써 양품 확률을 향상시켜 생산성을 향상시킴과 아울러 공정비용을 줄일 수 있는 인쇄회로기판의 도금선 형성 방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method of forming a plated line of a printed circuit board which can improve the yield probability by reducing the variation of the plated thickness by making the length of the plated line the same, thereby improving productivity and reducing the process cost. do.

상기 목적을 달성하기 위하여, 본 발명의 실시 예에 따른 인쇄회로기판의 도금선 형성 방법은 다수의 인쇄회로기판 유닛이 형성된 다수의 스트립과 상기 스트립을 구분 짓도록 상기 다수의 스트립 사이와 상기 스트립의 외곽부에 형성된 더미 영역을 포함하는 인쇄회로기판 패널에 있어서, 외부 전원장치의 음극과 연결되는 도금 접점과 상기 인쇄회로기판 유닛 사이에 동일한 연결 길이를 갖도록 상기 더미 영역에 도금선을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the plating line forming method of a printed circuit board according to an embodiment of the present invention and the plurality of strips formed with a plurality of printed circuit board unit and the strip between the plurality of strips to distinguish the strip In the printed circuit board panel including a dummy region formed in the outer portion, forming a plating line in the dummy region to have the same connection length between the plated contact connected to the cathode of the external power supply and the printed circuit board unit It is characterized by including.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일 실시 예에 따른 인쇄회로기판의 도금선 형성 방법에 의해 형성된 인쇄회로기판 패널을 나타내는 도면이다.2 is a view showing a printed circuit board panel formed by a plating line forming method of a printed circuit board according to an embodiment of the present invention.

도 2를 참조하면, 본 발명의 일 실시 예에 따른 인쇄회로기판 패널(60)은 다수의 인쇄회로기판 유닛(52)이 형성된 스트립(54), 외부 전원장치(도시하지 않음)의 음극(-)에 연결되는 도금 접점(56) 및 도금 접점(56)과 인쇄회로기판 유닛(52) 사이에 동일한 연결 길이를 갖도록 형성된 다수의 도금선(58)을 포함한다.Referring to FIG. 2, a printed circuit board panel 60 according to an exemplary embodiment may include a strip 54 having a plurality of printed circuit board units 52 formed therein, and a negative electrode (−) of an external power supply (not shown). ) And a plurality of plating lines 58 formed to have the same connection length between the plating contact 56 and the plating contact 56 and the printed circuit board unit 52.

스트립(54)은 인쇄회로기판 패널(60)에 다수 개가 형성되고, 다수의 스트립(54) 각각에 다수의 인쇄회로기판 유닛(52)이 형성되어 있다. 이에 따라, 전해 도금 공정 시 많은 인쇄회로기판 유닛(52)에 전해 도금을 동시에 할 수 있게 된다. A plurality of strips 54 are formed on the printed circuit board panel 60, and a plurality of printed circuit board units 52 are formed on each of the plurality of strips 54. Accordingly, the electroplating can be performed simultaneously on many printed circuit board units 52 during the electroplating process.

이러한, 스트립(54)은 회로가 형성되어 있지 않은 더미 영역(62)에 의해 인접하는 스트립(54)과 구분되어 진다. 이때, 더미 영역(62)은 다수의 스트립(54) 사이와 스트립(54)의 외곽부에 형성된다.This strip 54 is distinguished from the adjacent strip 54 by a dummy region 62 in which no circuit is formed. In this case, the dummy region 62 is formed between the plurality of strips 54 and the outer portion of the strip 54.

도금 접점(56)은 더미 영역(62)에 다수 개가 형성되고, 전해 도금 공정 시 외부 전원장치(도시하지 않음)의 음극(-)에 연결되어 도금선(58)을 통해 인쇄회로기판 유닛(52)에 접지를 공급하는 역할을 한다.A plurality of plating contacts 56 are formed in the dummy region 62, and are connected to the negative electrode (−) of an external power supply (not shown) during the electrolytic plating process, and are printed circuit board units 52 through the plating lines 58. ) To supply ground.

도금선(58)은 다수의 스트립(54)과 더미 영역(62)을 형성한 후 도금 접점(56)과 다수의 인쇄회로기판 유닛(52)을 각각 연결하기 위해 더미 영역(62)에 꾸 불꾸불한 사행(meander) 형태로 인쇄회로기판 유닛(52) 수만큼 형성한다. 이로 인해, 도금 접점(56)과 다수의 인쇄회로기판 유닛(52)이 각각 연결된다. 이에 따라, 도금 접점(56)에 연결되는 외부 전원장치(도시하지 않음)의 음극(-)은 도금선(58)을 통해 각각의 인쇄회로기판 유닛(52)에 연결된다.The plating lines 58 form a plurality of strips 54 and dummy regions 62 and then decorate the dummy regions 62 to connect the plating contacts 56 and the plurality of printed circuit board units 52, respectively. The number of printed circuit board units 52 is formed in a meander shape. As a result, the plating contact 56 and the plurality of printed circuit board units 52 are connected to each other. Accordingly, the cathode (-) of the external power supply (not shown) connected to the plating contact 56 is connected to each printed circuit board unit 52 through the plating line 58.

이러한, 도금선(58)은 동일한 연결 길이 즉, 동일한 저항을 갖도록 형성된다. 이에 따라, 전해 도금 공정 시 동일한 연결 길이를 갖도록 형성된 도금선(58)을 통해 다수의 인쇄회로기판 유닛(52) 각각에 동일한 전류가 공급되므로 전해 도금 공정 시 도금층을 균일하게 형성할 수 있게 된다.The plating line 58 is formed to have the same connection length, that is, the same resistance. Accordingly, since the same current is supplied to each of the plurality of printed circuit board units 52 through the plating line 58 formed to have the same connection length during the electrolytic plating process, the plating layer may be uniformly formed during the electrolytic plating process.

도 3은 본 발명의 다른 실시 예에 따른 인쇄회로기판의 도금선 형성 방법에 의해 형성된 인쇄회로기판 패널을 나타내는 도면이다.3 is a view showing a printed circuit board panel formed by a plating line forming method of a printed circuit board according to another embodiment of the present invention.

도 3을 참조하면, 본 발명의 다른 실시 예에 따른 인쇄회로기판 패널(60)은 다수의 인쇄회로기판 유닛(52)이 형성된 스트립(54), 외부 전원장치(도시하지 않음)의 음극(-)에 연결되는 도금 접점(56) 및 도금 접점(56)과 인쇄회로기판 유닛(52) 사이에 동일한 연결 길이를 갖도록 형성된 다수의 도금선(58)을 포함한다.Referring to FIG. 3, a printed circuit board panel 60 according to another embodiment of the present invention may include a strip 54 having a plurality of printed circuit board units 52 formed therein, and an anode (−) of an external power supply (not shown). ) And a plurality of plating lines 58 formed to have the same connection length between the plating contact 56 and the plating contact 56 and the printed circuit board unit 52.

스트립(54)은 인쇄회로기판 패널(60)에 다수 개가 형성되고, 다수의 스트립(54) 각각에 다수의 인쇄회로기판 유닛(52)이 형성되어 있다. 이에 따라, 전해 도금 공정 시 많은 인쇄회로기판 유닛(52)에 전해 도금을 동시에 할 수 있게 된다. A plurality of strips 54 are formed on the printed circuit board panel 60, and a plurality of printed circuit board units 52 are formed on each of the plurality of strips 54. Accordingly, the electroplating can be performed simultaneously on many printed circuit board units 52 during the electroplating process.

이러한, 스트립(54)은 회로가 형성되어 있지 않은 더미 영역(62)에 의해 인접하는 스트립(54)과 구분되어 진다. 이때, 더미 영역(62)은 다수의 스트립(54) 사이와 스트립(54)의 외곽부에 형성된다.This strip 54 is distinguished from the adjacent strip 54 by a dummy region 62 in which no circuit is formed. In this case, the dummy region 62 is formed between the plurality of strips 54 and the outer portion of the strip 54.

도금 접점(56)은 더미 영역(62)에 다수 개가 형성되고, 전해 도금 공정 시 외부 전원장치(도시하지 않음)의 음극(-)에 연결되어 도금선(58)을 통해 인쇄회로기판 유닛(52)에 접지를 공급하는 역할을 한다.A plurality of plating contacts 56 are formed in the dummy region 62, and are connected to the negative electrode (−) of an external power supply (not shown) during the electrolytic plating process, and are printed circuit board units 52 through the plating lines 58. ) To supply ground.

도금선(58)은 다수의 스트립(54)과 더미 영역(62)을 형성한 후 도금 접점(56)과 다수의 인쇄회로기판 유닛(52)을 연결하기 위해 더미 영역(62)에 꾸불꾸불한 사행(meander) 형태로 형성된다. 이러한, 도금선(58)은 도금 접점(56)부터 더미 영역(62)의 소정 위치에 있는 접점(66)까지 하나의 배선으로 공통으로 형성된 제 1 배선(58a)과 접점(66)부터 각각의 인쇄회로기판 유닛(52)까지 형성된 제 2 배선(58b)을 포함한다. The plating lines 58 form a plurality of strips 54 and a dummy region 62, and are then twisted in the dummy region 62 to connect the plating contacts 56 and the plurality of printed circuit board units 52. It is formed in the form of meander. The plated wire 58 is formed of the first wire 58a and the contact 66 which are commonly formed in one wire from the plated contact 56 to the contact 66 at a predetermined position of the dummy region 62. The second wiring 58b formed up to the printed circuit board unit 52 is included.

이때, 제 1 배선(58a) 및 제 2 배선(58b)은 동시에 형성되거나 제 1 배선(58a) 또는 제 2 배선을 형성한 후 제 2 배선(58b) 또는 제 1 배선(58a)을 형성한다. 여기서, 제 2 배선(58b)은 각각 동일한 연결 길이 즉, 동일한 저항을 갖도록 형성된다. At this time, the first wiring 58a and the second wiring 58b are formed at the same time, or after forming the first wiring 58a or the second wiring, the second wiring 58b or the first wiring 58a is formed. Here, each of the second wirings 58b is formed to have the same connection length, that is, the same resistance.

이에 따라, 전해 도금 공정 시 동일한 연결 길이를 갖도록 형성된 도금선(58)을 통해 다수의 인쇄회로기판 유닛(52) 각각에 동일한 전류가 공급되므로 전해 도금 공정 시 도금층을 균일하게 형성할 수 있게 된다.Accordingly, since the same current is supplied to each of the plurality of printed circuit board units 52 through the plating line 58 formed to have the same connection length during the electrolytic plating process, the plating layer may be uniformly formed during the electrolytic plating process.

상술한 바와 같이, 본 발명은 도금 접점과 인쇄회로기판 사이에 형성된 도금선의 길이를 동일하게 형성함으로써 전해 도금 공정 시 도금선을 통해 인쇄회로기 판에 동일한 전류가 공급되므로 전해 도금 공정 시 형성되는 도금층의 두께 편차를 줄일 수 있다.As described above, the present invention by forming the same length of the plating line formed between the plating contact and the printed circuit board, the plating layer formed during the electroplating process because the same current is supplied to the printed circuit board through the plating line during the electroplating process Can reduce the thickness variation.

이로 인해, 인쇄회로기판의 양품 확률이 향상되어 생산성이 향상될 뿐만 아니라 공정비용을 줄일 수 있다.As a result, the yield probability of the printed circuit board is improved, thereby improving productivity and reducing process costs.

여기서, 상술한 본 발명에서는 바람직한 실시예를 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자는 하기의 특허청구범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경할 수 있음을 이해할 수 있을 것이다. Herein, the present invention described above has been described with reference to preferred embodiments, but those skilled in the art can variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that this can be changed.

Claims (4)

다수의 인쇄회로기판 유닛이 형성된 다수의 스트립과 상기 스트립을 구분 짓도록 상기 다수의 스트립 사이와 상기 스트립의 외곽부에 형성된 더미 영역을 포함하는 인쇄회로기판 패널에 있어서,A printed circuit board panel comprising a plurality of strips on which a plurality of printed circuit board units are formed and a dummy area formed between the plurality of strips and an outer portion of the strip to distinguish the strips. 외부 전원장치의 음극과 연결되는 도금 접점과 상기 인쇄회로기판 유닛 사이에 동일한 연결 길이를 갖도록 상기 더미 영역에 도금선을 형성하는 단계를 포함하는 것을 특징으로 하는 인쇄회로기판의 도금선 형성 방법.And forming a plating line in the dummy region so as to have the same connection length between the plating contact connected to the cathode of an external power supply and the printed circuit board unit. 제 1 항에 있어서,The method of claim 1, 상기 도금선은 사행 형태로 형성된 것을 특징으로 하는 인쇄회로기판의 도금선 형성 방법.The plating line is a plating line forming method, characterized in that formed in the meandering form. 제 2 항에 있어서,The method of claim 2, 상기 도금선을 형성하는 단계는 상기 도금 접점과 상기 다수의 인쇄회로기판 유닛 사이에 상기 도금선을 각각 형성하는 단계를 포함하는 것을 특징으로 하는 인쇄회로기판의 도금선 형성 방법.The forming of the plating line may include forming the plating line between the plating contact point and the plurality of printed circuit board units, respectively. 제 2 항에 있어서,The method of claim 2, 상기 도금선을 형성하는 방법은 상기 도금 접점부터 상기 더미 영역의 소정 위치의 접점까지 하나의 배선으로 연결된 제 1 배선을 형성하는 단계; 및The method of forming the plating line may include forming a first wiring connected by one wiring from the plating contact to a contact at a predetermined position of the dummy region; And 상기 접점부터 상기 각각의 인쇄회로기판 유닛까지 동일한 연결 길이를 갖는 제 2 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 인쇄회로기판의 도금선 형성 방법. Forming a second wiring having the same connection length from the contact point to each of the printed circuit board units.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101007327B1 (en) * 2009-05-08 2011-01-13 삼성전기주식회사 Printed circuit board panel
KR101066642B1 (en) * 2009-08-31 2011-09-22 삼성전기주식회사 Manufacturing method for printed circuit board
TWI416687B (en) * 2010-12-28 2013-11-21 Powertech Technology Inc Substrate strip with thinned plating layer at mold gate
KR20170061501A (en) 2015-11-26 2017-06-05 삼성전기주식회사 Printed circuit board panel
US9793034B2 (en) 2014-06-24 2017-10-17 Samsung Electronics Co., Ltd. Semiconductor module having a tab pin with no tie bar

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02125497A (en) * 1988-11-04 1990-05-14 Toshiba Corp Printed circuit board
JPH11340609A (en) * 1998-05-26 1999-12-10 Eastern Co Ltd Manufacture of printed wiring board and manufacture of unit wiring board
JP2002289988A (en) * 2001-03-27 2002-10-04 Fujitsu Ltd Wiring board and method of cutting the same
JP2005209761A (en) * 2004-01-21 2005-08-04 Sumitomo Metal Electronics Devices Inc Multi-molded wiring board
US7181837B2 (en) * 2004-06-04 2007-02-27 Micron Technology, Inc. Plating buss and a method of use thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101007327B1 (en) * 2009-05-08 2011-01-13 삼성전기주식회사 Printed circuit board panel
KR101066642B1 (en) * 2009-08-31 2011-09-22 삼성전기주식회사 Manufacturing method for printed circuit board
US8253032B2 (en) 2009-08-31 2012-08-28 Samsung Electro-Mechanics Co., Ltd. Printed circuit board strip and panel
TWI416687B (en) * 2010-12-28 2013-11-21 Powertech Technology Inc Substrate strip with thinned plating layer at mold gate
US9793034B2 (en) 2014-06-24 2017-10-17 Samsung Electronics Co., Ltd. Semiconductor module having a tab pin with no tie bar
KR20170061501A (en) 2015-11-26 2017-06-05 삼성전기주식회사 Printed circuit board panel

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