TWI416687B - Substrate strip with thinned plating layer at mold gate - Google Patents
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本發明係有關於半導體封裝裝置之部件,特別係有關於一種薄化注澆口表面電鍍層之基板條結構。The present invention relates to components of a semiconductor package device, and more particularly to a substrate strip structure for thinning a surface of a gate.
按,基板條常運用於大量生產半導體封裝製程,作為晶片載板。以往在製作基板條的線路時,除了在基板條之植球面形成有用以電性連接之線路之外,亦會在基板條之模封面形成與注澆口對應之金屬層,以便於在模封作業之後分離基板條與注澆口之外的的廢膠體,有助於脫模動作之進行。一般而言,在基板條之線路與注澆口金屬層製作完成之後,會再於基板條兩表面上各形成一防銲層(solder mask),以覆蓋線路與電鍍線,但顯露出位於植球面之線路層之接墊與位於模封面之注澆口金屬層。其中,線路層之接墊與注澆口金屬層皆以所需的電鍍線連接,可提供一電位,以對接墊與注澆口金屬層進行電鍍製程。然而,由於注澆口金屬層與其連接之電鍍層皆不屬於半導體封裝構造之內部元件,而是僅為了脫模動作能夠順利進行而設置。因此,形成於注澆口金屬層上之電鍍層厚度為影響電鍍製程之成本因素之一。According to the substrate strip, it is often used in mass production of semiconductor packaging processes as a wafer carrier. In the past, when the circuit of the substrate strip was fabricated, in addition to forming a circuit for electrically connecting the ball-forming surface of the substrate strip, a metal layer corresponding to the gate is formed on the mold cover of the substrate strip to facilitate the molding. The separation of the substrate strip and the waste colloid other than the sprue after the operation facilitates the demolding operation. Generally, after the circuit of the substrate strip and the metal layer of the gate metal are completed, a solder mask is formed on both surfaces of the substrate strip to cover the line and the plating line, but the substrate is exposed. The pad of the spherical circuit layer and the metal layer of the gate of the mold cover. Wherein, the pad of the circuit layer and the metal layer of the gate are connected by a required electroplating line, and a potential can be provided to perform an electroplating process on the butt pad and the gate metal layer. However, since the gate metal layer and the plating layer connected thereto are not internal components of the semiconductor package structure, they are provided only for the smooth release operation. Therefore, the thickness of the plating layer formed on the gate metal layer is one of the cost factors affecting the plating process.
如美國專利編號US 6,861,764 B2號「WIRING SUBSTRATE HAVING POSITION INFORMATION」,揭示一種習知基板條,以無電鍍銅方式形成一導電層,使得該導電層能披覆於基板條之上下表面。接著,經曝光顯影製程,以濕蝕刻方式圖案化該導電層以形成包含電鍍線之線路結構,該線路結構另包含用以連接銲球之接墊。再覆蓋防銲層於導電層之上,並圖案化該防銲層以顯露出部分之導電層,其中顯露之部分包含了位在不同表面之接墊與注澆口金屬層,注澆口金屬層位於基板條之一側邊並在由複數個基板單元所構成之模封區域之外。之後,以電鍍方式形成一鎳金層(即電鍍層),使其形成於接墊與注澆口金屬層上,藉由鎳金層之設置可防止由銅材質之導電層的顯露表面發生氧化,亦可增加銲接時的接合強度。然而,在同一電鍍步驟中在注澆口金屬層上之鎳金層與在接墊上之鎳金層通常具有相同之厚度,在注澆口金屬層上之鎳金層在封膠完成後皆會被視為廢料而被切除。因此,若能控制形成於注澆口金屬層上之鎳金層的厚度,將可有效降低成本。For example, U.S. Patent No. 6,861,764 B2, "WIRING SUBSTRATE HAVING POSITION INFORMATION", discloses a conventional substrate strip in which a conductive layer is formed by electroless copper plating so that the conductive layer can be applied over the lower surface of the substrate strip. Then, through the exposure and development process, the conductive layer is patterned by wet etching to form a wiring structure including a plating line, and the wiring structure further includes a pad for connecting the solder balls. The solder resist layer is overlaid on the conductive layer, and the solder resist layer is patterned to expose a portion of the conductive layer, wherein the exposed portion includes the pad and the gate metal layer on different surfaces, and the gate metal The layer is located on one side of the substrate strip and outside of the mold region formed by the plurality of substrate units. Thereafter, a nickel gold layer (ie, a plating layer) is formed by electroplating to be formed on the pad and the gate metal layer, and the nickel gold layer is disposed to prevent oxidation of the exposed surface of the copper conductive layer. It can also increase the joint strength at the time of welding. However, the nickel-gold layer on the gate metal layer in the same plating step usually has the same thickness as the nickel-gold layer on the pad, and the nickel-gold layer on the gate metal layer will be after the sealing is completed. It is cut off as a waste. Therefore, if the thickness of the nickel gold layer formed on the gate metal layer can be controlled, the cost can be effectively reduced.
有鑒於此,本發明之主要目的係在於提供一種薄化注澆口表面電鍍層之基板條結構,可薄化於注澆口金屬層上之電鍍層厚度,但仍保持封裝件主動區上之電鍍層有足夠的厚度,從而降低基板條成本。In view of the above, the main object of the present invention is to provide a substrate strip structure for thinning the surface of a gate casting surface, which can be thinned on the thickness of the plating layer on the gate metal layer, but still maintain the active area of the package. The plating layer is thick enough to reduce the cost of the substrate strip.
本發明之次一目的係在於提供一種薄化注澆口表面電鍍層之基板條結構,使得注澆口金屬層上之電鍍層厚度向內遞減。A second object of the present invention is to provide a substrate strip structure for thinning a surface of a gate casting surface such that the thickness of the plating layer on the gate metal layer is decreased inward.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種薄化注澆口表面電鍍層之基板條結構,主要包含一基板條本體、一注澆口金屬層、一圖案化金屬層、一曲折電鍍線、一第一電鍍層以及一第二電鍍層。該基板條本體內係形成有複數個一體構成且呈矩陣排列之基板單元。該注澆口金屬層係設於該基板條本體之一第一表面上。該圖案化金屬層係設於該基板條本體之一第二表面上,該圖案化金屬層係包含有複數個電鍍線匯流排、複數個電鍍導線與複數個接墊,其中該些電鍍線匯流排係設置於該些基板單元之外,而該些電鍍導線與該些接墊係設置於該些基板單元內,並且藉由該些電鍍導線電性連接該些電鍍線匯流排至該些接墊。該曲折電鍍線係設於該基板條本體之該第一表面上並連接至該注澆口金屬層。該第一電鍍層係形成於該注澆口金屬層上。該第二電鍍層係形成於該些接墊上,藉由該曲折電鍍線使該第一電鍍層之厚度係小於該第二電鍍層之厚度。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a substrate strip structure for thinning a surface of a gate pouring surface, which mainly comprises a substrate strip body, a gate metal layer, a patterned metal layer, a zigzag plating line, a first plating layer and a first Two electroplated layers. The substrate strip body is formed with a plurality of substrate units integrally formed and arranged in a matrix. The gate metal layer is disposed on a first surface of the substrate strip body. The patterned metal layer is disposed on a second surface of the substrate strip body, and the patterned metal layer comprises a plurality of electroplated wire bus bars, a plurality of plated wires and a plurality of pads, wherein the plated wires are converged The galvanic wires are disposed outside the substrate units, and the plating wires and the pads are disposed in the substrate units, and the plating wires are electrically connected to the wires by the plating wires. pad. The zigzag plating line is disposed on the first surface of the substrate strip body and connected to the gate metal layer. The first plating layer is formed on the gate metal layer. The second plating layer is formed on the pads, and the thickness of the first plating layer is smaller than the thickness of the second plating layer by the zigzag plating line.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述的薄化注澆口表面電鍍層之基板條結構中,該第一電鍍層與該第二電鍍層係可由同一電鍍製程所形成。In the foregoing substrate strip structure for thinning the gate surface plating layer, the first plating layer and the second plating layer may be formed by the same plating process.
在前述的薄化注澆口表面電鍍層之基板條結構中,該曲折電鍍線係可位於該些基板單元與該注澆口金屬層之間。In the foregoing substrate strip structure for thinning the gate surface plating layer, the zigzag plating line may be located between the substrate unit and the gate metal layer.
在前述的薄化注澆口表面電鍍層之基板條結構中,該曲折電鍍線係可為一波形曲折之電鍍線框,並圍繞在該些基板單元之外。In the foregoing substrate strip structure for thinning the gate surface plating layer, the zigzag plating line may be a corrugated electroplated wire frame and surround the substrate units.
在前述的薄化注澆口表面電鍍層之基板條結構中,該曲折電鍍線係可藉由複數個等距排列之短導線並聯至該注澆口金屬層。In the foregoing substrate strip structure for thinning the gate surface plating layer, the meander plating line may be connected in parallel to the gate metal layer by a plurality of equidistantly arranged short wires.
在前述的薄化注澆口表面電鍍層之基板條結構中,可另包含有一第一防銲層,係形成於該基板條本體之該第一表面上,以覆蓋該曲折電鍍線但顯露該注澆口金屬層。In the foregoing substrate strip structure for thinning the gate surface plating layer, a first solder resist layer may be further formed on the first surface of the substrate strip body to cover the zigzag plating line but revealing the Note the gate metal layer.
在前述的薄化注澆口表面電鍍層之基板條結構中,可另包含有一第二防銲層,係形成於該基板條本體之該第二表面上,以覆蓋該些電鍍線匯流排與該些電鍍導線但顯露該些接墊。In the foregoing substrate strip structure for thinning the gate surface plating layer, a second solder resist layer may be further formed on the second surface of the substrate strip body to cover the plating line bus bars and The electroplated wires are exposed but the pads are exposed.
在前述的薄化注澆口表面電鍍層之基板條結構中,該第一防銲層係可具有一開孔,以顯露該第一表面在該些基板單元內之部位。In the foregoing substrate strip structure for thinning the gate surface plating layer, the first solder resist layer may have an opening to expose a portion of the first surface in the substrate unit.
由以上技術方案可以看出,本發明之薄化注澆口表面電鍍層之基板條結構,具有以下優點與功效:It can be seen from the above technical solution that the substrate strip structure of the thinned gate surface plating layer of the present invention has the following advantages and effects:
一、可藉由將曲折電鍍線連接至注澆口金屬層之特定組合關係作為其中之一技術手段,由於曲折電鍍線之長度較長,所以可藉由曲折電鍍線使形成於注澆口金屬層之第一電鍍層厚度小於形成於圖案化金屬層之接墊之第二電鍍層厚度。因此,可薄化於注澆口金屬層上之電鍍層厚度,但仍保持封裝件主動區上之電鍍層有足夠的厚度,從而降低基板條成本。1. A specific combination of the zigzag electroplating lines connected to the gate metal layer can be used as one of the technical means. Since the zigzag electroplating line has a long length, the metal can be formed in the gate metal by the zigzag electroplating line. The thickness of the first plating layer of the layer is less than the thickness of the second plating layer formed on the pads of the patterned metal layer. Therefore, the thickness of the plating layer on the gate metal layer can be thinned, but the plating layer on the active region of the package is maintained to have a sufficient thickness, thereby reducing the cost of the substrate strip.
二、可藉由曲折電鍍線之特定組合關係作為其中之一技術手段,由於曲折電鍍線係可位於基板單元與注澆口金屬層之間,進而減少通過曲折電鍍線之電流量,故可使注澆口金屬層上之電鍍層厚度向內遞減。Second, the specific combination relationship of the zigzag electroplating line can be used as one of the technical means, since the zigzag electroplating line can be located between the substrate unit and the gate metal layer, thereby reducing the amount of current passing through the zigzag electroplating line, The thickness of the plating layer on the gate metal layer decreases inward.
以下將配合所附圖示詳細說明本發明之實施例,然應注意的是,該些圖示均為簡化之示意圖,僅以示意方法來說明本發明之基本架構或實施方法,故僅顯示與本案有關之元件與組合關係,圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製,某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理,以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計,詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之一具體實施例,一種薄化注澆口表面電鍍層之基板條結構舉例說明於第1圖繪示其第一表面之上視示意圖、第2圖繪示其第一表面之局部放大示意圖、第3圖繪示其第二表面之局部放大示意圖以及第4A至4C圖之局部截面示意圖。該薄化注澆口表面電鍍層之基板條結構100係主要包含一基板條本體110、一注澆口金屬層120、一圖案化金屬層130、一曲折電鍍線140、一第一電鍍層150與一第二電鍍層160。According to an embodiment of the present invention, a substrate strip structure for thinning a gate surface plating layer is illustrated in FIG. 1 , which is a top view of the first surface thereof, and FIG. 2 illustrates a portion of the first surface thereof. FIG. 3 is a partially enlarged schematic view showing a second surface thereof and a partial cross-sectional view of FIGS. 4A to 4C. The substrate strip structure 100 for thinning the gate surface plating layer mainly comprises a substrate strip body 110, a gate metal layer 120, a patterned metal layer 130, a meandering plating line 140, and a first plating layer 150. And a second plating layer 160.
請參閱第1圖所示,該基板條本體110內係形成有複數個一體構成且呈矩陣排列之基板單元111,該些基板單元111係為保留於半導體封裝構造內的基板部位,用以承載與電性連接晶片。該些基板單元111之間係定義出複數個縱橫交錯的切割道(如圖中虛線所示),並在模封之後可依據該些切割道切割該基板條本體110,依該些基板單元111的大小分離成各式半導體封裝構造。詳細而言,如第4A至4C圖所示,該基板條本體110係具有一第一表面112與一第二表面113,並且該第一表面112與該第二表面113係為該基板條本體110兩相對應之表.面。其中,該第一表面112係作為提供予封膠體形成之模封表面,而該第二表面113係作為對外電性連接之植球面。在一較佳實施例中,該基板條本體110之材料係可選用高分子樹脂材料,例如:FR-4環氧樹脂(FR-4 epoxy)。或者,為了適合特殊應用需求,亦可選用其它高性能的樹脂材料,例如:聚亞醯胺(PI)樹脂、三氮雜苯雙馬來醯亞胺(BT)樹脂。此外,該基板條本體110係可另具有複數個中央槽孔114,其係對準在該些基板單元111之中央部位,並且該些中央槽孔係由該第一表面112貫穿至該第二表面113,用以作為打線連接之通道,以適用於窗口型球格陣列封裝。Referring to FIG. 1 , a plurality of integrally formed and matrix-arranged substrate units 111 are formed in the substrate strip body 110. The substrate units 111 are substrate portions retained in the semiconductor package structure for carrying The wafer is electrically connected. Between the substrate units 111, a plurality of criss-crossing dicing streets (shown by broken lines in the figure) are defined, and after the molding, the substrate strip body 110 can be cut according to the dicing lines, according to the substrate units 111. The size is separated into various semiconductor package configurations. In detail, as shown in FIGS. 4A to 4C , the substrate strip body 110 has a first surface 112 and a second surface 113 , and the first surface 112 and the second surface 113 are the substrate strip body. 110 two corresponding tables. Wherein, the first surface 112 serves as a molding surface for providing a sealant, and the second surface 113 serves as a spherical surface for external electrical connection. In a preferred embodiment, the material of the substrate strip body 110 may be a polymer resin material such as FR-4 epoxy. Alternatively, other high performance resin materials such as polyammonium (PI) resin and triazapine bismuthimide (BT) resin may be used to suit specific application requirements. In addition, the substrate strip body 110 can further have a plurality of central slots 114 aligned with the central portion of the substrate units 111, and the central slots are penetrated by the first surface 112 to the second The surface 113 is used as a channel for wire bonding to be suitable for a window type ball grid array package.
請參閱第1、2、4A及4B圖所示,該注澆口金屬層120係設於該基板條本體110之該第一表面112上。該注澆口金屬層120的材質可為銅。在一較佳實施例中,該注澆口金屬層120係配置於該基板條本體110預定執行注澆作業之一側邊,通常是在該些基板單元111之外,並且具有不被防銲層覆蓋之表面,該表面更形成有厚度為H1之該第一電鍍層150。待在上下模具合模之後可對應至模具注澆口之位置,故在注澆作業完成後可藉由該注澆口金屬層120及其表面的該第一電鍍層150之設置,可防止封膠體全面黏固於該基板條本體110之側邊,而有助於脫模作業之進行。更具體地,如第4A與4B圖所示,該薄化注澆口表面電鍍層之基板條結構100係可另包含有一第一防銲層171,係形成於該基板條本體110之該第一表面112上,以覆蓋該曲折電鍍線140但顯露該注澆口金屬層120,故可防止該第一電鍍層150形成於該曲折電鍍線140,更能夠限制該注澆口金屬層120之被電鍍區域,進而免除不必要之電鍍材料浪費。此外,該第一防銲層171係可具有一開孔173,以顯露該第一表面112在該些基板單元111內之部位(如第1圖所示),而藉由該開孔173之設置,更能夠增加該些基板單元111與模封膠體之間的結合力。Referring to FIGS. 1, 2, 4A and 4B, the gate metal layer 120 is disposed on the first surface 112 of the substrate strip body 110. The material of the gate metal layer 120 may be copper. In a preferred embodiment, the gate metal layer 120 is disposed on one side of the substrate strip body 110 for performing a pouring operation, usually outside the substrate units 111, and has no solder resist. The surface of the layer is covered with the first plating layer 150 having a thickness H1. After the upper and lower molds are clamped, the position corresponding to the mold pouring gate can be corresponding, so that the sealing metal layer 120 and the surface of the first plating layer 150 can be prevented from being sealed after the pouring operation is completed. The colloid is fully adhered to the side of the substrate strip body 110 to facilitate the demolding operation. More specifically, as shown in FIGS. 4A and 4B, the substrate strip structure 100 of the thinned gate surface plating layer may further include a first solder resist layer 171 formed on the substrate strip body 110. A surface 112 is formed to cover the meandering plating line 140 but the gate metal layer 120 is exposed. Therefore, the first plating layer 150 can be prevented from being formed on the meandering plating line 140, and the gate metal layer 120 can be further restricted. The area to be plated, thereby eliminating unnecessary waste of plating materials. In addition, the first solder resist layer 171 may have an opening 173 to expose a portion of the first surface 112 in the substrate unit 111 (as shown in FIG. 1 ), and the opening 173 The setting is more capable of increasing the bonding force between the substrate unit 111 and the molding compound.
再如第4C圖所示,該第二電鍍層160係形成於該圖案化金屬層130之接墊133上。請參閱第3圖所示,其繪示出該基板條本體110之一第二表面113,以完整呈現該圖案化金屬層130於該第二表面113上之配置情形,故上述第二電鍍層省略而未顯示於第3圖中。由第3圖並對照第4C圖可知,該圖案化金屬層130係設於該基板條本體110之該第二表面113上,也就是說,該圖案化金屬層130與該注澆口金屬層120係配置於該基板條本體110之不同表面。其中,該圖案化金屬層130係包含有複數個電鍍線匯流排131、複數個電鍍導線132與複數個接墊133,表示上述所列元件是屬於相同材質的同一層線路結構。其中該些電鍍線匯流排131係設置於該些基板單元111之外,例如:本實施例中,該些電鍍線匯流排131位於該基板條本體在該些基板單元111之間之切割道內;在不同實施例中,電鍍線匯流排亦可設置於貫穿該些中央槽孔114之位置。該些電鍍線匯流排131之型態除了直線也可以是波形曲折或「之」形曲折。而該些電鍍導線132與該些接墊133係設置於該些基板單元111內,並且該些電鍍導線132更延伸連接至該些電鍍線匯流排131,藉由該些電鍍導線132電性連接該些電鍍線匯流排131至該些接墊133。故該些電鍍線匯流排131係作為電鍍接墊時的主要導線,用以傳遞電流至該些基板單元111內,並且經由該些電鍍導線132將電流導通至該些接墊133。在一較佳型態中,如第4C圖所示,在該基板條本體110上形成該圖案化金屬層130之後,可另形成一第二防銲層172於該第二表面113上,以覆蓋該些電鍍線匯流排131與該些電鍍導線132,並且該第二防銲層172係具有複數個開口,用以顯露出該些接墊133。因此,藉由該第二防銲層172之設置,可防止該第二電鍍層160形成於該些電鍍線匯流排131與該些電鍍導線132上,進而降低製造成本。其中,該第二防銲層172之開口係可小於該些接墊133,使該些接墊133為銲罩界定墊(solder mask defined,SMD)。或者,該第二防銲層172之開口亦可大於該些接墊133,使該些接墊133係為非銲罩界定墊(non-solder mask defined,SMD)。Further, as shown in FIG. 4C, the second plating layer 160 is formed on the pads 133 of the patterned metal layer 130. Referring to FIG. 3, a second surface 113 of the substrate strip body 110 is illustrated to completely present the arrangement of the patterned metal layer 130 on the second surface 113. It is omitted and is not shown in FIG. As shown in FIG. 3 and FIG. 4C, the patterned metal layer 130 is disposed on the second surface 113 of the substrate strip body 110, that is, the patterned metal layer 130 and the gate metal layer. The 120 series are disposed on different surfaces of the substrate strip body 110. The patterned metal layer 130 includes a plurality of electroplated wire bus bars 131, a plurality of plated wires 132, and a plurality of pads 133, indicating that the elements listed above are the same layer structure of the same material. The electroplating wire bus bar 131 is disposed outside the substrate unit 111. For example, in the embodiment, the electroplating wire bus bar 131 is located in the cutting path between the substrate strip body and the substrate unit 111. In various embodiments, the plating line bus bar may also be disposed at a position penetrating the central slots 114. The shape of the electroplated wire busbars 131 may be a zigzag or zigzag twist in addition to a straight line. The plated wires 132 and the pads 133 are disposed in the substrate units 111, and the plated wires 132 are further connected to the plated wire bus bars 131, and the plated wires 132 are electrically connected. The electroplated wire bus bars 131 are connected to the pads 133. Therefore, the plating wire bus bars 131 serve as main wires when the plating pads are used to transfer current into the substrate units 111, and conduct current to the pads 133 via the plating wires 132. In a preferred embodiment, as shown in FIG. 4C, after the patterned metal layer 130 is formed on the substrate strip body 110, a second solder resist layer 172 may be further formed on the second surface 113 to The plating wire bus bar 131 and the plating wires 132 are covered, and the second solder resist layer 172 has a plurality of openings for exposing the pads 133. Therefore, by the arrangement of the second solder resist layer 172, the second plating layer 160 can be prevented from being formed on the plating line bus bars 131 and the plating wires 132, thereby reducing the manufacturing cost. The opening of the second solder resist layer 172 can be smaller than the pads 133, so that the pads 133 are solder mask defined (SMD). Alternatively, the opening of the second solder resist layer 172 may be larger than the pads 133, such that the pads 133 are non-solder mask defined (SMD).
請再參閱第1與2圖所示,該曲折電鍍線140係設於該基板條本體110之該第一表面112上並連接至該注澆口金屬層120。其中,該曲折電鍍線140係可藉由複數個等距排列之短導線141並聯至該注澆口金屬層120。通常該些短導線141係配置於每一注澆口之位置。而該曲折電鍍線140為反覆彎曲,在一固定距離下比起習知直線形電鍍線的線長更長,可達到兩倍以上,進而增加了本身之電阻值,故可減少電鍍時所流入的電流量。詳細而言,該曲折電鍍線140係可作為電鍍時用以傳遞電流至該注澆口金屬層120之主要導線。在一較佳型態中,該曲折電鍍線140係可為一波形曲折之電鍍線框,並圍繞在該些基板單元111之外。尤佳地,波形曲折的方式為方形波,在每一波峰與波谷各提供兩個直角彎折,藉以產生寄生效應,進而干擾與延遲電流。在一具體型態中,該曲折電鍍線140亦可變更為梳狀或鋸齒狀之曲折型態。在電鍍製程中,由外部導線將電流經由該基板條本體110之接點導入至該基板條本體110內部時,由於該曲折電鍍線140係可位於該些基板單元111與該注澆口金屬層120之間,並且該曲折電鍍線140具有較大的電阻值,使得所導入之電流較不易往電阻值較大之該曲折電鍍線140流通,進而減少通過該曲折電鍍線140之電流量。因此,可使形成於該注澆口金屬層120上之電鍍層厚度向內朝向基板單元方向遞減,即可省去在注澆口非主要功能區的電鍍層厚度。Referring to FIGS. 1 and 2, the meandering plating line 140 is disposed on the first surface 112 of the substrate strip body 110 and connected to the gate metal layer 120. The zigzag plating line 140 can be connected in parallel to the gate metal layer 120 by a plurality of equidistantly arranged short wires 141. Usually, the short wires 141 are disposed at the position of each gate. The zigzag plating line 140 is repeatedly curved, and can be more than twice as long as the line length of the conventional linear electroplating line at a fixed distance, thereby increasing the resistance value thereof, thereby reducing the inflow of plating. The amount of current. In detail, the zigzag plating line 140 can be used as a main conductor for transferring current to the gate metal layer 120 during electroplating. In a preferred embodiment, the meandering plating line 140 can be a corrugated electroplated wire frame and surround the substrate unit 111. More preferably, the meandering of the waveform is a square wave, providing two right-angle bends at each peak and trough, thereby creating parasitic effects, which in turn interfere with the delay current. In a specific form, the meandering plating line 140 can also be changed to a comb-like or zigzag-shaped zigzag pattern. In the electroplating process, when a current is introduced into the inside of the substrate strip body 110 through the contact of the substrate strip body 110, the zigzag plating line 140 can be located in the substrate unit 111 and the gate metal layer. Between 120 and the zigzag plating line 140 has a large resistance value, so that the introduced current is less likely to flow to the zigzag plating line 140 having a larger resistance value, thereby reducing the amount of current passing through the meandering plating line 140. Therefore, the thickness of the plating layer formed on the gate metal layer 120 can be decreased inward toward the substrate unit, thereby eliminating the thickness of the plating layer in the non-primary functional region of the gate.
請參閱第4A至4C圖所示,該第一電鍍層150係形成於該注澆口金屬層120上,並且該第二電鍍層160係形成於該些接墊133上。如上所述,由於該曲折電鍍線140之長度加長,而大幅地增加本身之電阻值,所以在電鍍時所流入該曲折電鍍線140之電流量會較低於流入該圖案化電鍍層之電流量。根據電解定律、電化當量以及電流效率公式,可以導出電鍍層之厚度與電流密度係為正比關係,其中「電流密度」係指通過單位面積的電流量。所以,如果在單位面積相同之條件下,流入的電流量越大,則所形成電鍍層之厚度也越大。因此,藉由該曲折電鍍線140能使該第一電鍍層150之厚度H1(如第4A圖所示)係小於該第二電鍍層160之厚度H2(如第4C圖所示)。故而該第一電鍍層150與該第二電鍍層160在同一電鍍製程中形成,其中,該基板條結構100在單體化分離之前係多個一體配置於一基板面板(substrate panel)(圖中未繪出)中,為矩陣排列,進而使故除了可簡化電鍍製程之外,更能縮短電鍍製程之時間。Referring to FIGS. 4A-4C, the first plating layer 150 is formed on the gate metal layer 120, and the second plating layer 160 is formed on the pads 133. As described above, since the length of the meandering plating line 140 is lengthened and the resistance value thereof is greatly increased, the amount of current flowing into the meandering plating line 140 during plating is lower than the amount of current flowing into the patterned plating layer. . According to the electrolysis law, the electrochemical equivalent and the current efficiency formula, it can be derived that the thickness of the plating layer is proportional to the current density, wherein "current density" refers to the amount of current passing through a unit area. Therefore, if the amount of current flowing in is larger under the same unit area, the thickness of the formed plating layer is also larger. Therefore, the thickness H1 of the first plating layer 150 (as shown in FIG. 4A) can be made smaller than the thickness H2 of the second plating layer 160 by the meandering plating line 140 (as shown in FIG. 4C). Therefore, the first plating layer 150 and the second plating layer 160 are formed in the same electroplating process, wherein the substrate strip structure 100 is integrally disposed on a substrate panel before being singulated and separated (in the figure) In the case of unillustrated, the matrix is arranged, so that the electroplating process can be shortened in addition to simplifying the electroplating process.
綜上可知,本發明藉由將該曲折電鍍線140連接至該注澆口金屬層120之特定組合關係作為其中之一技術手段,由於該曲折電鍍線140之曲折型態而使其本身長度增加,所以可利用該曲折電鍍線140使形成於該注澆口金屬層120之該第一電鍍層150之厚度H1小於形成於該圖案化金屬層130之該些接墊133之該第二電鍍層160之厚度H2。因此,可薄化於該注澆口金屬層120上之電鍍層厚度,但仍保持封裝件主動區上之電鍍層有足夠的厚度,從而降低基板條成本。In summary, the present invention is one of the technical means for connecting the meander plating line 140 to the gate metal layer 120 by a specific combination, and the length of the zigzag plating line 140 is increased due to the meandering pattern. Therefore, the thickness H1 of the first plating layer 150 formed on the gate metal layer 120 is smaller than the second plating layer formed on the pads 133 of the patterned metal layer 130 by using the zigzag plating line 140. The thickness of 160 is H2. Therefore, the thickness of the plating layer on the gate metal layer 120 can be thinned, but the plating layer on the active region of the package is maintained to have a sufficient thickness, thereby reducing the cost of the substrate strip.
以上所述,僅是本發明的較佳實施例而已,並非對本發明作任何形式上的限制,雖然本發明已以較佳實施例揭露如上,然而並非用以限定本發明,任何熟悉本項技術者,在不脫離本發明之技術範圍內,所作的任何簡單修改、等效性變化與修飾,均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
100...薄化注澆口表面電鍍層之基板條結構100. . . Thinned substrate gate plating layer
110...基板條本體110. . . Substrate strip body
111...基板單元111. . . Substrate unit
112...第一表面112. . . First surface
113...第二表面113. . . Second surface
114...中央槽孔114. . . Central slot
120...注澆口金屬層120. . . Gate metal layer
130...圖案化金屬層130. . . Patterned metal layer
131...電鍍線匯流排131. . . Plating line bus
132...電鍍導線132. . . Electroplated wire
133...接墊133. . . Pad
140...曲折電鍍線140. . . Zigzag plating line
141...短導線141. . . Short wire
150...第一電鍍層150. . . First plating
160...第二電鍍層160. . . Second plating
171...第一防銲層171. . . First solder mask
172...第二防銲層172. . . Second solder mask
173...開孔173. . . Opening
H1...第一電鍍層厚度H1. . . First plating thickness
H2...第二電鍍層厚度H2. . . Second plating thickness
第1圖:依據本發明之一具體實施例的一種薄化注澆口表面電鍍層之基板條結構之第一表面之上視示意圖。1 is a top plan view of a first surface of a substrate strip structure for thinning a gate surface plating according to an embodiment of the present invention.
第2圖:依據本發明之一具體實施例的薄化注澆口表面電鍍層之基板條結構之第一表面之局部放大示意圖。2 is a partially enlarged schematic view showing a first surface of a substrate strip structure of a thinned gate surface plating layer according to an embodiment of the present invention.
第3圖:依據本發明之一具體實施例的薄化注澆口表面電鍍層之基板條結構之第二表面之局部放大示意圖。Figure 3 is a partially enlarged plan view showing the second surface of the substrate strip structure of the thinned gate surface plating layer according to an embodiment of the present invention.
第4A至4C圖:依據本發明之一具體實施例的薄化注澆口表面電鍍層之基板條結構之局部截面示意圖,其中(A)為注澆口金屬層的局部剖切,(B)為曲折電鍍線的局部剖切,(C)為多個接墊的局部剖切。4A to 4C are partial cross-sectional views showing a substrate strip structure of a thinned gate surface plating layer according to an embodiment of the present invention, wherein (A) is a partial cut of the gate metal layer, (B) For partial sectioning of the meandering plating line, (C) is a partial cut of a plurality of pads.
100‧‧‧薄化注澆口表面電鍍層之基板條結構100‧‧‧Thin substrate structure for thinning the surface of the gate
110‧‧‧基板條本體110‧‧‧Sheet strip body
111‧‧‧基板單元111‧‧‧Substrate unit
112‧‧‧第一表面112‧‧‧ first surface
114‧‧‧中央槽孔114‧‧‧Central slot
120‧‧‧注澆口金屬層120‧‧‧ pouring gate metal layer
140‧‧‧曲折電鍍線140‧‧‧Zigzag plating line
150‧‧‧第一電鍍層150‧‧‧First plating
173‧‧‧開孔173‧‧‧Opening
Claims (9)
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TW99146435A TWI416687B (en) | 2010-12-28 | 2010-12-28 | Substrate strip with thinned plating layer at mold gate |
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TW99146435A TWI416687B (en) | 2010-12-28 | 2010-12-28 | Substrate strip with thinned plating layer at mold gate |
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TW201227899A TW201227899A (en) | 2012-07-01 |
TWI416687B true TWI416687B (en) | 2013-11-21 |
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TW99146435A TWI416687B (en) | 2010-12-28 | 2010-12-28 | Substrate strip with thinned plating layer at mold gate |
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KR102101109B1 (en) | 2016-01-12 | 2020-04-14 | 제이에프이 스틸 가부시키가이샤 | Stainless steel sheet having Ni and O-containing coating on the surface and method for manufacturing the same |
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TWI283472B (en) * | 2005-12-30 | 2007-07-01 | Walton Advanced Eng Inc | Chip package having a slot type metal film carrying a wire-bonding chip |
KR20070118349A (en) * | 2006-06-12 | 2007-12-17 | 삼성전기주식회사 | Formation method of plating line for printed circuit board |
TWM351447U (en) * | 2008-09-25 | 2009-02-21 | Walton Advanced Eng Inc | Substrate strip for semiconductor packaging |
US20090133902A1 (en) * | 2007-11-27 | 2009-05-28 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board |
TW200929451A (en) * | 2007-12-28 | 2009-07-01 | Powertech Technology Inc | Substrate strip for semiconductor packages |
TW201004514A (en) * | 2008-07-04 | 2010-01-16 | Powertech Technology Inc | Substrate panel |
CN100592506C (en) * | 2007-12-28 | 2010-02-24 | 力成科技股份有限公司 | Non-planar base grate and method for semiconductor package using same |
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2010
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Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI283472B (en) * | 2005-12-30 | 2007-07-01 | Walton Advanced Eng Inc | Chip package having a slot type metal film carrying a wire-bonding chip |
KR20070118349A (en) * | 2006-06-12 | 2007-12-17 | 삼성전기주식회사 | Formation method of plating line for printed circuit board |
US20090133902A1 (en) * | 2007-11-27 | 2009-05-28 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board |
TW200929451A (en) * | 2007-12-28 | 2009-07-01 | Powertech Technology Inc | Substrate strip for semiconductor packages |
CN100592506C (en) * | 2007-12-28 | 2010-02-24 | 力成科技股份有限公司 | Non-planar base grate and method for semiconductor package using same |
TW201004514A (en) * | 2008-07-04 | 2010-01-16 | Powertech Technology Inc | Substrate panel |
TWM351447U (en) * | 2008-09-25 | 2009-02-21 | Walton Advanced Eng Inc | Substrate strip for semiconductor packaging |
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TW201227899A (en) | 2012-07-01 |
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