TWI416687B - Substrate strip with thinned plating layer at mold gate - Google Patents

Abstract

Disclosed is a substrate strip with thinned plating layer at mold gate. A winding plating line, for example a wire frame having wavy winding, is disposed on a molding surface of the substrate body and connected with a mold gate metal layer disposed on the same surface. A pattern metal layer including connecting pads is disposed on another surface of the substrate body. The thickness of the plating layer on the mold gate metal layer is smaller than the thickness of the plating layer on the connecting pads OF the pattern metal layer by plating through the winding plating line. Accordingly, there can be thinned thickness of plating layer on the mold gate metal layer but still kept enough thickness of plating layer on package active area to reduce cost.

Description

Thinned substrate gate plating layer

The present invention relates to components of a semiconductor package device, and more particularly to a substrate strip structure for thinning a surface of a gate.

According to the substrate strip, it is often used in mass production of semiconductor packaging processes as a wafer carrier. In the past, when the circuit of the substrate strip was fabricated, in addition to forming a circuit for electrically connecting the ball-forming surface of the substrate strip, a metal layer corresponding to the gate is formed on the mold cover of the substrate strip to facilitate the molding. The separation of the substrate strip and the waste colloid other than the sprue after the operation facilitates the demolding operation. Generally, after the circuit of the substrate strip and the metal layer of the gate metal are completed, a solder mask is formed on both surfaces of the substrate strip to cover the line and the plating line, but the substrate is exposed. The pad of the spherical circuit layer and the metal layer of the gate of the mold cover. Wherein, the pad of the circuit layer and the metal layer of the gate are connected by a required electroplating line, and a potential can be provided to perform an electroplating process on the butt pad and the gate metal layer. However, since the gate metal layer and the plating layer connected thereto are not internal components of the semiconductor package structure, they are provided only for the smooth release operation. Therefore, the thickness of the plating layer formed on the gate metal layer is one of the cost factors affecting the plating process.

For example, U.S. Patent No. 6,861,764 B2, "WIRING SUBSTRATE HAVING POSITION INFORMATION", discloses a conventional substrate strip in which a conductive layer is formed by electroless copper plating so that the conductive layer can be applied over the lower surface of the substrate strip. Then, through the exposure and development process, the conductive layer is patterned by wet etching to form a wiring structure including a plating line, and the wiring structure further includes a pad for connecting the solder balls. The solder resist layer is overlaid on the conductive layer, and the solder resist layer is patterned to expose a portion of the conductive layer, wherein the exposed portion includes the pad and the gate metal layer on different surfaces, and the gate metal The layer is located on one side of the substrate strip and outside of the mold region formed by the plurality of substrate units. Thereafter, a nickel gold layer (ie, a plating layer) is formed by electroplating to be formed on the pad and the gate metal layer, and the nickel gold layer is disposed to prevent oxidation of the exposed surface of the copper conductive layer. It can also increase the joint strength at the time of welding. However, the nickel-gold layer on the gate metal layer in the same plating step usually has the same thickness as the nickel-gold layer on the pad, and the nickel-gold layer on the gate metal layer will be after the sealing is completed. It is cut off as a waste. Therefore, if the thickness of the nickel gold layer formed on the gate metal layer can be controlled, the cost can be effectively reduced.

In view of the above, the main object of the present invention is to provide a substrate strip structure for thinning the surface of a gate casting surface, which can be thinned on the thickness of the plating layer on the gate metal layer, but still maintain the active area of the package. The plating layer is thick enough to reduce the cost of the substrate strip.

A second object of the present invention is to provide a substrate strip structure for thinning a surface of a gate casting surface such that the thickness of the plating layer on the gate metal layer is decreased inward.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a substrate strip structure for thinning a surface of a gate pouring surface, which mainly comprises a substrate strip body, a gate metal layer, a patterned metal layer, a zigzag plating line, a first plating layer and a first Two electroplated layers. The substrate strip body is formed with a plurality of substrate units integrally formed and arranged in a matrix. The gate metal layer is disposed on a first surface of the substrate strip body. The patterned metal layer is disposed on a second surface of the substrate strip body, and the patterned metal layer comprises a plurality of electroplated wire bus bars, a plurality of plated wires and a plurality of pads, wherein the plated wires are converged The galvanic wires are disposed outside the substrate units, and the plating wires and the pads are disposed in the substrate units, and the plating wires are electrically connected to the wires by the plating wires. pad. The zigzag plating line is disposed on the first surface of the substrate strip body and connected to the gate metal layer. The first plating layer is formed on the gate metal layer. The second plating layer is formed on the pads, and the thickness of the first plating layer is smaller than the thickness of the second plating layer by the zigzag plating line.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing substrate strip structure for thinning the gate surface plating layer, the first plating layer and the second plating layer may be formed by the same plating process.

In the foregoing substrate strip structure for thinning the gate surface plating layer, the zigzag plating line may be located between the substrate unit and the gate metal layer.

In the foregoing substrate strip structure for thinning the gate surface plating layer, the zigzag plating line may be a corrugated electroplated wire frame and surround the substrate units.

In the foregoing substrate strip structure for thinning the gate surface plating layer, the meander plating line may be connected in parallel to the gate metal layer by a plurality of equidistantly arranged short wires.

In the foregoing substrate strip structure for thinning the gate surface plating layer, a first solder resist layer may be further formed on the first surface of the substrate strip body to cover the zigzag plating line but revealing the Note the gate metal layer.

In the foregoing substrate strip structure for thinning the gate surface plating layer, a second solder resist layer may be further formed on the second surface of the substrate strip body to cover the plating line bus bars and The electroplated wires are exposed but the pads are exposed.

In the foregoing substrate strip structure for thinning the gate surface plating layer, the first solder resist layer may have an opening to expose a portion of the first surface in the substrate unit.

It can be seen from the above technical solution that the substrate strip structure of the thinned gate surface plating layer of the present invention has the following advantages and effects:

1. A specific combination of the zigzag electroplating lines connected to the gate metal layer can be used as one of the technical means. Since the zigzag electroplating line has a long length, the metal can be formed in the gate metal by the zigzag electroplating line. The thickness of the first plating layer of the layer is less than the thickness of the second plating layer formed on the pads of the patterned metal layer. Therefore, the thickness of the plating layer on the gate metal layer can be thinned, but the plating layer on the active region of the package is maintained to have a sufficient thickness, thereby reducing the cost of the substrate strip.

Second, the specific combination relationship of the zigzag electroplating line can be used as one of the technical means, since the zigzag electroplating line can be located between the substrate unit and the gate metal layer, thereby reducing the amount of current passing through the zigzag electroplating line, The thickness of the plating layer on the gate metal layer decreases inward.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to an embodiment of the present invention, a substrate strip structure for thinning a gate surface plating layer is illustrated in FIG. 1 , which is a top view of the first surface thereof, and FIG. 2 illustrates a portion of the first surface thereof. FIG. 3 is a partially enlarged schematic view showing a second surface thereof and a partial cross-sectional view of FIGS. 4A to 4C. The substrate strip structure 100 for thinning the gate surface plating layer mainly comprises a substrate strip body 110, a gate metal layer 120, a patterned metal layer 130, a meandering plating line 140, and a first plating layer 150. And a second plating layer 160.

Referring to FIG. 1 , a plurality of integrally formed and matrix-arranged substrate units 111 are formed in the substrate strip body 110. The substrate units 111 are substrate portions retained in the semiconductor package structure for carrying The wafer is electrically connected. Between the substrate units 111, a plurality of criss-crossing dicing streets (shown by broken lines in the figure) are defined, and after the molding, the substrate strip body 110 can be cut according to the dicing lines, according to the substrate units 111. The size is separated into various semiconductor package configurations. In detail, as shown in FIGS. 4A to 4C , the substrate strip body 110 has a first surface 112 and a second surface 113 , and the first surface 112 and the second surface 113 are the substrate strip body. 110 two corresponding tables. Wherein, the first surface 112 serves as a molding surface for providing a sealant, and the second surface 113 serves as a spherical surface for external electrical connection. In a preferred embodiment, the material of the substrate strip body 110 may be a polymer resin material such as FR-4 epoxy. Alternatively, other high performance resin materials such as polyammonium (PI) resin and triazapine bismuthimide (BT) resin may be used to suit specific application requirements. In addition, the substrate strip body 110 can further have a plurality of central slots 114 aligned with the central portion of the substrate units 111, and the central slots are penetrated by the first surface 112 to the second The surface 113 is used as a channel for wire bonding to be suitable for a window type ball grid array package.

Referring to FIGS. 1, 2, 4A and 4B, the gate metal layer 120 is disposed on the first surface 112 of the substrate strip body 110. The material of the gate metal layer 120 may be copper. In a preferred embodiment, the gate metal layer 120 is disposed on one side of the substrate strip body 110 for performing a pouring operation, usually outside the substrate units 111, and has no solder resist. The surface of the layer is covered with the first plating layer 150 having a thickness H1. After the upper and lower molds are clamped, the position corresponding to the mold pouring gate can be corresponding, so that the sealing metal layer 120 and the surface of the first plating layer 150 can be prevented from being sealed after the pouring operation is completed. The colloid is fully adhered to the side of the substrate strip body 110 to facilitate the demolding operation. More specifically, as shown in FIGS. 4A and 4B, the substrate strip structure 100 of the thinned gate surface plating layer may further include a first solder resist layer 171 formed on the substrate strip body 110. A surface 112 is formed to cover the meandering plating line 140 but the gate metal layer 120 is exposed. Therefore, the first plating layer 150 can be prevented from being formed on the meandering plating line 140, and the gate metal layer 120 can be further restricted. The area to be plated, thereby eliminating unnecessary waste of plating materials. In addition, the first solder resist layer 171 may have an opening 173 to expose a portion of the first surface 112 in the substrate unit 111 (as shown in FIG. 1 ), and the opening 173 The setting is more capable of increasing the bonding force between the substrate unit 111 and the molding compound.

Further, as shown in FIG. 4C, the second plating layer 160 is formed on the pads 133 of the patterned metal layer 130. Referring to FIG. 3, a second surface 113 of the substrate strip body 110 is illustrated to completely present the arrangement of the patterned metal layer 130 on the second surface 113. It is omitted and is not shown in FIG. As shown in FIG. 3 and FIG. 4C, the patterned metal layer 130 is disposed on the second surface 113 of the substrate strip body 110, that is, the patterned metal layer 130 and the gate metal layer. The 120 series are disposed on different surfaces of the substrate strip body 110. The patterned metal layer 130 includes a plurality of electroplated wire bus bars 131, a plurality of plated wires 132, and a plurality of pads 133, indicating that the elements listed above are the same layer structure of the same material. The electroplating wire bus bar 131 is disposed outside the substrate unit 111. For example, in the embodiment, the electroplating wire bus bar 131 is located in the cutting path between the substrate strip body and the substrate unit 111. In various embodiments, the plating line bus bar may also be disposed at a position penetrating the central slots 114. The shape of the electroplated wire busbars 131 may be a zigzag or zigzag twist in addition to a straight line. The plated wires 132 and the pads 133 are disposed in the substrate units 111, and the plated wires 132 are further connected to the plated wire bus bars 131, and the plated wires 132 are electrically connected. The electroplated wire bus bars 131 are connected to the pads 133. Therefore, the plating wire bus bars 131 serve as main wires when the plating pads are used to transfer current into the substrate units 111, and conduct current to the pads 133 via the plating wires 132. In a preferred embodiment, as shown in FIG. 4C, after the patterned metal layer 130 is formed on the substrate strip body 110, a second solder resist layer 172 may be further formed on the second surface 113 to The plating wire bus bar 131 and the plating wires 132 are covered, and the second solder resist layer 172 has a plurality of openings for exposing the pads 133. Therefore, by the arrangement of the second solder resist layer 172, the second plating layer 160 can be prevented from being formed on the plating line bus bars 131 and the plating wires 132, thereby reducing the manufacturing cost. The opening of the second solder resist layer 172 can be smaller than the pads 133, so that the pads 133 are solder mask defined (SMD). Alternatively, the opening of the second solder resist layer 172 may be larger than the pads 133, such that the pads 133 are non-solder mask defined (SMD).

Referring to FIGS. 1 and 2, the meandering plating line 140 is disposed on the first surface 112 of the substrate strip body 110 and connected to the gate metal layer 120. The zigzag plating line 140 can be connected in parallel to the gate metal layer 120 by a plurality of equidistantly arranged short wires 141. Usually, the short wires 141 are disposed at the position of each gate. The zigzag plating line 140 is repeatedly curved, and can be more than twice as long as the line length of the conventional linear electroplating line at a fixed distance, thereby increasing the resistance value thereof, thereby reducing the inflow of plating. The amount of current. In detail, the zigzag plating line 140 can be used as a main conductor for transferring current to the gate metal layer 120 during electroplating. In a preferred embodiment, the meandering plating line 140 can be a corrugated electroplated wire frame and surround the substrate unit 111. More preferably, the meandering of the waveform is a square wave, providing two right-angle bends at each peak and trough, thereby creating parasitic effects, which in turn interfere with the delay current. In a specific form, the meandering plating line 140 can also be changed to a comb-like or zigzag-shaped zigzag pattern. In the electroplating process, when a current is introduced into the inside of the substrate strip body 110 through the contact of the substrate strip body 110, the zigzag plating line 140 can be located in the substrate unit 111 and the gate metal layer. Between 120 and the zigzag plating line 140 has a large resistance value, so that the introduced current is less likely to flow to the zigzag plating line 140 having a larger resistance value, thereby reducing the amount of current passing through the meandering plating line 140. Therefore, the thickness of the plating layer formed on the gate metal layer 120 can be decreased inward toward the substrate unit, thereby eliminating the thickness of the plating layer in the non-primary functional region of the gate.

Referring to FIGS. 4A-4C, the first plating layer 150 is formed on the gate metal layer 120, and the second plating layer 160 is formed on the pads 133. As described above, since the length of the meandering plating line 140 is lengthened and the resistance value thereof is greatly increased, the amount of current flowing into the meandering plating line 140 during plating is lower than the amount of current flowing into the patterned plating layer. . According to the electrolysis law, the electrochemical equivalent and the current efficiency formula, it can be derived that the thickness of the plating layer is proportional to the current density, wherein "current density" refers to the amount of current passing through a unit area. Therefore, if the amount of current flowing in is larger under the same unit area, the thickness of the formed plating layer is also larger. Therefore, the thickness H1 of the first plating layer 150 (as shown in FIG. 4A) can be made smaller than the thickness H2 of the second plating layer 160 by the meandering plating line 140 (as shown in FIG. 4C). Therefore, the first plating layer 150 and the second plating layer 160 are formed in the same electroplating process, wherein the substrate strip structure 100 is integrally disposed on a substrate panel before being singulated and separated (in the figure) In the case of unillustrated, the matrix is arranged, so that the electroplating process can be shortened in addition to simplifying the electroplating process.

In summary, the present invention is one of the technical means for connecting the meander plating line 140 to the gate metal layer 120 by a specific combination, and the length of the zigzag plating line 140 is increased due to the meandering pattern. Therefore, the thickness H1 of the first plating layer 150 formed on the gate metal layer 120 is smaller than the second plating layer formed on the pads 133 of the patterned metal layer 130 by using the zigzag plating line 140. The thickness of 160 is H2. Therefore, the thickness of the plating layer on the gate metal layer 120 can be thinned, but the plating layer on the active region of the package is maintained to have a sufficient thickness, thereby reducing the cost of the substrate strip.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100. . . Thinned substrate gate plating layer

110. . . Substrate strip body

111. . . Substrate unit

112. . . First surface

113. . . Second surface

114. . . Central slot

120. . . Gate metal layer

130. . . Patterned metal layer

131. . . Plating line bus

132. . . Electroplated wire

133. . . Pad

140. . . Zigzag plating line

141. . . Short wire

150. . . First plating

160. . . Second plating

171. . . First solder mask

172. . . Second solder mask

173. . . Opening

H1. . . First plating thickness

H2. . . Second plating thickness

1 is a top plan view of a first surface of a substrate strip structure for thinning a gate surface plating according to an embodiment of the present invention.

2 is a partially enlarged schematic view showing a first surface of a substrate strip structure of a thinned gate surface plating layer according to an embodiment of the present invention.

Figure 3 is a partially enlarged plan view showing the second surface of the substrate strip structure of the thinned gate surface plating layer according to an embodiment of the present invention.

4A to 4C are partial cross-sectional views showing a substrate strip structure of a thinned gate surface plating layer according to an embodiment of the present invention, wherein (A) is a partial cut of the gate metal layer, (B) For partial sectioning of the meandering plating line, (C) is a partial cut of a plurality of pads.

100‧‧‧Thin substrate structure for thinning the surface of the gate

110‧‧‧Sheet strip body

111‧‧‧Substrate unit

112‧‧‧ first surface

114‧‧‧Central slot

120‧‧‧ pouring gate metal layer

140‧‧‧Zigzag plating line

150‧‧‧First plating

173‧‧‧Opening

Claims (9)

A substrate strip structure for thinning a gate surface plating layer, comprising: a substrate strip body, wherein the substrate strip body is formed with a plurality of substrate units integrally formed and arranged in a matrix; a gate metal layer is provided On a first surface of the substrate strip body; a patterned metal layer is disposed on a second surface of the substrate strip body, the patterned metal layer includes a plurality of electroplated wire bus bars, and a plurality of electroplating a wire and a plurality of pads, wherein the plating wire busbars are disposed outside the substrate units, and the plating wires and the pads are disposed in the substrate units, and the plating wires are Electrically connecting the plating wire bus bars to the pads; a zigzag plating line is disposed on the first surface of the substrate strip body and connected to the gate metal layer, wherein the zigzag plating line is a non-crossing wire that is undulatingly curved to increase its own resistance value; a first plating layer is formed on the gate metal layer; and a second plating layer is formed on the pads by The twist The line thickness of the first plating layer is less than the thickness of the lines of the second plating layer. The substrate strip structure of the thinned gate surface plating layer according to claim 1, wherein the first plating layer and the second plating layer are formed by the same plating process. The substrate strip structure for thinning a gate surface plating layer according to claim 2, wherein the meander plating line is located between the substrate unit and the gate metal layer. The substrate strip structure of the thinned gate surface plating layer according to the first, second or third aspect of the patent application, wherein the meandering plating line is a corrugated electroplated wire frame and surrounds the substrate unit outer. A substrate strip structure for thinning a gate surface plating layer according to claim 4, wherein the meandering plating line is connected in parallel to the gate metal layer by a plurality of equidistantly arranged short wires. The substrate strip structure of the thinned gate surface plating layer according to claim 4, further comprising a first solder resist layer formed on the first surface of the substrate strip body to cover the zigzag The plating line is exposed but the metal layer of the gate is exposed. The substrate strip structure of the thinned gate surface plating layer according to claim 6 of the patent application, further comprising a second solder resist layer formed on the second surface of the substrate strip body to cover the The electroplated wire is connected to the electroplated wires but the pads are exposed. The substrate strip structure of the thinned gate surface plating layer according to claim 7 , wherein the first solder resist layer has an opening to expose a portion of the first surface in the substrate unit . The substrate strip structure of the thinned gate surface plating layer according to claim 1, 2 or 3, wherein the line length of the meandering plating line is a line length of a linear plating line at a fixed distance Times the above.