200929451 九、發明說明： 【發明所屬之技術領域】 本發明係有關於印刷電路板，特別係有關於一種適 用於半導體封裝以避免裂縫生長之基板條。 【先前技術】 傳統地在半導體封裝製程中，基於成本考量與量產 需求，一般係會使用基板條（substrate)作為多個晶片之 載體’其上方之模封區係包含有複數個矩陣排列之單 元，在經過設置晶片、電性連接等半導體封裝作業後， 沿著單元周邊進行單體化切割，可獲得複數個半導體封 裝構造。而基板條在半導體封裝製程的運輸過程中，基 板條會受到應力與摩擦而容易在基板條之兩相對長側 產生裂縫，而裂縫會受應力的影響持續擴大，甚至延伸 至模封區而造成設置於該模封區内如晶片等電子元件 的損害。 Q 【發明内容】 本發月之主要目的係在於提供一種適用於半導體封 裝之基板條’藉由金屬網層之形狀與位置設計，能避免 裂縫之生長且提供較佳的應力分散性能，並可降低溼氣 進入。 本發明之次一目的係在於提供一種適用於半導體封 裝之基板條，能抑制裂缝沿著電鍍匯流條進入模封區。 本發明之另目的係在於提供一種適用於半導體封 裝之基板條，具有增加靜電放電防護（ESD)並增進裂縫 5 200929451 抑制生長之功效。 本發明之另一目的係在於提供一種適用於半導體封 裝之基板條，能避免靜電放電之破壞。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的》依據本發明一種適用於半導體封裝之基板 條主要匕含模封區以及兩侧軌。該模封區係包含複 數個單7C。該些側軌係位於該模封區之外及該基板條之 〇兩相對較長侧並於表面配設有一金屬網層，該金屬網層 係由複數條網線所組成，該些網線位於該金屬網層之邊 緣係形成為複數個獨立線端。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的基板條中’該些網線係可為直線狀並斜向 於該些較長側。 在前述的基板條中’該金屬網層係可不具有周邊框 ❹線。 在前述的基板條中’可另包含有一電鍍匯流排線， 其係延伸進入該模封區並穿過該金屬網層。 在前述的基板條中’該電鍍匯流排線在穿過該金屬 網層之線段係可為非直線，而具有至少一彎折點。 在前述的基板條中’該些網線係可包含複數個第一 平行條與複數個第二平行條，該些第一平行條與該些第 二平行條係相互交又以形成有複數個裂缝抑制交錯節 200929451 在前述的基板條中，至少一網線係可連接該電链匯 流排線，並且該些裂缝抑制交錯節點係不重叠於該電链 匯流排線。 在前述的基板條中’該些第一平行條之獨立線端與該 些第二平行條之獨立線端係可為v形連接。 在前述的基板條中’該些網線之該些獨立線端係可 不延伸至該基板條之該些較長侧。 ❾ 在前述的基板條中，可另包含一銲罩層，其係覆蓋 該金屬網層以及該些獨立線端。 在前述的基板條中，該些單元係可為球格陣列封裝 (BGA)之基板。 在前述的基板條中，該些單元係可為平面陣列封裝 (LGA)之基板。 在前述的基板條中，該些單元係可為記憶卡之晶片 載板。 © 在前述的基板條中，該金屬網層係可位於該基板條 之一上表面。 在前述的基板條中，該金屬網層係可更延伸而鄰近 位於該基板條之兩相對較短侧，以圍繞該模封區。 【實施方式】 通常基板條係一種用於承載複數個晶片以及相關電 性連接元件之印刷電路板。半導體封裝製程中會經過設 置晶片、晶片與基板間電性連接以及形成封膠體等作業 之後，再以單體化切割以製成複數個半導體封裝構造。 7 200929451 一本發明之第一具體實施例’配合參閲第1至3圖揭 示一種適用於丰练檄私壯 ^ 千等體封裝之基板條。如第1圖所示，一 種適用於半導w 导體封裳之基板條100係為長條狀，主要包 含至v模封區110以及兩側軌120。該基板條100係 具有兩相對較長側101以及兩相對與該些較長側ι〇ι垂 較短側1 0 2 ’該些較長侧i 〇丨長度大於該些較短侧 可為兩倍以上。具體而言，如第3圖所示，該基 φ板條1〇0更具有一上表面1〇3以及一下表面1〇4，該模 封區110之封膠表面係形成於該上表面i Μ並佈設有一 線路層（圖中未纷出）。通常該基板條100係可為-單 層、雙層或多層之印刷電路板。 模封區110係包含複數個單元11b在此所指「單 元」係為一種半導體封裝構造中之晶片載板並可傳輸晶 片訊號，而在經過半導體封裝製程以及單體切割作業之 後，由每一單元lu可製造完成一半導體封裝構造。非 ©限定地在本實施例中，每一模封區110概可包含十六個 單π 111或更多，該些單元lu係為矩陣方式排列於該 模封區110内，而每一單元U1係可概成矩形或正方形。 請參閱帛1圖所示，該些側軌120係位於該模封區 之外及該基板條1〇〇之該些較長側1〇1並於表面配 設有一金屬網層130’除了能增強該基板條1〇〇之該些 較長侧101之抗變形能力，並具有不影響位於該些單元 πι之内部線路之功效。請參閱第2圖所示該金屬網 層130係由複數條網線131所組成，該些網線i3i位於 8 200929451 該金屬網層130之邊緣係形成為複數個獨立線端丨32。 在此所稱之獨立線端係指除了該些網線13ι之線端相 互交會連接之情況之外，該些獨立線端132不與同一線 路層中之其它線路與框線串接。在本實施例_，該金屬 網層130係可位於該基板條1〇〇之該上表面1〇3。而該 金屬網層130係可不具有周邊框線，以避免裂縫之生 長。其中’該金屬網層130係可與該基板條ι〇〇之該上 表面103所佈設之線路層為相同材質，例如銅，立在蝕 刻形成該線路層之過程中可同時形成該金屬網層13〇， 故不會增加製程之困難度也不會增加製造成本。該些網 線131係可為直線狀並斜向於該些較長侧ι〇1，即該些 網線1 3 1既不是平行’也不是垂直於該兩較長侧1 〇 i。 請再參閱第2圖所示，該些網線131係可包含複數個第 一平行條131A與複數個第二平行條ι31Β，該些第一平 行條131A依一第一傾斜角度相互平行，該些第二平行 Q 條131B依一第二傾斜角度相互平行。該些第一平行條 131A與該些第二平行條131B係相互交又以形成有複數 個裂縫抑制交錯節點1 3 3 ’以抑制裂縫持續擴大，避免 裂缝延伸至該模封區110。較佳地，該些網線之气 些獨立線端132係可不延伸至該基板條1〇〇之該些較長 侧101，避免靜電放電之破壞❶在一具體實施例中，部 分或全部之該些第一平行條131A之獨立線端132與讀也 第二平行條131B之獨立線端132係可為v形連接（如第 圖所示）。 9 200929451 在一具體結構中，如第2圖所+ ^ 闽所不，該基板條100係可 另包含有一電鍍匯流排線14〇， 再係延伸進入該模封區 110並穿過該金屬網層130。其φ 备相 、甲，該電鍍匯流排線140 在穿過該金屬網層130之線段係 J為非直線，而具有至 少一彎折點1 4 1，避免裂縫沿著該 百項電鍍匯流排線u〇往 該模封區110生長。請再參閱第 2圖所不，至少一網線 131係可連接該電鍍匯流排線丨 # Α4〇，並且該些裂縫抑制 交錯節點133係不重疊於該電铲藤泣u太 © 电錢匯流排線140,任何瞬 間的大電流不會直接沿著該電链匯流排線14〇進入該 模封區110而會分散於該金屬網 两唧層130，故具有增加靜 電放電防護（ESD)並增進裂縫抑制生長之功效。 具體而言’請參閱第3圖所示，該基板條⑽係可 另包含-銲罩層15〇,其係形成於該上表面iG3，以覆 蓋該金屬網層130以及該些獨立線端132,故該金屬網 層：3〇可不需要電鍍層亦不會銹化。更具體而言，每一 〇單7〇111皆係具有複數個外接墊112，其係形成於該基 板條1〇〇之該下表面104,而另一銲罩層15〇係可更覆 蓋該下表面104且顯露該些外接墊112。在本實施例 中，該些單兀111係可為球格陣列封裝（BGA)之基板， 而該些外接墊U2則為陣列排列，例如陣列之球墊，並 可在該外接墊112上植設銲球以供對外銲接至一印刷 電路板（圖中未繪出）。在不同實施例中，該些單元iu 係可為平面陣列封裝（LG A)之基板，而該些外接墊112 則為陣列排列之接觸墊。或者，該些單元lu亦可為記 10 200929451 憶卡之晶片載板時，該些外接墊112則係為成排可電性 接觸之金手指，以作為電源輸送與資料交換的電性連接 端子。 因此，該金屬網層130之周邊係不具有可串接該些 網線131之周邊框線，以避免裂缝之生長，並可藉由該 些金屬網層130之設計，分散該基板條100在傳輸的過 程中’施加於該基板條100上之應力，從而避免該基板 ©條100受擠壓而產生變形，以提升該基板條100之品質 良率。因此’本發明之該基板條100不僅能避免裂縫之 生長且具有較佳的應力分散與突波電流的分散功能，並 可降低溼氣進入。即使該基板條丨00受損傷而產生裂 缝’亦可以該些金屬網層130所形成之該些裂縫抑制交 錯節點133抑制裂縫的擴大而不至進入該模封區u〇 内〇 本發明並不局限所包含之金屬網層之數量與位置。 © 在本發明之第二具體實施例中，如第4圖所示，揭示另 一種適用於半導體封裝之基板條2〇〇主要包含一模封 區2 1 0以及兩側軌220。該模封區2 1 0係包含複數個單 元211。該些側軌22〇係位於該模封區21〇之外及該基 板條200之兩相對較長侧201並於該基板條200之上表 面203配設有一金屬網層23〇，該金屬網層23〇係由複 數條網線23 1所組成，該些網線23丨位於該金屬網層 230之邊緣係形成為複數個獨立線端232，用以避免裂 縫之生長。該些網線231係可相互交叉以形成有複數個 11 200929451 裂缝抑制交錯節點233。請再參閱第4圖所示，在本實 施例中，該金屬網層230係可更延伸而鄰近位於該基板 條200之兩相對較短側2〇2,以圍繞該模封區以 提供該基板條200更完善的保護。較佳地，該些網線 231之該些獨立線端232係可不延伸至該基板條之 該些較長側2〇1與該些較短側2〇2，以避免靜電放電與 切割毛邊。 φ 乂上所述，僅疋本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 5化的等效實施W，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内》 ❹ 【圖式簡單說明】 第1圖.依據本發明之第一具體實施例，一種適用於半 導體封裝之基板條之上表面示意圖。 第2圖·依據本發明之第一具體實施例，該基板條中一 金屬網層之局部放大示意圖。 第3圖.依據本發明之第一具體實施例該基板條沿著 網線之其中之一第一平行條剖切示意圖。 第4圖.依據本發明之第二具體實施例，另一種適用於 半導體封裝之基板條之上表面示意圖。 12 200929451 【主要元件符號說明】 1〇〇基板條 103上表面 110模封區 120側軌 101較長側 104下表面 111單元 130金屬網層 131網線 131B第二平行冑132獨立線端200929451 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to printed circuit boards, and more particularly to a substrate strip suitable for use in semiconductor packages to avoid crack growth. [Prior Art] Traditionally, in the semiconductor packaging process, based on cost considerations and mass production requirements, a substrate is generally used as a carrier for a plurality of wafers. The molding region above it includes a plurality of matrix arrays. The unit is subjected to a semiconductor package operation such as a wafer or an electrical connection, and then singulated along the periphery of the cell to obtain a plurality of semiconductor package structures. While the substrate strip is transported during the semiconductor packaging process, the substrate strip is subjected to stress and friction, and cracks are easily generated on the opposite long sides of the substrate strip, and the crack is continuously affected by the stress, and even extends to the mold sealing area. Damage to electronic components such as wafers disposed in the mold region. Q [Abstract] The main purpose of this month is to provide a substrate strip suitable for semiconductor packaging. By the shape and position design of the metal mesh layer, crack growth can be avoided and better stress dispersion performance can be provided. Reduce moisture ingress. A second object of the present invention is to provide a substrate strip suitable for use in a semiconductor package that inhibits cracks from entering the molding region along the plating bus bar. Another object of the present invention is to provide a substrate strip suitable for semiconductor encapsulation which has the effect of increasing electrostatic discharge protection (ESD) and enhancing crack growth 5 200929451. Another object of the present invention is to provide a substrate strip suitable for semiconductor packaging which can avoid the destruction of electrostatic discharge. The object of the present invention and the technical problem thereof are achieved by the following technical scheme. According to the present invention, a substrate strip suitable for a semiconductor package mainly includes a molding region and both side rails. The seal zone contains a plurality of single 7Cs. The side rails are located outside the mold sealing zone and the two relatively long sides of the substrate strip and are provided with a metal mesh layer on the surface, the metal mesh layer is composed of a plurality of network wires, and the network wires are composed of a plurality of network wires. The edge of the metal mesh layer is formed as a plurality of independent line ends. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the aforementioned substrate strips, the network lines may be linear and oblique to the longer sides. In the aforementioned substrate strip, the metal mesh layer may not have a peripheral frame line. In the foregoing substrate strips, a plating bus bar may be further included which extends into the molding region and passes through the metal mesh layer. In the aforementioned substrate strip, the electroplated bus bar may be non-linear in the line segment passing through the metal mesh layer and have at least one bending point. In the foregoing substrate strips, the network lines may include a plurality of first parallel strips and a plurality of second parallel strips, and the first parallel strips and the second parallel strips intersect each other to form a plurality of Crack suppression staggered section 200929451 In the foregoing substrate strip, at least one network line can be connected to the electric chain bus line, and the crack suppression staggered nodes do not overlap the electric chain bus line. In the aforementioned substrate strips, the independent line ends of the first parallel strips and the independent line ends of the second parallel strips may be v-shaped. In the aforementioned substrate strips, the individual line ends of the network lines may not extend to the longer sides of the substrate strip. ❾ In the foregoing substrate strip, a solder mask layer may be further included to cover the metal mesh layer and the individual line ends. In the aforementioned substrate strip, the units may be a substrate of a ball grid array package (BGA). In the foregoing substrate strips, the units may be substrates of a planar array package (LGA). In the aforementioned substrate strips, the units may be wafer carriers of a memory card. © In the aforementioned substrate strip, the metal mesh layer may be located on an upper surface of the substrate strip. In the foregoing substrate strip, the metal mesh layer may extend further adjacent the two relatively shorter sides of the substrate strip to surround the mold region. [Embodiment] A substrate strip is typically a printed circuit board for carrying a plurality of wafers and associated electrical connection elements. In the semiconductor packaging process, after the wafer is placed, the wafer is electrically connected to the substrate, and the encapsulant is formed, the semiconductor package is diced to form a plurality of semiconductor package structures. 7 200929451 A first embodiment of the present invention' with reference to Figures 1 to 3 discloses a substrate strip suitable for use in a compact package. As shown in Fig. 1, a substrate strip 100 suitable for use in a semi-conducting w-conductor is elongated, and mainly includes a v-molding region 110 and side rails 120. The substrate strip 100 has two relatively long sides 101 and two opposite sides and the longer sides ι 〇 a shorter side 1 0 2 'the longer sides i 〇丨 length is greater than the shorter sides can be two More than double. Specifically, as shown in FIG. 3, the base φ slat 1 〇 0 further has an upper surface 1 〇 3 and a lower surface 1 〇 4, and the sealing surface of the molding region 110 is formed on the upper surface i There is a circuit layer (not shown in the figure). Typically, the substrate strip 100 can be a single layer, double layer or multiple layers of printed circuit board. The molding area 110 includes a plurality of units 11b. The unit referred to herein is a wafer carrier in a semiconductor package structure and can transmit wafer signals, and after passing through the semiconductor packaging process and the single-cutting operation, each The unit lu can be fabricated to complete a semiconductor package construction. In the present embodiment, each of the molding regions 110 may include sixteen single π 111 or more, and the units are arranged in a matrix manner in the molding region 110, and each unit The U1 system can be roughly rectangular or square. Referring to FIG. 1 , the side rails 120 are located outside the molding area and the longer sides 1 1 of the substrate strip 1 and are provided with a metal mesh layer 130 ′ on the surface. The deformation resistance of the longer sides 101 of the substrate strip 1 is enhanced and has the effect of not affecting the internal lines located in the cells. Referring to FIG. 2, the metal mesh layer 130 is composed of a plurality of network wires 131 located at 8 200929451. The edge of the metal mesh layer 130 is formed as a plurality of independent wire ends 32. The term "independent line end" as used herein means that the individual line ends 132 are not connected in series with the other lines in the same line layer except for the case where the line ends of the network lines 131 are connected to each other. In this embodiment, the metal mesh layer 130 may be located on the upper surface 1〇3 of the substrate strip 1〇〇. The metal mesh layer 130 may not have a peripheral frame to avoid crack growth. Wherein the metal mesh layer 130 is the same material as the circuit layer disposed on the upper surface 103 of the substrate strip, such as copper, and the metal mesh layer can be simultaneously formed during etching to form the wiring layer. 13〇, it will not increase the difficulty of the process and will not increase the manufacturing cost. The plurality of wires 131 may be linear and oblique to the longer sides ι1, i.e., the network lines 1 31 are neither parallel nor perpendicular to the longer sides 1 〇 i. Referring to FIG. 2 again, the network wires 131 may include a plurality of first parallel strips 131A and a plurality of second parallel strips 131A. The first parallel strips 131A are parallel to each other according to a first tilt angle. The second parallel Q strips 131B are parallel to each other at a second tilt angle. The first parallel strips 131A and the second parallel strips 131B are interdigitated to form a plurality of crack suppression staggered nodes 1 3 3 ' to inhibit the crack from continuing to expand, preventing the cracks from extending to the mold region 110. Preferably, the individual wire ends 132 of the network wires may not extend to the longer sides 101 of the substrate strips 1 to avoid damage of electrostatic discharge. In a specific embodiment, some or all of them The independent line ends 132 of the first parallel strips 131A and the independent line ends 132 of the read second parallel strips 131B may be v-shaped connections (as shown in the figures). 9 200929451 In a specific structure, as shown in FIG. 2, the substrate strip 100 may further comprise a plating bus bar 14〇, and then extend into the molding region 110 and pass through the metal mesh. Layer 130. The φ phase, A, the plating bus bar 140 is non-linear in the line segment J passing through the metal mesh layer 130, and has at least one bending point 141 to avoid cracks along the hundred electroplating bus The line u is grown toward the mold region 110. Please refer to FIG. 2 again. At least one network cable 131 can be connected to the plating bus bar 丨# Α4〇, and the crack suppression staggering nodes 133 do not overlap the electric shovel weeping u too © electric money confluence In the cable 140, any large current at any moment does not directly enter the die seal region 110 along the electrical bus bar 14 and is dispersed in the two layers 130 of the metal mesh, thereby increasing electrostatic discharge protection (ESD) and Improve the effect of crack inhibition growth. Specifically, as shown in FIG. 3 , the substrate strip ( 10 ) may further include a solder mask layer 15 形成 formed on the upper surface iG3 to cover the metal mesh layer 130 and the independent line ends 132 . Therefore, the metal mesh layer: 3 〇 can be etched without plating. More specifically, each of the cymbals 7 〇 111 has a plurality of circumscribing pads 112 formed on the lower surface 104 of the substrate strip 1 , and the other solder mask layer 15 can further cover the The lower surface 104 and the outer pads 112 are exposed. In this embodiment, the single turn 111 can be a substrate of a ball grid array package (BGA), and the external pads U2 are arranged in an array, such as an array of ball pads, and can be implanted on the outer pad 112. Solder balls are provided for external soldering to a printed circuit board (not shown). In various embodiments, the units iu can be substrates of a planar array package (LG A), and the external pads 112 are arrays of contact pads. Alternatively, the units lu may also be the chip carrier board of the 2009 20095151 memory card, and the external pads 112 are arranged in a row of electrically contactable gold fingers as electrical connection terminals for power transmission and data exchange. . Therefore, the periphery of the metal mesh layer 130 does not have a peripheral frame line that can be connected to the network wires 131 to avoid the growth of cracks, and the substrate strip 100 can be dispersed by the design of the metal mesh layers 130. The stress applied to the substrate strip 100 during the transfer process prevents the substrate © strip 100 from being deformed by deformation to improve the quality yield of the substrate strip 100. Therefore, the substrate strip 100 of the present invention not only prevents the growth of cracks but also has a better function of dispersing the stress dispersion and surge current, and reduces moisture ingress. Even if the substrate strip 00 is damaged to cause cracks, the crack-inhibiting staggered nodes 133 formed by the metal mesh layers 130 can suppress the expansion of the cracks without entering the mold-sealing region, and the present invention does not Limit the number and location of the metal mesh layers included. © In a second embodiment of the present invention, as shown in FIG. 4, another substrate strip 2 for a semiconductor package is disclosed which mainly includes a mold sealing region 210 and a side rail 220. The seal region 2 1 0 includes a plurality of cells 211. The side rails 22 are located outside the molding area 21〇 and the two relatively long sides 201 of the substrate strip 200, and a metal mesh layer 23 is disposed on the upper surface 203 of the substrate strip 200. The layer 23 is composed of a plurality of network wires 23 1 which are formed at the edges of the metal mesh layer 230 to form a plurality of independent wire ends 232 for avoiding the growth of cracks. The network lines 231 are cross-cored to form a plurality of 11 200929451 crack suppression interlacing nodes 233. Referring to FIG. 4 again, in the embodiment, the metal mesh layer 230 can be further extended adjacent to the two relatively shorter sides 2〇2 of the substrate strip 200 to surround the molding region to provide the The substrate strip 200 is more fully protected. Preferably, the individual line ends 232 of the network wires 231 do not extend to the longer sides 2〇1 of the substrate strips and the shorter sides 2〇2 to avoid electrostatic discharge and cutting burrs. The above description of the preferred embodiments of the present invention is not intended to limit the scope of the present invention. Any person skilled in the art can make some modifications or modifications to the equivalent implementation of the above-mentioned technical contents by using the technical content disclosed above, but the above embodiments are in accordance with the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modification, equivalent change, and modification are still within the scope of the technical solution of the present invention. ❹ [Simplified description of the drawings] FIG. 1 is a first embodiment of the present invention, a substrate suitable for a semiconductor package. A schematic diagram of the surface above the strip. Fig. 2 is a partially enlarged schematic view showing a metal mesh layer in the substrate strip in accordance with a first embodiment of the present invention. Fig. 3 is a cross-sectional view of the substrate strip along a first parallel strip of one of the network lines in accordance with a first embodiment of the present invention. Figure 4 is a schematic view of another surface of a substrate strip suitable for use in a semiconductor package in accordance with a second embodiment of the present invention. 12 200929451 [Description of main components] 1 〇〇 substrate strip 103 upper surface 110 mold sealing area 120 side rail 101 longer side 104 lower surface 111 unit 130 metal mesh layer 131 network line 131B second parallel 胄 132 independent line end
133 140 200 201 210 220 230 233 裂縫抑制交錯節點 電鍍匯流排線141彎折點 基板條 較長側 棋封區 側軌 202較短侧 211單元 金屬網層 231網線 裂縫抑制交錯節點 102較短側 112外接墊 131A第一平行條 150銲罩層 203上表面 232獨立線端133 140 200 201 210 220 230 233 Crack suppression staggered node plating bus bar 141 bending point substrate strip longer side chess seal area side rail 202 shorter side 211 unit metal mesh layer 231 network line crack suppression stagger node 102 shorter side 112 outer pad 131A first parallel strip 150 solder mask layer 203 upper surface 232 independent line end
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