KR20070075981A - Method for manufacturing of semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to improve the refresh characteristic by patterning an isolation layer after a recess gate region is formed. A recess gate region(10) is formed in the active region of a semiconductor substrate. An isolation layer(20) is formed in the semiconductor substrate. In the recess gate region, an exposure source having a lower wavelength than that of the exposure source in the isolation layer is used. A recess gate is formed on the active region. The recess gate region can be of a contact hole type, formed by a resist reflow process. ArF can be used as an exposure source in the process for forming the isolation layer.

Description

Method for manufacturing a semiconductor device

1A and 1B are layout views of a conventional isolation layer and a recess gate region.

2A to 2C are SEM images showing a patterning result of a conventional isolation layer and a recess gate region.

3 is a mask layout diagram of an isolation layer and a recess gate region in accordance with an embodiment of the present invention.

4A and 4B are SEM photographs showing mask patterning results of a recess gate region and an isolation layer according to the present invention.

5A and 5B are a plan view and a cross-sectional view showing an active region according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a device isolation film is formed after formation of a recess gate region to improve refresh operation characteristics.

In general, an isolation layer (ISO) of a semiconductor device is formed by forming a field insulating layer on a predetermined portion of a semiconductor substrate using a conventional device isolation method such as local oxide of silicon (LOCOS) or profiled groove isolation (PGI). A device isolation film is formed to define the device isolation film.

Among these device isolation methods, the LOCOS method forms a nitride film, which is an oxidation mask defining an active region, on a semiconductor substrate, is patterned by a photolithography method to expose a predetermined portion of the semiconductor substrate, and then the exposed semiconductor. The substrate is oxidized to form a field oxide film used as the device isolation region.

By the way, the LOCOS method has the advantage that the process is simple and can separate the wide and narrow areas at the same time, but the bird's beak is formed by the lateral oxidation to increase the width of the device isolation region, Reduce the effective area. In addition, when the field oxide film is formed, stress is concentrated on the edge of the oxide film due to the difference in thermal expansion coefficient, so that a crystal defect occurs in the silicon substrate, which causes a large leakage current.

In addition, the PGI method forms a groove by etching a semiconductor substrate and fills an insulating material in the groove to define an active region. Thus, the PGI method is a device isolation method that can solve the problem of encroaching the active region. There is a way.

The STI method forms a nitride film having a good etching selectivity with a semiconductor substrate on a semiconductor substrate, and forms a nitride film pattern by patterning the nitride film by a photolithography method to use the nitride film as a hard mask. The trench is formed by patterning the semiconductor substrate to a predetermined depth by using a nitride film pattern as a hard mask. Thereafter, an insulating film is embedded in the trench, followed by chemical mechanical polishing (CMP) to form a field insulating film embedded in the trench.

The device isolation film (ISO) formed by the above-described various methods applies Z-type and T-type as the design rule of the semiconductor device gradually decreases, and more recently, bar-type or island-type. An element isolation film is applied.

1A and 1B are layout views of a conventional isolation layer ISO and a recess gate area.

FIG. 1A is a layout diagram of a bar device isolation layer ISO in a 6F2 cell structure for reducing chip size. FIG. 1B is a layout diagram of a recess gate region RGA having a width of 0.06 μm.

However, unlike the conventional device isolation layer ISO and the recess gate area, the duty ratio between the line and the space is not 1: 1, unlike 8F2. It is difficult to obtain a pattern profile of size.

That is, unlike a general gate and bit line, the device isolation layer pattern has a duty ratio of 1: 0.8, and a bar having a line is larger than a space. If the spacing between the bars and bars is narrow at a certain pitch, the process margin is inevitably reduced due to factors such as contrast of incident light and diffusion of PEG than when the spacing is wide.

2A to 2C are scanning electron microscope (SEM) images showing a patterning result of a conventional device isolation layer and a recess gate region.

Here, FIG. 2A shows the patterning result of the device isolation film, FIG. 2B shows the direct patterning of the recess gate area using KrF as the exposure source, and FIG. 2C shows the recess gate area using ArF as the exposure source. It is a figure which shows the patterning result.

Although the DICD (Develop Inspection Critical Dimension) target value of the recess gate region is 60 nm, the direct patterning limit becomes 70 nm in the case of patterning using KrF as an exposure source as shown in FIG. 2B. Therefore, even when using a resist flow process, there is a problem in that a line width (CD) difference between a center region of a cell and a region adjacent to a peripheral circuit occurs.

As shown in FIG. 2C, even in the case of patterning using ArF as an exposure source, line edge roughness occurs, and the depth of focus (DoF) and exposure latitude (EL) are insufficient to assist the assist ( Assist) There is a problem that the trace of the pattern remains.

The present invention has been made to solve the above problems, and in particular, an object isolation film is formed after the formation of the recess gate region to improve the refresh operation characteristics.

In addition, an object of the present invention is to form a recess gate region of a contact hole type to ensure the cross-sectional area of the device.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises a first step of forming a recess gate region in the active region of the semiconductor substrate; Forming a device isolation film on the semiconductor substrate; And forming a recess gate on the active region.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a mask layout diagram of an isolation layer ISO and a recess gate region RGA according to the present invention.

In the process development of a memory chip using a complementary metal oxide semiconductor (CMOS) structure, as the line width (CD) of the device becomes smaller, securing a gate cross-sectional area becomes important for improving refresh characteristics.

To this end, according to the present invention, when the patterning is performed using the recess gate region 10 and the device isolation layer 20 mask set, mask layout of the recess gate region 10 is performed. After performing the patterning, the mask layout of the device isolation layer 20 is patterned.

4A and 4B are SEM (Scanning Electron Microscope) photographs showing a mask patterning result of the recess gate region 10 and the device isolation layer 20 according to the present invention.

First, as shown in FIG. 4A, patterning is performed using a contact hole type recess gate region 10 mask layout before forming the device isolation layer 20. At this time, as demonstrated in the bit line contact process of KrF, a resist flow process is performed to perform space patterning of 60 nm or less.

Next, as shown in FIG. 4B, patterning using a mask layout of the device isolation layer 20 is performed. In this case, a device isolation film mask process using ArF as an exposure source may be performed to obtain a device isolation film pattern having a desired shape.

In this case, the process of forming the recess gate region 10 is performed first, and the contact gate type recess gate region 10 is already formed under the active region of the mask of the device isolation layer 20.

Thereafter, the etching process is performed and the photoresist is removed to obtain the recess gate region 10 and the device isolation layer 20 pattern having a desired level as shown in FIG. 5A. A recess gate region 10 is formed in the active region B of the semiconductor device, and each active region B is separated by a field oxide layer 30.

FIG. 5B is a cross-sectional view of the active region B viewed in the direction AA ′ of FIG. 5A. 5B, the field oxide layer 30 is formed on both sides of the active region B, and the recess gate region 10 is formed in the upper region on the active region B in the contact hole type.

The present invention does not form the recess gate region 10 in a line / space type, but in a contact hole type.

Accordingly, the present invention implements a more precise and small space pattern using a resist flow process in performing contact hole patterning so as to obtain a desired patterning level of 60 nm. In addition, the recess gate region 10 mask may be formed on the silicon wafer of the flat plate to solve a problem related to patterning due to a step difference or a difference in lower physical properties.

As described above, the present invention provides an effect of improving the refresh operation characteristics by patterning the device isolation layer after formation of the recess gate region.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

Forming a recess gate region in an active region of the semiconductor substrate; Forming a device isolation film on the semiconductor substrate; And And forming a recess gate on the active region. The method of claim 1, wherein the recess gate region is formed in a contact hole type. The method of claim 1, wherein an exposure source having a wavelength lower than that of the device isolation layer of the second step is used for the first step recess gate region. The method of claim 3, wherein the recess gate region uses KrF as an exposure source. The method of claim 3, wherein the device isolation layer uses ArF as an exposure source. The method of claim 1, wherein the recess gate region is formed by a resist flow process.

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