KR100979368B1 - Method of fabricating semiconductor apparatus and semiconductor apparatus fabricated thereby - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor device capable of eliminating collisions or defects between a plug contact and a gate pattern and securing a process margin when forming a transistor in a highly integrated semiconductor device. A method of manufacturing a semiconductor device according to the present invention includes determining a gate region in a semiconductor substrate and defining an active region in the semiconductor substrate in which the gate region is determined.

Semiconductors, Pin Transistors, Recess Gates

Description

TECHNICAL FIELD OF THE INVENTION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE {METHOD OF FABRICATING SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS FABRICATED THEREBY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a unit cell that operates stably in a highly integrated semiconductor memory device.

In general, a semiconductor is one of a class of materials according to electrical conductivity, and is a material belonging to an intermediate region between conductors and non-conductors. In a pure state, a semiconductor is similar to non-conductor, but the electrical conductivity is increased by the addition of impurities or other operations. Such a semiconductor is used to create a semiconductor device such as a transistor by adding impurities and connecting conductors. A device having various functions made using the semiconductor device is called a semiconductor device. A representative example of such a semiconductor device is a semiconductor memory device.

The semiconductor memory device includes a plurality of unit cells composed of a capacitor and a transistor, and a double capacitor is used to temporarily store data, and a transistor is used to control signals (word lines) by using a property of a semiconductor whose electrical conductivity varies depending on the environment. Correspondingly used to transfer data between the bit line and the capacitor. The transistor is composed of three regions: a gate, a source, and a drain, and charge transfer between the source and the drain occurs according to a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region, which uses the nature of the semiconductor.

When conventional transistors are made in a semiconductor substrate, a gate is formed on the semiconductor substrate and doped with impurities on both sides of the gate to form a source and a drain. As the data storage capacity of the semiconductor memory device increases and the degree of integration increases, the size of each unit cell is required to be made smaller and smaller. That is, the design rules of the capacitors and transistors included in the unit cell have been reduced. As a result, the channel length of the cell transistors has gradually decreased, and thus, short channel effects and drain induced barrier lower (DIBL) effects have been applied to conventional transistors. Occurred, and the reliability of the operation was deteriorated. Phenomena that occur as the channel length decreases can be overcome by maintaining the threshold voltage so that the cell transistor can perform normal operation. Typically, the shorter the channel of the transistor, the higher the doping concentration of impurities in the region where the channel is formed.

However, as the design rule decreases below 100 nm, increasing the doping concentration in the channel region further increases the electric field at the storage node (SN) junction, which deteriorates the refresh characteristics of the semiconductor memory device. Cause. To overcome this problem, a cell transistor having a three-dimensional channel structure having a long channel length in the vertical direction is used to maintain the channel length of the cell transistor even if the design rule is reduced. That is, even if the channel width in the horizontal direction is short, the doping concentration can be reduced by securing the channel length in the vertical direction, thereby preventing the refresh characteristics from deteriorating. Hereinafter, a structure and a manufacturing process of a transistor including a recess gate used as a cell transistor having a three-dimensional channel structure will be described.

1A to 1E are cross-sectional views for explaining a transistor forming method of a conventional semiconductor memory device.

Referring to FIG. 1A, a pad oxide film 104 is formed on a semiconductor substrate 102, and a pad nitride film 106 is deposited on the pad oxide film 104. At this time, the pad oxide film 104 is formed to a thickness of 50 ~ 150Å, the pad nitride film 106 is deposited to a thickness of about 500 ~ 15001.

Although not shown, a photoresist film (not shown) is applied on the pad nitride film 106 to define the active region and the inactive region, and the photoresist film is patterned using an ISO mask defining the active region. Thereafter, the pad oxide film 104 and the pad nitride film 106 are etched using the patterned photoresist film, and the remaining photoresist film is removed. Subsequently, the exposed semiconductor substrate 102 is etched using the pad oxide film 104 and the pad nitride film 106 as a mask to form a trench. The trench is filled with an insulating insulating film 108 and planarized by performing a chemical mechanical polishing process (CMP) until the pad nitride film 106 is exposed. Typically, these processes are called shallow trench isolation (STI) processes.

The depth of the trench formed in the above-described STI process is formed about 2500 ~ 4000Å. In addition, the isolation insulating layer 108 filling the trench may use a material such as a spin on dielectric (SOD) layer that may be deposited by spin coating, so that the space inside the trench is not empty. In addition, in order to completely fill the trench, it is deposited to about 3000 to 7000 깊은 deeper than the depth of the trench. The chemical mechanical polishing process (CMP) performed after the trench is filled with the insulating insulating film 108 is performed until the thickness of the pad nitride film 106 remains about 40 to 60%.

As shown in FIG. 1C, the pad oxide film 104 and the pad nitride film 106 are planarized to be removed, and then an ion implantation process is performed. At this time, it is necessary to remove the natural oxide film naturally occurring during the process step, to suppress the generation of moat, and to control the effective field-oxide height (EFH), in order to effectively control the hydrofluoric acid (HF) It is cleaned using. In the case of removing the pad nitride layer 106, it is preferred to use phosphoric acid (H ₃ PO ₄₎ of the high temperature. The pad oxide film 104 may be removed only by a cleaning operation performed immediately before the ion implantation process without performing a separate removal process. Subsequently, in the ion implantation process, ions are implanted only in a desired region by using a mask corresponding to formation of a well region and a channel region.

Referring to FIG. 1D, first and second recesses 110a and 110b for forming a fin gate or a recess gate are formed in the active region and the insulating insulating layer 108 of the semiconductor substrate 102. However, since the etching selectivity of the semiconductor substrate 102 and the insulating insulating film 108 is not the same, the second recess 110b formed in the insulating insulating film 108 is more than the first recess 110a formed in the active region. It is deep and wide.

Although not shown, a gate oxide layer (not shown) is formed on the structure including the first recess 110a and the second recess 110b. In particular, the size difference between the first recess 110a and the second recess 110b is widened by a cleaning operation performed immediately before the gate oxide film is formed in the recess, and a part of the isolation insulating film 108 is removed. Sometimes. As illustrated in FIG. 1E, a gate pattern including a gate lower electrode and an upper gate electrode is embedded by filling a conductive material (for example, polysilicon) in the first recess 110a and the second recess 110b. When forming 112, a portion of the insulating insulating film 108 is removed between the second recess 110b, which is larger than the first recess 110a, and the second recess 110b during the cleaning operation. Due to the phenomenon, the gate pattern 112 may be tilted. In addition, when the inclination of the gate pattern 112 is severe, a gate bridge phenomenon may occur in which neighboring gate patterns 112 are connected.

FIG. 2 is a plan view illustrating a disadvantage of a transistor formed as shown in FIGS. 1A to 1E.

After the formation of the gate pattern 112, the landing plug contact 114 is formed between the neighboring gate patterns 112. Here, the gate pattern 112 is generally formed in both the active region and the isolation insulating film 108, and as shown, the gate pattern 112 is formed on the two regions having different sizes, and thus the gate pattern 112 is formed in the active region. The width of the gate pattern 112 formed in the isolation insulating film 108 becomes wider than the pattern 112. If the difference between the regions where the gate pattern 112 is to be formed becomes excessively large, as shown in FIG. 1E, the gate pattern 112 may be inclined.

When the landing plug contact 114 is formed between the neighboring gate patterns 112, a problem does not occur in the active region in which the gate pattern 112 is normally formed, but the landing plug is formed on the isolation insulating layer 108 in which the gate pattern 112 is large. The contact 114 and the gate pattern 112 collide with each other. That is, as the landing plug contact 114 is formed, a portion of the gate pattern 112 is collapsed.

The above-described phenomenon occurs due to the difference in etching selectivity because the recess gate is formed after defining the active region and forming the isolation insulating layer 108. In general, since the insulating insulating film 108 is made of a material of SOD, there is a high possibility that a part of the insulating insulating film 108 is lost by a cleaning process performed in each manufacturing process. Therefore, as the width of the recess formed on the insulating insulating film 108 becomes wider, a contact failure occurs when the plug contact is formed after the gate pattern is formed, and the defect is generated by connecting the gate pattern and the plug contact.

In addition, the depth of the recess formed on the insulating insulating film 108 also becomes deeper. This may affect neighboring gate patterns, which may degrade operating characteristics of the transistor.

In addition, the STI process of defining the active region and forming a trench to fill the insulating insulating layer must be excessively etched to form a trench having a depth of 2000 μs to 4000 μs. However, in this case, it is not easy to control each trench to have a constant depth, and when the trench depths are different from each other, electrical disconnection does not occur between neighboring devices, thereby degrading operation characteristics of the transistor and operating reliability of the transistor. Lowers.

In order to solve the above-mentioned problems, the present invention defines a gate region when forming a transistor in a highly integrated semiconductor device, and then defines an active region to change the size of a gate region (CD) to be positioned on the isolation insulating layer. A method of manufacturing a semiconductor device capable of minimizing collisions or defects between a plug contact and a gate pattern and securing a process margin is provided.

The present invention provides a method of manufacturing a semiconductor device comprising determining a gate region in a semiconductor substrate and defining an active region in the semiconductor substrate in which the gate region is determined.

Preferably, the step of determining a gate region on the semiconductor substrate includes forming a pad oxide film on the semiconductor substrate, applying a photoresist film on the pad oxide film, and performing an exposure process using a gate mask, and the exposure Etching the pad oxide film and the semiconductor substrate using the photosensitive film patterned by the process.

Preferably, the pad oxide film is characterized in that the deposition to a thickness of 50 ~ 150Å.

Preferably, the step of defining an active region in a semiconductor substrate having the gate region determined includes forming a pad nitride film on the semiconductor substrate having the gate region determined therein, and applying a photoresist film on the pad nitride layer and using an ISO mask. Forming a trench by etching the pad nitride film and the semiconductor substrate using the photosensitive film patterned by the exposure process, filling the trench with an isolation insulating film, until the pad nitride film is exposed. Performing a planarization process, and performing an ion implantation process on the active region.

Preferably, the depth of the trench is characterized in that 2500 ~ 4000Å.

Preferably, the pad nitride layer is characterized in that the PE-nitride layer (Plasma Enhanced Nitride).

Preferably, the pad nitride layer is made of a material having excellent step coverage.

Preferably, the isolation insulating layer is made of a spin on dielectric (SOD) material deposited by a spin coating method.

Preferably, the insulating insulating film is deposited to a thickness of 3000 ~ 7000Å for filling the trench.

Preferably, the planarization process is characterized in that the pad nitride film proceeds so that the thickness of at least 500 kPa or more remains.

Preferably, performing an ion implantation process on the active region includes removing the pad nitride layer and implanting ions using a mask corresponding to a well region and a channel region.

Preferably, the pad nitride film is characterized in that the removal using a high temperature phosphoric acid.

Preferably, the method may further include forming a gate pattern on the gate region.

The forming of the gate pattern on the gate region may include wet etching the gate region to extend the region except the active region, and dry etching the gate region to round the lower portion of the gate region. And embedding a conductive material on the gate region.

Preferably, forming a plug contact between the gate pattern.

According to an exemplary embodiment of the present invention, the gate pattern may not be tilted while the size of the recess formed in the active region and the other region is changed due to a subsequent process performed after the formation of the recess gate or the fin gate formation recess. There is an advantage.

In addition, according to the present invention, the sizes of the recesses formed on the active region and the other regions are different from each other, so that gaps between neighboring gate patterns formed on the recesses are different, thereby preventing collision with the gate pattern when the plug contacts are formed. can do.

Furthermore, the present invention does not form a gate pattern formed only in a region other than an active region that is not involved in the operation of the semiconductor device, thereby reducing the operational reliability of a transistor that may occur due to a narrow gap between neighboring gate patterns in a highly integrated semiconductor device. It has the advantage of preventing degradation.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The method of manufacturing a semiconductor device according to the present invention can be applied to a cell transistor constituting a unit cell in a semiconductor memory device. In particular, a recess gate is applied to prevent short channel effects while reducing the size of the cell transistor due to high integration. Alternatively, a method of forming a transistor including a pin gate will be described as an example.

3A to 3E are cross-sectional views and plan views illustrating a method of forming a transistor in a semiconductor device according to an embodiment of the present invention. In particular, in the transistor forming method illustrated in FIGS. 3A to 3E, defects due to a collision between a gate pattern and a plug contact generated when a portion of a recess gate or a pin gate is formed outside the active region, and electrical disconnection between neighboring gate patterns are achieved. It is a method to prevent the coupling noise (coupling noise, neighbor gate effect) caused by the loss.

Referring to FIG. 3A, a pad oxide film 304 is formed on a semiconductor substrate 302. At this time, the pad oxide film 304 is deposited to a thickness of 50 ~ 150Å. Subsequently, although not shown, the photoresist is coated and the photoresist is patterned by performing an exposure process using a gate mask. The pad oxide layer 304 and the semiconductor substrate 302 are etched using the patterned photoresist to form a recess 310a as a gate region on the semiconductor substrate 302 as shown in FIG. 3A.

For reference, in the etching process for determining the gate region, a process condition (time, etc.) that is 50% stronger than that of the conventional method should be applied to form a recess having the same size and depth as the conventional gate region. In the conventional case, the etching process is performed to form the recess in a multi-step process such as forming the recess 110b on the isolation insulating film first and then forming the recess 110a on the active region. This is because the recess 310a is formed in the semiconductor substrate 302 through a single etching process.

Referring to FIG. 3B, a pad nitride film 306 is formed on the semiconductor substrate 302 on which the gate region is formed. Thereafter, the photoresist is coated and patterned by performing an exposure process using an ISO mask. The pad nitride layer 306, the pad oxide layer 304, and the semiconductor substrate 302 exposed by the patterned photoresist are etched to form a trench 316 for device isolation.

Here, the pad nitride film 306 is deposited as thin as 600 kPa when a material having good step coverage is used, and when using a material such as PE-Plasma Enhanced Nitride, which is poor in step coverage, as in the prior art. It may be deposited. Since the recess 310a formed in the semiconductor substrate 302 typically has a width of 50 to 60 nm, the deposition thickness may be adjusted because excessive deformation of the pattern having good step coverage may result. On the other hand, when the step coverage is not good, it is not deposited on the sidewalls of the recess 310a, so that it is stacked on the upper portion of the semiconductor substrate 302 and then can be sufficiently removed through the planarization process.

The trench 316 for device isolation is etched to have a depth of 2500 ~ 4000Å can be sufficiently etched as expected depth even if the target of the etching process is reduced compared to the conventional. This is because both the active region and the inactive region are already etched by the depth corresponding to the recess 310a in FIG. 3A. Accordingly, in the etching process for forming the trench 316, the etching process conditions may not be enhanced as much as the depth of the recess 310a. As a result, in the present invention, the depth of the trench 316 for device isolation can be controlled more precisely than before, so that an electrical short between neighboring devices of the highly integrated semiconductor device can be made more clear.

Thereafter, as shown in FIG. 3C, the trench 316 is filled with the insulating insulating film 308, and the planarization is performed by performing a chemical mechanical polishing process (CMP) until the pad nitride film 306 (see FIG. 3B) is exposed. . At this time, the insulating insulating film 308 filling the trench is made of a material such as a spin on dielectric (SOD) film that can be deposited by spin coating, so that the space inside the trench is not empty, and the trench is completely filled. To do this, the deposition is carried out to 3000 ~ 7000Å deeper than the depth of the trench. The chemical mechanical polishing process (CMP) performed after the trench is filled with the insulating insulating film 308 is performed until the thickness of the pad nitride film 306 remains about 70%.

After the pad oxide film 304 and the pad nitride film 306 are planarized to be removed, an ion implantation process is performed. At this time, it is necessary to remove the natural oxide film naturally occurring during the process step, to suppress the generation of moat, and to control the effective field-oxide height (EFH), in order to effectively control the hydrofluoric acid (HF) It is cleaned using. In addition, when removing the pad nitride film 306, it is preferable to use high-temperature phosphoric acid (H ₃ PO ₄ ). The pad oxide film 304 may be removed only by a cleaning operation performed immediately before the ion implantation process without performing a separate removal process. Subsequently, in the ion implantation process, ions are implanted only in a desired region by using a mask corresponding to formation of a well region and a channel region.

Through the above-described process, in the semiconductor device according to the present invention, a recess in which the gate pattern is to be formed is formed only in the active region, and the inactive region is filled with the insulating insulating layer 308 without the recess. Therefore, it is possible to prevent the coupling noise (coupling noise, neighbor gate effect) caused by the electrical disconnection with the neighboring gate pattern which may have the structure of the conventional semiconductor device. It is possible to prevent the degradation of the operational reliability of the transistor that may occur.

Referring to FIG. 3D, the recess 310a exposed by removing the pad nitride layer 306 is wet-etched to increase the etching rate between the semiconductor substrate 302 which is an active region and the surface where the isolation insulating layer 308 abuts, thereby increasing anisotropy. Cause the effect of etching. As a result, the recess 310a is extended to a part of the isolation insulating layer 308. After wet etching, dry etching is performed to determine the depth of the recess 310b and to round the lower portion of the recess 310b.

Referring to FIG. 3E, a conductive material (eg, polysilicon) is embedded in the recess 310b to form a gate pattern 312 including a gate lower electrode and a gate upper electrode. After the formation of the gate pattern 312, the landing plug contact 314 is formed between the neighboring gate patterns 312. Unlike the related art, in the present invention, the landing plug contact 314 and the gate pattern 312 collide with each other. This doesn't happen. This is because the recess 310b for forming the gate pattern is prevented from becoming larger through a plurality of steps without forming a recess in the isolation insulating film 308.

As described above, in the present invention, the gate region is first determined before defining the active region and the inactive region in the semiconductor substrate. This ensures an electrical short circuit of neighboring devices by not forming recesses such as gate regions in the inactive regions. In addition, the insulating insulating film formed in the inactive region is excessively etched more than necessary to prevent the gate pattern from being tilted or collapsed, thereby reducing defects of the semiconductor device. Furthermore, in the present invention, distortion of the gate region can be prevented even if a pad nitride film to be deposited on a semiconductor substrate is made of a material having a low step coverage.

In addition, as in the conventional semiconductor device, a difference occurs in the size of the gate pattern formed in the active region and the inactive region, thereby preventing collision between the gate pattern and the plug contact, which may occur when a plug contact is formed between the gate patterns. have.

In addition, when forming a recess for forming a gate pattern, as shown in FIG. 3D, after the recess 310a is exposed, an additional region is removed through anisotropic etching by wet etching and dry etching is performed. The recess 310b may be expanded, the depth may be adjusted, and the lower portion may be rounded to more precisely control the structure of the recess gate or the fin gate.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1E are cross-sectional views for explaining a transistor forming method of a conventional semiconductor memory device.

2 is a plan view for explaining the disadvantages of the transistor formed as shown in Figures 1a to 1e.

3A to 3E are cross-sectional views and plan views illustrating a method of forming a transistor in a semiconductor device according to an embodiment of the present invention.

Claims (15)

Determining a gate region in the semiconductor substrate; Defining an active region in the semiconductor substrate from which the gate region is determined; And Forming a gate pattern on the gate region; Forming the gate pattern Wet etching the gate region to extend the gate region from side to side; Dry etching the gate region to round a lower portion of the gate region; And Embedding a conductive material on the gate region; Method for manufacturing a semiconductor device comprising a. The method of claim 1, Determining a gate region in the semiconductor substrate Forming a pad oxide film on the semiconductor substrate; Coating a photoresist film on the pad oxide film and performing an exposure process using a gate mask; And Etching the pad oxide film and the semiconductor substrate using the photosensitive film patterned by the exposure process. The method of claim 2, The pad oxide film is a semiconductor device manufacturing method characterized in that the deposition to a thickness of 50 ~ 150 ~. The method of claim 1, Defining an active region in the semiconductor substrate in which the gate region is determined Forming a pad nitride film on the semiconductor substrate on which the gate region is determined; Applying a photoresist film on the pad nitride film and performing an exposure process using an ISO mask; Etching the pad nitride film and the semiconductor substrate using the photosensitive film patterned by the exposure process to form a trench; Filling the trench with an isolation insulating film; Performing a planarization process until the pad nitride layer is exposed; And And performing an ion implantation process in the active region. The method of claim 4, wherein The trench has a depth of 2500 to 4000 micrometers. The method of claim 4, wherein The pad nitride film is a PE-nitride film (Plasma Enhanced Nitride) characterized in that the manufacturing method of the semiconductor device. The method of claim 4, wherein And the pad nitride layer is made of a material having excellent step coverage. The method of claim 4, wherein The isolation insulating film is a semiconductor device manufacturing method, characterized in that consisting of a spin on dielectric (SOD) material deposited by a spin coating method. The method of claim 4, wherein The isolation insulating film is deposited to a thickness of 3000 ~ 7000 Å for filling the trench. The method of claim 4, wherein And the planarization step is performed such that the pad nitride film has a thickness of at least 500 GPa or more. The method of claim 4, wherein Performing an ion implantation process in the active region Removing the pad nitride film; And Implanting ions using a mask corresponding to the well region and the channel region. The method of claim 11, The pad nitride film is removed using high temperature phosphoric acid. delete delete The method of claim 1, Forming a plug contact between the gate pattern.

Images