KR20140090447A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20140090447A
KR20140090447A KR1020130002512A KR20130002512A KR20140090447A KR 20140090447 A KR20140090447 A KR 20140090447A KR 1020130002512 A KR1020130002512 A KR 1020130002512A KR 20130002512 A KR20130002512 A KR 20130002512A KR 20140090447 A KR20140090447 A KR 20140090447A
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KR
South Korea
Prior art keywords
insulating film
film
trench
buried gate
forming
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Application number
KR1020130002512A
Other languages
Korean (ko)
Inventor
신승아
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020130002512A priority Critical patent/KR20140090447A/en
Publication of KR20140090447A publication Critical patent/KR20140090447A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device capable of preventing the occurrence of a bridge of a buried gate, the method including: forming a device isolation film in which a first insulating film is formed on a semiconductor substrate; Etching the semiconductor substrate between the device isolation films to form a trench; Forming a buried gate to fill a portion of the trench; Forming a second insulating film on the buried gate to fill the rest of the trench; Recessing the first insulating film of the isolation film; And forming a third insulating film on the recessed first insulating film to fill the remaining portion of the device isolation film, thereby removing the conductive residue material while simultaneously removing the shim of the element isolation film, thereby preventing bridging between the buried gates .

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a semiconductor device,

This embodiment relates to a semiconductor manufacturing technique, and more specifically, to a method of manufacturing an element isolation film of a semiconductor device having a buried gate.

As the degree of integration of semiconductor devices increases, the number of design rules decreases and the pattern of semiconductor devices becomes finer. As miniaturization and high integration of a semiconductor device progresses, the overall chip area increases in proportion to an increase in memory capacity, but the area of a cell area where a semiconductor device pattern is formed is actually decreasing. Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell region, so that a fine pattern with a reduced critical dimension of the pattern must be formed.

Among semiconductor devices, a DRAM includes a plurality of unit cells including a capacitor and a transistor. Among them, a capacitor is used for temporarily storing data, and a transistor is used for transferring data between a bit line and a capacitor corresponding to a control signal (word line) by using the property of a semiconductor whose electrical conductivity changes according to an environment. A transistor consists of three regions: a gate, a source, and a drain. A charge is transferred between the source and the drain in accordance with a control signal input to the gate. The charge transfer between the source and the drain takes place through the channel region, which is based on the nature of the semiconductor.

When a conventional transistor is formed on a semiconductor substrate, a gate is formed on a semiconductor substrate and doping is performed on both sides of the gate to form a source and a drain. In this case, the region between the source and the drain under the gate becomes the channel region of the transistor. A transistor having such a horizontal channel region occupies a semiconductor substrate of a certain area. In the case of a complicated semiconductor memory device, it is difficult to reduce the total area due to a plurality of transistors included in the semiconductor memory device.

By reducing the total area of the semiconductor memory device, the number of semiconductor memory devices that can be produced per wafer can be increased and productivity is improved. Various methods have been proposed to reduce the total area of the semiconductor memory device. In place of a conventional planar gate in which one of them has a horizontal channel region, a recess is formed in the substrate and a gate is formed in the recess, thereby forming a recess in which the channel region is formed along the curved surface of the recess A buried gate is formed by embedding the entire gate in the recess in addition to the recessed gate.

The semiconductor device includes a device isolation film for insulation between adjacent unit components, and the device isolation film is formed through a shallow trench isolation (STI) process. In the STI process, trenches are formed in a substrate and an isolation material is buried in the trenches to form a device isolation film. This technology can be applied to an ultra-high-density semiconductor device fabrication process at present and beyond.

On the other hand, in the case of a cell area having a small line width due to a decrease in design rules, the device isolation film is completely buried by the liner nitride film, and a nitride film is used as a gap fill material of the device isolation film.

However, when a device isolation film is used as a nitride film, seam is inevitably generated. Furthermore, the shim of the device isolation film has a problem in that a conductive material deposited during the formation of a subsequent buried gate remains, resulting in bridge failure between buried gates.

The present embodiment provides a method of manufacturing a semiconductor device capable of preventing bridge generation of a buried gate.

A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming an isolation layer on a semiconductor substrate, the isolation layer being formed of a first insulating layer; Etching the semiconductor substrate between the device isolation films to form a trench; Forming a buried gate to fill a portion of the trench; Forming a second insulating film on the buried gate to fill the rest of the trench; Recessing the first insulating film of the isolation film; And forming a third insulating film on the recessed first insulating film to fill the remaining portion of the isolation film.

In particular, the first insulating film may include an insulating material having an etch selectivity with respect to the second insulating film, the first insulating film may include a nitride material, the second insulating film may include an oxide material, The second insulating film may include a nitride film, and the second insulating film may include an oxide film.

The third insulating layer may include an oxide layer, and the third insulating layer may include an SOD layer.

The recessing of the first insulating layer may be performed using a wet etching process using a phosphoric acid (H 3 PO 4 ) solution.

The buried gate may include a conductive material, and the buried gate may include a metal material.

This technique has the effect of preventing the bridge between the buried gates by removing the conductive residual material while simultaneously removing the shims of the device isolation film.

1 is a layout diagram showing a memory cell of a DRAM.
2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, which is taken along the line A-A 'of FIG.
3A to 3H are process cross-sectional views for explaining an example of a method of manufacturing a semiconductor device according to the present embodiment in the direction of B-B 'in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art will be able to easily understand the technical idea of the embodiment.

1 is a layout diagram showing a memory cell of a DRAM.

As shown in Fig. 1, island-shaped active regions formed in oblique directions are repeatedly arranged at regular intervals, and active regions are defined by device isolation films.

Then, a buried gate (BG) across the active region is formed, and a bit line (BL) extending in a direction crossing the buried gate is formed on the substrate.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, which is taken along the line A-A 'of FIG. 3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention, which is taken along the line B-B 'of FIG. For ease of understanding, FIGS. 2A to 2H and FIGS. 3A to 3H will be described together. Each step has the same process sequence.

As shown in Figs. 2A and 3A, a hard mask pattern 12 is formed on a semiconductor substrate 11. As shown in Fig. The semiconductor substrate 11 may comprise a silicon substrate or a silicon germanium substrate. The hard mask pattern 12 is for forming a device isolation film and a subsequent buried gate and may include a material having an etch selection ratio with respect to the semiconductor substrate 11. [

Subsequently, the first trench 13 is formed by etching the semiconductor substrate 11 with the hard mask pattern 12 as an etching barrier.

Subsequently, a sidewall oxide film 14 is formed on the sidewall and bottom of the first trench 13. The sidewall oxide film 14 may be formed by oxidizing the exposed surface of the first trench 13 or by depositing an oxide film.

Next, a first insulating film 15 for filling the first trenches 13 is formed on the sidewall oxide film 14. The first insulating layer 15 serves as a device isolation layer. The first insulating layer 15 is formed to have a thickness sufficient to fill the first trenches 13, and then the planarization process is performed on the target exposed above the hard mask pattern 12 . For example, the nitride material may include a nitride film. Hereinafter, the first insulating film 15 is referred to as an "element isolation film 15".

At this time, the shim 16 may be formed on the first trench 13 due to the characteristics of the nitride film deposition.

As shown in FIGS. 2B and 3B, the hard mask pattern 12A is patterned so that the buried gate region is opened.

Subsequently, the patterned hard mask pattern 12A is etched to form the second trench 17 by etching the semiconductor substrate 11 with an etching barrier.

As shown in Figs. 2C and 3C, a gate insulating film 18 is formed on the sidewalls and bottom of the second trench 17. The gate insulating film 18 may be formed through an oxidation process or a deposition process, and the gate insulating film 18 may include an oxide such as a silicon oxide film.

Then, a conductive film 19 for filling the second trenches 17 is formed on the gate insulating film 18. The conductive film 19 is for forming a buried gate and can be formed to a thickness enough to embed the second trench 17 therein. The conductive film 19 may include a material serving as an electrode. The conductive film 19 may include a low resistance material, for example, a tungsten film. Alternatively, the conductive film 19 may include a laminated structure of a diffusion barrier film and a metal film. For example, the diffusion barrier film may comprise a titanium-containing material, and the metal film may comprise a low resistance metal. The titanium-containing material may include, for example, a titanium nitride film (TiN).

As shown in Figs. 2D and 3D, the conductive film 19 is planarized with the target from which the semiconductor substrate 11 is exposed. The planarization process may be a chemical mechanical polishing process or an etch back process.

The conductive film 19 on which planarization has proceeded is indicated by reference numeral 19A.

The conductive film 19 remains only in the second trench 17 through planarization. At this time, the conductive film deposited between the padding 16 of the device isolation film in FIG. 2D may remain as it is without being removed in the planarization process. The remaining conductive film 19, which is not removed in the planarization step, is hereinafter referred to as a "residue 19B". This residue 19B may cause bridging failure between adjacent buried gates in a subsequent process, and thus must be removed.

As shown in Figs. 2E and 3E, the conductive film 19A is recessed to form a buried gate 20 for embedding a part of the second trench 17 therein. At this time, the gate insulating film 18 may also be recessed to remain at the same height as the buried gate 20. The recessed gate insulating film 18 is shown at 18A.

After the recessing process of the conductive film 19A for forming the buried gate 20 is completed, the residue 19B deposited between the shims of the device isolation film in Fig. 2E can remain as it is without being removed. This is because the element isolation film 15 has an etching selection ratio with respect to the buried gate 20 and the line width of the core of the element isolation film 15 is narrow and it is not easy to remove the residue 19B.

A second insulating film 21 is formed to fill the remaining portion of the second trench 17 on the buried gate 20, as shown in Figs. 2F and 3F. The second insulating film 21 serves to protect oxidation and attack of the buried gate 20 from a subsequent process, and may include an insulating material.

The second insulating film 21 may include a material having an etch selection ratio with respect to the device isolation film 15. The second insulating film 21 may include, for example, an oxide material.

As shown in Figs. 2G and 3G, the device isolation film 15 is recessed to a certain depth. The recessed element isolation film 15 is denoted by 15A.

The device isolation film 15A can recess at least as deep as the depth of the shim 16 is removed, that is, to a depth sufficient to remove all of the residue 19B deposited between the shim 16.

The element isolation film 15A can be recessed by wet etching. At this time, the wet etching can be performed using a phosphoric acid (H 3 PO 4 ) solution.

As the device isolation film 15A is recessed to the depth at which the shim is removed, all of the residue 19B deposited in the shim 16 is also removed. Accordingly. Bridge defects between neighboring buried gates 20 can be prevented.

As shown in FIGS. 2h and 3h, a third insulating film 22 is formed on the recessed element isolation film 15A. The third insulating film 22 may include a material that does not generate seam and may include a spin-on dielectric (SOD) film formed by a spin-on coating method.

As described above, since the residue 19B deposited on the core of the device isolation film 15 is removed through the recess of the subsequent device isolation film 15 when the buried gate 20 is formed, the bridging defect between the neighboring buried gates 20 Can be prevented.

It is noted that the technical idea of the present embodiment has been specifically described according to the above embodiment, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. It will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the embodiment.

11: semiconductor substrate 13: first trench
14: sidewall oxide film 15A: element isolation film
22: Third insulating film

Claims (10)

Forming an element isolation film in which a first insulating film is formed on a semiconductor substrate;
Etching the semiconductor substrate between the device isolation films to form a trench;
Forming a buried gate to fill a portion of the trench;
Forming a second insulating film on the buried gate to fill the rest of the trench;
Recessing the first insulating film of the isolation film; And
Forming a third insulating film on the recessed first insulating film to fill the rest of the isolation film;
≪ / RTI >
The method according to claim 1,
Wherein the first insulating film includes an insulating material having an etch selectivity with respect to the second insulating film.
The method according to claim 1,
Wherein the first insulating film includes a nitride material, and the second insulating film includes an oxidizing material.
The method according to claim 1,
Wherein the first insulating film includes a nitride film, and the second insulating film includes an oxide film.
The method according to claim 1,
Wherein the third insulating film includes an oxide film.
The method according to claim 1,
Wherein the third insulating film comprises an SOD film.
The method according to claim 1,
Wherein the step of recessing the first insulating film comprises:
A method for fabricating a semiconductor device that proceeds with wet etching. The method according to claim 1,
Wherein the step of recessing the first insulating film comprises:
Phosphoric acid (H 3 PO 4 ) solution.
The method according to claim 1,
Wherein the buried gate comprises a conductive material.
The method according to claim 1,
Wherein the buried gate comprises a metal material.
KR1020130002512A 2013-01-09 2013-01-09 Method for manufacturing semiconductor device KR20140090447A (en)

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