KR20040025946A - Method for forming gate of semiconductor element - Google Patents
Method for forming gate of semiconductor element Download PDFInfo
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- KR20040025946A KR20040025946A KR1020020056420A KR20020056420A KR20040025946A KR 20040025946 A KR20040025946 A KR 20040025946A KR 1020020056420 A KR1020020056420 A KR 1020020056420A KR 20020056420 A KR20020056420 A KR 20020056420A KR 20040025946 A KR20040025946 A KR 20040025946A
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- gate
- poly layer
- layer
- gate electrode
- poly
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 게이트 형성 방법에 관한 것으로, 더욱 상세하게는 게이트와 콘텍이 접촉되는 영역의 실리사이드의 표면적을 증가시켜 게이트/콘텍 저항이 최소화되도록 한 반도체 소자의 게이트 형성 방법에 관한 것이다.The present invention relates to a method of forming a gate of a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device in which the gate / contact resistance is minimized by increasing the surface area of the silicide in a region where the gate is in contact with the contact.
주지와 같이, 반도체가 고집적화가 되어감에 따라 칩 사이즈는 계속 작아지고 이에 따라 폴리실리콘 게이트의 폭은 더욱 좁아지고 있다.As is well known, as semiconductors become more integrated, chip sizes continue to decrease, resulting in narrower polysilicon gate widths.
종래 기술에 따른 반도체 소자의 게이트 형성 방법을 도 1를 참조하여 설명하면, 반도체 기판(11) 상에 게이트 산화막(12)과 게이트 폴리층(13)을 형성한 다음, 포토레지스트 패턴(도시하지 않음)을 이용한 노광 및 식각 공정으로 게이트 폴리층(13)을 선택적으로 제거하여 게이트 전극을 형성한다.A method of forming a gate of a semiconductor device according to the prior art will be described with reference to FIG. 1. After forming the gate oxide film 12 and the gate poly layer 13 on the semiconductor substrate 11, a photoresist pattern (not shown) Gate gate layer is formed by selectively removing the gate poly layer 13 by an exposure and etching process using the?).
게이트 전극이 형성된 전체구조 상에 질화막(14)을 형성한 후에 질화막 식각 공정을 진행하면 게이트 폴리층(13)의 좌,우측면의 질화막(14)은 게이트 전극의 측벽으로 남게된다.After the nitride film 14 is formed on the entire structure on which the gate electrode is formed, the nitride film etching process is performed, and the nitride films 14 on the left and right sides of the gate poly layer 13 remain as sidewalls of the gate electrode.
전면에 실리사이드 형성 소오스를 증착한 후 어닐 공정을 수행하면 표면으로 노출된 영역에 실리사이드(15)가 형성된다.When the silicide forming source is deposited on the entire surface, the annealing process is performed to form the silicide 15 in the region exposed to the surface.
그러나, 전술한 바와 같은 종래의 게이트 형성 방법은 칩 사이즈가 작아짐에 따라 폴리실리콘 게이트의 폭은 더욱 좁아지게 되고, 좁은 폭의 폴리실리콘에 의해 실리사이드 저항이 문제가 된다.However, in the conventional gate forming method as described above, as the chip size becomes smaller, the width of the polysilicon gate becomes narrower, and the silicide resistance becomes a problem due to the narrow width of the polysilicon.
본 발명은 이와 같은 종래의 문제점을 해결하기 위하여 제안한 것으로, 게이트와 콘텍이 접촉되는 영역의 실리사이드의 표면적을 증가시켜 좁은 폭의 폴리실리콘 게이트에서도 접촉면적이 넓게되어 상대적으로 게이트/콘텍 저항이 최소화되도록 한 반도체 소자의 게이트 형성 방법을 제공하는 데 그 목적이 있다.The present invention has been proposed to solve such a conventional problem, so as to increase the surface area of the silicide in the region where the gate and the contact is in contact, so that the contact area becomes wider even in a narrow polysilicon gate so that the gate / contact resistance is relatively minimized. It is an object to provide a method for forming a gate of a semiconductor device.
이와 같은 목적을 실현하기 위한 본 발명에 따른 반도체 소자의 게이트 형성 방법은, 반도체 기판 상에 게이트 산화막을 형성한 후 전체구조 상에 게이트 폴리층을 형성하는 제 1 단계와, 상기 게이트 폴리층이 형성된 전체구조 상에 상부 폴리층을 형성한 후 상기 상부 폴리층을 선택적으로 제거하여 이후 게이트 전극이 형성될 영역에만 상기 상부 폴리층을 남기는 제 2 단계와, 상기 패터닝된 상부 폴리층을 포함한 전체구조 상에 산화막을 형성한 후 상기 산화막과 폴리층과의 선택비를 이용한 폴리 식각 공정을 실시하여 게이트 전극 형성 영역상의 가장자리에 상기산화막을 남기는 제 3 단계와, 상기 폴리 식각 공정이 진행된 전체구조에 게이트 폴리층 식각 공정을 수행하여 상기 산화막의 작용에 의해 상부의 가장자리가 돌출되고 중앙부가 오목한 형상의 게이트 전극을 형성하는 제 4 단계와, 상기 게이트 전극이 형성된 전체구조 상에 질화막을 형성한 후 상기 질화막 식각 공정을 진행하여 상기 질화막으로 상기 게이트 전극의 측벽을 형성하는 제 5 단계와, 전면에 실리사이드 형성 소오스를 증착한 후 어닐 공정을 수행하여 표면으로 노출된 영역에 실리사이드를 형성하는 제 6 단계를 포함한다.The gate forming method of a semiconductor device according to the present invention for achieving the above object comprises a first step of forming a gate poly layer on the entire structure after forming a gate oxide film on a semiconductor substrate, and the gate poly layer is formed A second step of forming an upper poly layer on the entire structure and then selectively removing the upper poly layer to leave the upper poly layer only in an area where a gate electrode is to be formed, and the overall structure including the patterned upper poly layer A third step of leaving the oxide film at an edge on the gate electrode formation region by performing a poly etching process using an oxide film and a selectivity ratio between the oxide film and the poly layer, and forming a gate poly in the entire structure in which the poly etching process is performed. By performing the layer etching process, the upper edge protrudes and the center is concave by the action of the oxide film. A fourth step of forming a gate electrode on the substrate, a fifth step of forming a nitride film on the entire structure where the gate electrode is formed, and then performing a nitride film etching process to form sidewalls of the gate electrode with the nitride film; And depositing a silicide forming source and then performing an annealing process to form silicide in an area exposed to the surface.
도 1은 종래 기술에 따라 게이트가 형성된 반도체 소자의 단면도,1 is a cross-sectional view of a semiconductor device in which a gate is formed according to the prior art;
도 2a 내지 도 2g는 본 발명에 따른 게이트 형성 방법을 설명하기 위한 공정 단면도.2A to 2G are cross-sectional views illustrating a method of forming a gate according to the present invention.
본 발명의 실시예로는 다수개가 존재할 수 있으며, 이하에서는 첨부한 도면을 참조하여 바람직한 실시예에 대하여 상세히 설명하기로 한다. 이 실시예를 통해 본 발명의 목적, 특징 및 이점들을 보다 잘 이해할 수 있게 된다.There may be a plurality of embodiments of the present invention. Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. This embodiment allows for a better understanding of the objects, features and advantages of the present invention.
도 2a 내지 도 2g는 본 발명에 따른 게이트 형성 방법을 설명하기 위한 공정 단면도이다.2A to 2G are cross-sectional views illustrating a method of forming a gate according to the present invention.
도 2a를 참조하면, 반도체 기판(101) 상에 게이트 산화막(102)을 형성하고, 전체구조 상에 게이트 폴리층(103)을 형성한 다음, 전체구조 상에 상부 폴리층(104)을 형성한다. 이후 포토레지스트 패턴(도시하지 않음)을 이용한 노광 및 식각 공정으로 상부 폴리층(104)을 선택적으로 제거하여 이후 게이트 전극이 형성될 영역에만 상부 폴리층(104)을 남긴다.Referring to FIG. 2A, the gate oxide layer 102 is formed on the semiconductor substrate 101, the gate poly layer 103 is formed on the entire structure, and then the upper poly layer 104 is formed on the entire structure. . Thereafter, the upper poly layer 104 is selectively removed by an exposure and etching process using a photoresist pattern (not shown), thereby leaving the upper poly layer 104 only in the region where the gate electrode is to be formed.
도 2b를 참조하면, 패터닝된 상부 폴리층(104)을 포함한 전체구조 상에 산화막(105)을 형성한다.Referring to FIG. 2B, an oxide film 105 is formed on the entire structure including the patterned upper poly layer 104.
도 2c를 참조하면, 산화막(105)과 폴리층(103, 104)과의 선택비를 이용한 폴리 식각 공정을 실시한다. 이때, 폴리층(103, 104)과 산화막(105)은 약 1.5:1 정도의 선택비를 가지므로 선택비의 차이에 의해 게이트 전극 형성 영역상의 가장자리에 산화막(105)이 남게된다.Referring to FIG. 2C, a poly etching process using the selectivity between the oxide film 105 and the poly layers 103 and 104 is performed. At this time, since the poly layers 103 and 104 and the oxide film 105 have a selectivity of about 1.5: 1, the oxide film 105 remains at the edge on the gate electrode formation region due to the difference in selectivity.
도 2d를 참조하면, 다시 "F"기를 베이스로 한 식각을 진행하면 산화막(105)이 제거되고, 오버 식각에 의해 잔류물을 제거하면 상부의 가장자리가 돌출되고 중앙부가 오목한 형상의 게이트 전극이 형성된다.Referring to FIG. 2D, when the etching based on the “F” group is performed again, the oxide film 105 is removed, and when the residue is removed by over etching, the upper edge protrudes and the center electrode is concave. do.
도 2e를 참조하면, 게이트 전극이 형성된 전체구조 상에 질화막(106)을 형성한다.Referring to FIG. 2E, the nitride film 106 is formed on the entire structure where the gate electrode is formed.
도 2f를 참조하면, 질화막(106) 식각 공정을 진행함에 있어서 충분한 오버 식각이 이루어지도록 실시하면 게이트 폴리층(103)의 좌,우측면의 질화막(106)은 게이트 전극의 측벽으로 남게되고, 게이트 폴리층(103) 위의 질화막(106)은 낮은 단차와 충분한 오버 식각에 의해 완전히 제거된다.Referring to FIG. 2F, when sufficient etching is performed in the etching process of the nitride film 106, the nitride film 106 on the left and right sides of the gate poly layer 103 remains as sidewalls of the gate electrode. The nitride film 106 on the layer 103 is completely removed by low stepping and sufficient over etching.
도 2g를 참조하면, 전면에 실리사이드 형성 소오스를 증착한 후 어닐 공정을 수행하면 표면으로 노출된 영역에 실리사이드(107)가 형성된다. 이때 게이트 폴리층(103)의 상부면이 평탄하지 않고 가장자리에 돌출부를 가지므로 실리사이드(107)의 표면적이 종래의 공정보다 더 넓게 형성되고, 폴리저항이 종래의 공정보다 낮은 값을 유지하게 된다.Referring to FIG. 2G, when the silicide forming source is deposited on the entire surface, an annealing process is performed to form silicide 107 in an area exposed to the surface. In this case, since the top surface of the gate poly layer 103 is not flat and has protrusions at the edges, the surface area of the silicide 107 is formed to be wider than that of the conventional process, and the polyresistance is maintained at a lower value than the conventional process.
상기에서는 본 발명의 일 실시예에 국한하여 설명하였으나 본 발명의 기술이당업자에 의하여 용이하게 변형 실시될 가능성이 자명하다. 이러한 변형된 실시예들은 본 발명의 특허청구범위에 기재된 기술사상에 포함된다고 하여야 할 것이다.In the above description, but limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.
전술한 바와 같이 본 발명은 게이트와 콘텍이 접촉되는 영역의 실리사이드의 표면적을 증가시켜 좁은 폭의 폴리실리콘 게이트에서도 접촉면적이 넓게되어 상대적으로 게이트/콘텍 저항이 최소화되는 효과가 있다.As described above, the present invention increases the surface area of the silicide in the region where the gate is in contact with the contact, thereby increasing the contact area even in a narrow polysilicon gate, thereby minimizing the gate / contact resistance.
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| KR1020020056420A KR100632047B1 (en) | 2002-09-17 | 2002-09-17 | Method for forming gate of semiconductor element |
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