KR20060124900A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20060124900A
KR20060124900A KR1020050046578A KR20050046578A KR20060124900A KR 20060124900 A KR20060124900 A KR 20060124900A KR 1020050046578 A KR1020050046578 A KR 1020050046578A KR 20050046578 A KR20050046578 A KR 20050046578A KR 20060124900 A KR20060124900 A KR 20060124900A
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pad nitride
substrate
nitride layer
mask
etch
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KR1020050046578A
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Korean (ko)
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공필구
조용태
박원성
유재선
김석기
김은미
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주식회사 하이닉스반도체
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Priority to KR1020050046578A priority Critical patent/KR20060124900A/en
Publication of KR20060124900A publication Critical patent/KR20060124900A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)

Abstract

A method for fabricating a semiconductor device is provided to prevent process uniformity in a subsequent etch(patterning) process from being decreased by a step between a field region and an active region in a gate electrode formation process using a STAR(step gated asymmetric recess), by forming a STAR mask while a pad nitride layer is left under an isolation layer, by etching the pad nitride layer while using the STAR mask and by forming a protrusion in the center of a substrate while using the etched pad nitride layer as a hard mask. A pad oxide layer(111) is formed on a substrate(110) having a field region and an active region. A pad nitride layer(112) is formed on the pad oxide layer. The pad nitride layer and the substrate in the field region are etched to form a trench. An isolation layer(113) is formed to fill the trench. An etch mask is formed to expose a part of the pad nitride layer in the active region. An etch process using the etch mask is performed to etch the exposed pad nitride layer. After the etch mask is eliminated, an etch process using the etched pad nitride layer as a hard mask is performed to recess a predetermined depth of the exposed substrate. The pad nitride layer is removed by using H3PO4 to form a protrusion in the center of the substrate.

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE} Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1f는 종래기술에 따른 반도체 소자의 제조방법의 공정 단면도.1A to 1F are cross-sectional views of a method of manufacturing a semiconductor device according to the prior art.

도 2는 종래기술에 따른 반도체 소자의 제조방법을 통해 제조된 반도체 소자의 단면도.Figure 2 is a cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to the prior art.

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법의 공정 단면도.3A to 3D are cross-sectional views of a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

10, 110 : 기판10, 110: substrate

11, 111 : 패드 산화막11, 111: pad oxide film

12, 112 : 패드 질화막12, 112: pad nitride film

14 : 트렌치14: trench

15, 113 : 소자 분리막15, 113: device isolation film

17, 114 : 하부 반사방지막17, 114: lower antireflection film

18, 115 : 감광막 패턴(STAR 마스크)18, 115: Photosensitive film pattern (STAR mask)

19, 119 : 돌출부19, 119: projection

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 DRAM 소자 제조공정에서 STAR(STep gated Asymetric Recess) 공정을 이용한 반도체 소자의 게이트 전극 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate electrode of a semiconductor device using a star gated asymetric recess (STAR) process in a DRAM device manufacturing process.

반도체 소자는 그 내부에 다수의 단위 소자들을 포함한다. 이러한 반도체 소자가 고집적화되어 감에 따라 일정한 셀(cell) 면적 상에 고밀도로 소자들을 형성하여야 하며, 이로 인하여 단위 소자, 예컨대 트랜지스터와 캐패시터들의 크기는 점차 감소하게 되었다. 특히, DRAM과 같은 반도체 메모리 소자에서 디자인 룰(design rule)이 감소하면서 셀의 내부에 형성되는 반도체 소자들의 크기가 점차 감소하고 있다. 실제로, 최근에는 DRAM 소자의 최소 선폭은 0.1㎛이하로 형성되며, 100nm 이하까지 요구되고 있다. 이러한 좁아진 디자인 룰에 의해 채널의 길이가 짧아지고 있으며, 이것은 리프레시 타임(refresh time)을 감소시키는 결과를 초래하게 되었다.The semiconductor device includes a plurality of unit devices therein. As the semiconductor devices are highly integrated, devices must be formed at a high density on a constant cell area, thereby gradually decreasing the size of unit devices such as transistors and capacitors. In particular, as the design rule decreases in the semiconductor memory devices such as DRAM, the size of the semiconductor devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of a DRAM device is formed to be 0.1 탆 or less, and is required up to 100 nm or less. This narrower design rule results in shorter channel lengths, which results in a lower refresh time.

최근에는 DRAM 소자의 제조공정에서 트랜지스터의 채널 길이를 증가시키기 위한 일환으로 STAR(STep gated Asymetric Recess) 공정이 제안되어 사용되고 있다. Recently, a STAR (STep gated Asymetric Recess) process has been proposed and used as part of increasing the channel length of a transistor in a DRAM device manufacturing process.

이하, 도 1a 내지 도 1f를 참조하여 일반적인 STAR 공정을 이용한 반도체 소자의 게이트 전극 형성방법을 설명하기로 한다. 도 1a 내지 도 1f는 공정 단면도들이다. Hereinafter, a method of forming a gate electrode of a semiconductor device using a general STAR process will be described with reference to FIGS. 1A to 1F. 1A-1F are cross-sectional views of the process.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판(10) 상에 패드 산화막(11)과 패드 질화막(12)을 순차적으로 증착한다. First, as shown in FIG. 1A, the pad oxide film 11 and the pad nitride film 12 are sequentially deposited on the semiconductor substrate 10.

이어서, 도 1b에 도시된 바와 같이, 포토리소그래피(photolithography) 공정(13)을 실시하여 패드 질화막(12), 패드 산화막(11) 및 기판(10)을 식각하여 트렌치(14)를 형성한다. Subsequently, as illustrated in FIG. 1B, a photolithography process 13 may be performed to etch the pad nitride layer 12, the pad oxide layer 11, and the substrate 10 to form a trench 14.

이어서, 도 1c에 도시된 바와 같이, 트렌치(14)가 매립되도록 HDP(High Density Plasma) 산화막(15)을 증착한 후 CMP(Chemical Mechanical Polishing) 공정을 실시하여 소자 분리막을 형성한다. Subsequently, as shown in FIG. 1C, the HDP (High Density Plasma) oxide film 15 is deposited to fill the trench 14, and then a CMP (Chemical Mechanical Polishing) process is performed to form a device isolation film.

이어서, 도 1d에 도시된 바와 같이, 스트립 공정을 패드 질화막(12)과 패드 산화막(11)을 선택적으로 제거한다. Subsequently, as shown in FIG. 1D, the strip process selectively removes the pad nitride film 12 and the pad oxide film 11.

이어서, 도 1e에 도시된 바와 같이, 하부 반사방지막(Bottom Anti-Reflection Coating, BARC)막(17)과 감광막을 순차적으로 도포한 후 포토 마스크를 이용한 노광 및 현상공정을 실시하여 감광막 패턴(이하, STAR 마스크라 함)(18)을 형성한다. Subsequently, as shown in FIG. 1E, the bottom anti-reflection coating (BARC) film 17 and the photoresist film are sequentially applied, followed by an exposure and development process using a photo mask to perform photoresist pattern (hereinafter, 18, which is referred to as a STAR mask.

이어서, 도 1f에 도시된 바와 같이, STAR 마스크(18)를 이용한 식각공정을 실시하여 노출된 기판(10)과 소자 분리막(15)을 식각하여 액티브 영역의 중앙부에 돌출부(19)를 형성한다. Subsequently, as illustrated in FIG. 1F, an etching process using the STAR mask 18 is performed to etch the exposed substrate 10 and the device isolation layer 15 to form the protrusion 19 in the center of the active region.

이어서, 스트립 공정을 실시하여 STAR 마스크(18)와 하부 반사방지막(17)을 제거한다. Subsequently, a strip process is performed to remove the STAR mask 18 and the lower antireflection film 17.

그러나, 종래기술에 따른 STAR 공정을 이용한 반도체 소자의 게이트 전극 형성방법에서는 도 1d에 도시된 바와 같이 패드 질화막(12)과 패드 산화막(11)을 제거한 후 STAR 마스크(18)를 이용한 식각공정을 실시함에 따라 필드 영역과 액티브 영역 간에 단차에 의해 도 2에 도시된 바와 같이 액티브 영역에 혼(horn)(A)이 발생되고, 이런 상태에서 후속 식각공정을 진행함에 따라 공정의 균일성이 저하되는 원인이 된다. However, in the method of forming a gate electrode of a semiconductor device using a STAR process according to the related art, as shown in FIG. 1D, an etching process using a STAR mask 18 is performed after removing the pad nitride layer 12 and the pad oxide layer 11. As a result, a horn (A) is generated in the active region as shown in FIG. 2 due to the step between the field region and the active region, and the uniformity of the process decreases as a subsequent etching process is performed in this state. Becomes

따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출된 것으로서, STAR 공정을 이용한 반도체 소자의 게이트 전극 형성공정시 필드 영역과 액티브 영역 간의 단차에 의해 후속 식각공정(패터닝 공정) 진행시 공정의 균일성이 저하되는 것을 방지할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다. Accordingly, the present invention has been made to solve the above-described problems of the prior art, a process during the subsequent etching process (patterning process) by the step between the field region and the active region in the gate electrode forming process of the semiconductor device using the STAR process It is an object of the present invention to provide a method for manufacturing a semiconductor device which can prevent the uniformity of the semiconductor film from being lowered.

상기한 목적을 달성하기 위한 일측면에 따른 본 발명은, 필드 영역과 액티브 영역으로 정의된 기판 상에 패드 질화막을 형성하는 단계와, 상기 필드 영역의 상기 패드 질화막과 상기 기판을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치가 매립되도록 소자 분리막을 형성하는 단계와, 상기 액티브 영역의 상기 패드 질화막의 일부가 노출되도록 식각 마스크를 형성하는 단계와, 상기 식각 마스크를 이용한 식각공정을 실시하여 노출된 상기 패드 질화막을 식각하는 단계와, 상기 식각 마스크를 제거한 후 식각된 상기 패드 질화막을 하드 마스크로 이용한 식각공정을 실시하여 노출된 상기 기판을 일정 깊이로 리세스(recess)시키는 단계와, 상기 패드 질화막을 제거하여 상기 기판의 중앙부에 돌출부를 형성하는 단계를 포함하는 반도체 소자의 제조방법을 제공한다. According to an aspect of the present invention, a pad nitride film is formed on a substrate defined by a field region and an active region, and the trench is formed by etching the pad nitride layer and the substrate of the field region. Forming an isolation layer to fill the trench, forming an etch mask to expose a portion of the pad nitride layer in the active region, and performing an etching process using the etch mask. Etching the pad nitride film, removing the etching mask, and then etching the pad nitride film as a hard mask to recess the exposed substrate to a predetermined depth; Removing and forming a protrusion in the center of the substrate manufacturing method of a semiconductor device Provide the law.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다. 또한, 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장되어진 것이며, 층이 다른 층 또는 기판 "상"에 있다고 언급되어지는 경우에 그것은 다른 층 또는 기판 상에 직접 형성될 수 있거나, 또는 그들 사이에 제3의 층이 개재될 수도 있다. 또한 명세서 전체에 걸쳐서 동일한 참조번호는 표시된 부분은 동일한 구성요소들을 나타낸다. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

실시예Example

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조공정 중 STAR 공정을 이용한 반도체 소자의 게이트 전극 형성방법 설명하기 위하여 도시한 단면도들이다. 3A to 3D are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device using a STAR process in a semiconductor device manufacturing process according to an exemplary embodiment of the present invention.

먼저, 도 3a에 도시된 바와 같이, 반도체 기판(110) 상에 패드 산화막(111)과 패드 질화막(112)을 순차적으로 증착한다. First, as shown in FIG. 3A, the pad oxide film 111 and the pad nitride film 112 are sequentially deposited on the semiconductor substrate 110.

이어서, STI(Shallow Trench Isolation) 공정을 실시하여 반도체 기판(110)의 필드 영역에 트렌치(미도시)를 형성한다.Next, a trench trench isolation (STI) process is performed to form trenches (not shown) in the field region of the semiconductor substrate 110.

이어서, 트렌치가 매립되도록 전체 구조 상부에 소자 분리막용 산화막으로 매립 특성이 우수한 HDP 산화막(113)을 증착한다. Subsequently, an HDP oxide film 113 having excellent embedding characteristics is deposited as an oxide film for device isolation, so that the trench is buried.

이어서, HDP 산화막(113)을 CMP 공정과 같은 전면 식각공정으로 전체 구조 상부면을 동일한 높이로 평탄화한다. Subsequently, the HDP oxide layer 113 is planarized to the same height by the entire surface etching process such as the CMP process.

이어서, 평탄화된 전체 구조 상부면에 하부 반사방지막(114) 및 감광막을 도포한 후 포토 마스크를 이용한 노광 및 현상공정을 실시하여 STAR 마스크(115)를 형성한다.Subsequently, the lower anti-reflection film 114 and the photoresist film are applied to the entire top surface of the planarized structure, and then the exposure and development processes using the photo mask are performed to form the STAR mask 115.

이어서, 도 3b에 도시된 바와 같이, STAR 마스크(115)를 이용한 식각공정(116)을 실시하여 하부 반사방지막(114), 패드 질화막(112) 및 패드 산화막(111)을 식각한다. 이때, 식각공정(116)에 의해 노출된 소자 분리막(113)의 일부가 식각된다.Subsequently, as illustrated in FIG. 3B, the etching process 116 using the STAR mask 115 is performed to etch the lower anti-reflection film 114, the pad nitride film 112, and the pad oxide film 111. In this case, a portion of the device isolation layer 113 exposed by the etching process 116 is etched.

이어서, 도 3c에 도시된 바와 같이, 스트립 공정을 실시하여 STAR 마스크(115, 도 3b참조)와 하부 반사방지막(114)을 제거한다. Subsequently, as shown in FIG. 3C, a strip process is performed to remove the STAR mask 115 (see FIG. 3B) and the lower anti-reflection film 114.

이어서, 도 3b에서 식각된 패드 질화막(112)을 하드 마스크(hard mask)로 이용한 식각공정(117)을 실시하여 노출된 기판(110)을 일정 깊이로 리세스(recess)시 킨다. 이때, 식각공정(117)에 의해 노출된 소자 분리막(113)의 일부가 일정 깊이로 식각된다. Subsequently, an etching process 117 using the etched pad nitride layer 112 as a hard mask is performed in FIG. 3B to recess the exposed substrate 110 to a predetermined depth. In this case, a portion of the device isolation layer 113 exposed by the etching process 117 is etched to a predetermined depth.

이어서, 도 3c에 도시된 바와 같이, H3PO4를 이용한 식각공정(118)을 실시하여 패드 질화막(112)을 제거한다. Subsequently, as illustrated in FIG. 3C, an etching process 118 using H 3 PO 4 is performed to remove the pad nitride layer 112.

이어서, 패드 산화막(111)을 제거한다. 이로써, 동도면에 도시된 바와 같이 액티브 영역의 기판(110)의 중앙부가 돌출되어, 소정 크기의 돌출부(119)가 형성된다. Next, the pad oxide film 111 is removed. As a result, the center portion of the substrate 110 in the active region protrudes, as shown in the drawing, to form a protrusion 119 having a predetermined size.

한편, 식각공정(118)을 실시하기 전에 기판(110)의 손상을 방지하기 위하여 산화공정을 실시할 수도 있다. 이로써, 노출된 기판(110) 상부면에 실리콘 산화막이 형성되어 식각공정(118)이 노출된 기판(110)이 손상되는 것을 최소화시킬 수 있다. Meanwhile, before performing the etching process 118, an oxidation process may be performed to prevent damage to the substrate 110. As a result, a silicon oxide layer may be formed on the exposed upper surface of the substrate 110, thereby minimizing damage to the exposed substrate 110.

본 발명의 기술 사상은 바람직한 실시예들에서 구체적으로 기술되었으나, 상기한 실시예들은 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다. Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

이상 설명한 바와 같이, 본 발명에 의하면, 소자 분리막 형성 후 패드 질화막을 하부에 그대로 잔류시킨 상태에서 STAR 마스크를 형성하고, 이렇게 형성된 STAR 마스크를 이용하여 패드 질화막을 먼저 식각한 후, 식각된 패드 질화막을 하드 마스크로 이용한 식각공정을 실시하여 기판의 중앙부에 돌출부를 형성함으로써 STAR 공정을 이용한 반도체 소자의 게이트 전극 형성공정시 필드 영역과 액티브 영역 간의 단차에 의해 후속 식각공정(패터닝 공정) 진행시 공정의 균일성이 저하되는 것을 방지할 수 있다. As described above, according to the present invention, after forming the device isolation film, a STAR mask is formed while the pad nitride film is left as it is, and the pad nitride film is first etched using the thus formed STAR mask, and then the etched pad nitride film is The etching process using the hard mask is formed to form a protrusion in the center of the substrate, and thus the uniformity of the process during the subsequent etching process (patterning process) is performed by the step between the field region and the active region during the gate electrode formation process of the semiconductor device using the STAR process Degradation can be prevented.

Claims (4)

필드 영역과 액티브 영역으로 정의된 기판 상에 패드 질화막을 형성하는 단계;Forming a pad nitride film on the substrate defined by the field region and the active region; 상기 필드 영역의 상기 패드 질화막과 상기 기판을 식각하여 트렌치를 형성하는 단계;Etching the pad nitride layer and the substrate in the field region to form a trench; 상기 트렌치가 매립되도록 소자 분리막을 형성하는 단계;Forming an isolation layer to fill the trench; 상기 액티브 영역의 상기 패드 질화막의 일부가 노출되도록 식각 마스크를 형성하는 단계;Forming an etch mask to expose a portion of the pad nitride layer in the active region; 상기 식각 마스크를 이용한 식각공정을 실시하여 노출된 상기 패드 질화막을 식각하는 단계; Etching the exposed pad nitride layer by performing an etching process using the etching mask; 상기 식각 마스크를 제거한 후 식각된 상기 패드 질화막을 하드 마스크로 이용한 식각공정을 실시하여 노출된 상기 기판을 일정 깊이로 리세스(recess)시키는 단계; 및Removing the etching mask and recessing the exposed substrate to a predetermined depth by performing an etching process using the etched pad nitride layer as a hard mask; And 상기 패드 질화막을 제거하여 상기 기판의 중앙부에 돌출부를 형성하는 단계;Removing the pad nitride layer to form a protrusion at a center portion of the substrate; 를 포함하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 패드 질화막을 형성하는 단계 전에 상기 기판 상에 패드 산화막을 형성하는 단계를 더 포함하는 반도체 소자의 제조방법.And forming a pad oxide film on the substrate before forming the pad nitride film. 제 1 항 또는 제 2 항에 있어서, The method according to claim 1 or 2, 상기 기판을 리세스시키는 단계 후 산화공정을 실시하여 노출된 상기 기판 상에 산화막을 형성하는 단계를 더 포함하는 반도체 소자의 제조방법.And forming an oxide film on the exposed substrate by performing an oxidation process after the recessing of the substrate. 제 1 항 또는 제 2 항에 있어서, The method according to claim 1 or 2, 상기 패드 질화막 제거 공정은 H3PO4를 이용하여 실시하는 반도체 소자의 제조방법.The pad nitride film removing process is performed using H 3 PO 4 .
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