KR20060127485A - Method for forming a floating gate in semiconductor device - Google Patents

Abstract

A method for forming a floating gate of a semiconductor device is provided to reduce the loss of a predetermined field oxide layer of a first region without the increase of height of a pad nitride layer. A pad oxide layer and a pad nitride layer are formed on a semiconductor substrate(110) with first and second regions. A plurality of trenches are formed on the resultant structure. First and second field oxide layers(113a,113b) are filled in the trenches of the first and second region, respectively. The second field oxide layer of the second region is selectively etched. The pad nitride layer and the pad oxide layer are removed therefrom. A tunnel oxide layer(115) is formed on the substrate. A floating gate polysilicon layer(116) is formed on the entire surface of the resultant structure. A polish stop layer(117) is formed on the polysilicon layer of the second region. A floating gate is formed on the tunnel oxide layer of the first region by polishing the polysilicon layer.

Description

METHODS FOR FORMING A FLOATING GATE IN SEMICONDUCTOR DEVICE

1A to 1E are cross-sectional views illustrating a method of forming a self aligned floating gate of a flash memory device according to the related art.

2A to 2G are cross-sectional views illustrating a method of forming a self-aligned floating gate of a flash memory device according to a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10, 110: semiconductor substrate 11, 111: pad oxide film

12, 112: pad nitride film 13a, 113a: first field oxide film

13b, 113b: second field oxide film 15, 115: tunnel oxide film

16, 116: polysilicon layer for floating gate

117: anti-polishing films 16a, 116a: floating gate

A: cell area B: ferry area

The present invention relates to a method of forming a floating gate of a semiconductor device, and more particularly, to a method of forming a floating gate of a flash memory device to which a self-aligned process is applied.

In the manufacture of highly integrated memory devices, the degree of integration of the cells is mainly determined by the layout of the memory cells and the scalability of the layout as the critical dimension shrinks. As the critical dimension shrinks below the sub-micron region, the scalability of the layout is limited by the resolution of the manufacturing process and the alignment tolerance by the design mask. The alignment of the mask is limited by the mechanical technique of placing the mask on top of the wafer during processing and the technique of consistently printing the pattern on top of the mask. Accumulation of alignment tolerances causes misalignment errors in the layout of the array, so it is desirable to use fewer alignment threshold masks to control the alignment tolerances in chip design. Thus, so-called "self-aligned" process steps have been developed.

This self-alignment process has also been applied in forming floating gates of flash memory devices, which are increasingly integrated in recent years. As described above, the floating gate forming method of the flash memory device to which the self-alignment process is applied is as follows.

1A to 1E are cross-sectional views illustrating a method of forming a self-aligned floating gate of a flash memory device according to the related art.

First, as shown in FIG. 1A, a semiconductor substrate 10 defined as a region having a high pattern density, such as a cell region A and a region having a low pattern density, such as a peri region B, is described. A shallow trench isolation (STI) process is performed to form the first and second field oxide films 13a and 13b. For example, after the pad oxide film 11 and the pad nitride film 12 are deposited on the substrate 10, a mask process and an etching process are performed to form the substrate 10 of the cell region A and the ferry region B, respectively. After forming a plurality of exposed contact holes (not shown), first and second field oxide layers 13a and 13b may be formed to fill contact holes in the cell region A and the ferry region B, respectively.

Here, the second field oxide film 13b formed in the ferry region B having a low pattern density has a wider width than the first field oxide film 13a formed in the cell region A. FIG. Therefore, in the second field oxide film 13b, a dishing phenomenon occurs in which the central portion is recessed.

Subsequently, as shown in FIG. 1B, a wet etching process using phosphoric acid is performed to remove the remaining pad nitride film 12. As a result, the first and second field oxide films 13a and 13b protrude above the pad oxide film 11.

Subsequently, as shown in FIG. 1C, both sides of the first and second field oxide layers 13a and 13b of the protruding portion may be subjected to a wet etching process using an oxide etching solution such as HF or BOE (Buffered Oxide Etchant). Etch it. As a result, the widths of the first and second field oxide films 13a and 13b on the pad oxide film 11 are reduced by a predetermined width.

Subsequently, as shown in FIG. 1D, a wet etching process is performed to remove the pad oxide film 11 (see FIG. 1C), followed by an oxidation process to form the tunnel oxide film 15 on the exposed substrate 10. .

Subsequently, the polysilicon layer 16 for floating gate is deposited on the tunnel oxide film 15 so as to cover the first and second field oxide films 13a and 13b.

Subsequently, as illustrated in FIG. 1E, the polysilicon layer 16 is polished by performing a chemical mechanical polishing (CMP) process, whereby the polysilicon layer 16 is formed by cell area A and ferry area B, respectively. To be separated. As a result, the floating gate 16a is formed between the active region of the cell region A, that is, the first field oxide film 13a.

However, when the CMP process is performed as shown in FIG. 1E, the polysilicon layer 16 deposited in the active region of the ferry region B is compared with the polysilicon layer 16 deposited in the active region of the cell region A. Since the area is so large, dishing occurs in the polysilicon layer 16 deposited in the active region of the ferry region B, resulting in a problem of polishing to the tunnel oxide film 15 under the polysilicon layer 16. In addition, there is a problem in that the loss of the first field oxide film 13a in the cell region A becomes large.

In addition, the center portion of the second field oxide film 13b formed in the field region of the ferry region B is concave, so that the polysilicon layer 16 remains on the second field oxide film 13b even after polishing. This will adversely affect subsequent processes.

On the other hand, in order to remove the polysilicon layer 16 remaining on the second field oxide film 13b in the ferry region B, loss of the first field oxide film 13a in the cell region A is inevitable. As a result, in order to reduce the loss of the first field oxide layer 13a while removing the polysilicon layer 16 remaining on the second field oxide layer 13b, the first and second fields protruded onto the substrate 10. The heights of the oxide films 13a and 13b must be increased. As such, in order to increase the height of the first and second field oxide films 13a and 13b, the height of the pad nitride film 12 must be increased.

However, when the height of the pad nitride film 12 is increased in this way, the aspect ratio of the first and second field oxide films 13a and 13b filled in the pad nitride film 12 increases, which causes a big problem in the process margin.

Accordingly, the present invention has been proposed to solve the above-described problem, and the pattern is removed while removing the polysilicon layer remaining on the field oxide film in a low pattern density region without increasing the height of the pad nitride film when forming the floating gate of the semiconductor device. It is an object of the present invention to provide a method for forming a floating gate of a semiconductor device capable of reducing field oxide film loss in a high density region.

According to an aspect of the present invention, there is provided a semiconductor substrate including a first region having a high pattern density and a second region having a low pattern density, and Depositing a pad oxide film and a pad nitride film on the substrate, etching the pad nitride film, the pad oxide film, and the substrate to form a plurality of trenches in the first and second regions; Forming first and second field oxide films in which the trenches in the second region are buried, respectively, and the second field such that the first field oxide film in the first region is higher than the second field oxide film in the second region. Etching the oxide film to a predetermined depth, removing the pad nitride film and the pad oxide film, forming a tunnel oxide film on the substrate, and forming the tunnel oxide film. Depositing a polysilicon layer for a floating gate on an entire structure, forming an anti-polishing film on the polysilicon layer in the second region, and polishing the polysilicon layer in the tunnel in the first region It provides a floating gate forming method of a semiconductor device comprising the step of forming a floating gate on the oxide film.

Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

Example

2A to 2G are cross-sectional views illustrating a method of forming a self-aligned floating gate of a flash memory device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 2A to 2G are the same elements performing the same function.

First, as shown in FIG. 2A, a region having a high pattern density, such as a cell region A (hereinafter referred to as a first region) and a region having a low pattern density, such as a peri region B; The first and second field oxide layers 113a and 113b are formed by performing a shallow trench isolation (STI) process on the semiconductor substrate 110 defined as a second region. For example, after the pad oxide layer 111 and the pad nitride layer 122 are deposited on the substrate 110, a mask process and an etching process are performed to perform the substrate 110 in the first region A and the second region B. Forming a plurality of contact holes (not shown) to expose each. Then, first and second field oxide layers 113a and 113b are formed to fill contact holes in the first and second regions A and B, respectively.

Here, high pattern density means that the number of field oxide films formed relatively is large, and the width of the field oxide films formed is narrow. Accordingly, the second field oxide film 113b formed in the second region B has a wider width and a smaller number than the first field oxide film 113a formed in the first region A. FIG. As a result, a dishing phenomenon occurs in the second field oxide film 113b, the center portion of which is concave.

Subsequently, as shown in FIG. 2B, the wet etching process is performed to etch the second field oxide film 113b in the region except the first region A, that is, the second region B to a predetermined depth h. . In this case, the second field oxide layer 113b is etched to protrude to the substrate 110 by a thickness of 100 to 250 microns. As a result, the second field oxide film 113b is lower than the first field oxide film 113a to generate a step between the first and second field oxide films 113a and 113b. As a result, the contact area between the dielectric film (not shown) and the floating gate 116a (see FIG. 2F) to be formed through the subsequent process can be easily adjusted in the first region A, and the subsequent region in the second region B. The leakage current between the gate electrode (not shown) and the source / drain (not shown) to be formed through the process can be reduced.

Subsequently, as illustrated in FIG. 2C, the pad nitride film 112 is removed by performing a wet etching process using phosphoric acid. As a result, the first and second field oxide layers 113a and 113b protrude from the pad oxide layer 111, respectively.

Subsequently, a wet etching process using an oxide etching solution such as HF or buffered oxide etchant (BOE) is performed to etch both sides of the first and second field oxide layers 113a and 113b of the protruding portion. As a result, the widths of the first and second field oxide films 113a and 113b on the pad oxide film 111 are reduced to a desired width.

Subsequently, as shown in FIG. 2D, a wet etching process is performed to remove the pad oxide film 111 (see FIG. 2C), followed by an oxidation process to form the tunnel oxide film 115 on the exposed substrate 110. . Here, the oxidation process is performed by a wet oxidation method in which a semiconductor substrate is heated at a temperature of approximately 900 to 1000 ° C. in an oxidizing gas such as water vapor, or dry oxidation which is heated at a temperature of about 1200 ° C. using pure oxygen as an oxidizing gas. Do it in a way.

Subsequently, a floating gate polysilicon layer 116 (hereinafter referred to as a polysilicon layer) is deposited on the entire structure including the tunnel oxide layer 115 to cover the first and second field oxide layers 113a and 113b. In this case, the polysilicon layer 116 has the same thickness as that of the height of the first field oxide film 113a protruding above the substrate 110 in the first region A, that is, 50 to 50 of the line width of the second field oxide film 113b. Deposit a thickness of 70% line width.

Subsequently, as shown in FIG. 2E, an anti-polishing film to prevent polishing of the polysilicon layer 116 in the region other than the first region A, that is, the second region B, on the polysilicon layer 116. 117 is deposited. In this case, the anti-polishing film 117 deposits an oxide-based material at a thickness that compensates for the step difference between the polysilicon layer 116 in the first region A and the polysilicon layer 116 in the second region B.

Subsequently, after applying a photoresist (not shown) on the anti-polishing film 117, a photoresist pattern (not shown) covering the second region B by performing an exposure and development process using a photomask (not shown). To form.

Subsequently, an etching process using the photoresist pattern as an etching mask is performed to etch the anti-polishing film 117 in the first region A. FIG. As a result, the anti-polishing film 117 remains only in the second region B, thereby preventing the polysilicon layer 116 in the second region B from being etched.

Subsequently, as illustrated in FIG. 2F, a strip process is performed to remove the photoresist pattern (not shown), followed by a chemical mechanical polishing (CMP) process to polish the polysilicon layer 116. The polysilicon layer 116 is separated for each of the first region (A) and the second region (B). As a result, the floating gate 116a is formed on the active region of the first region A, that is, the tunnel oxide film 115 between the first field oxide film 113a.

Here, since the thickness of the polysilicon layer 116 to be polished is thinner than the above-mentioned prior art, the uniformity in the wafer may be improved.

However, as shown in FIG. 2G, a wet etching process is performed to remove the remaining anti-polishing film 117. In this case, the first field oxide layer 113a formed of the same oxide layer as the anti-polishing layer 117 and protruding onto the tunnel oxide layer 115 in the first region A may also be removed. Here, the slurry may be a low polishing rate slurry, such as a slurry used for mirror polishing of bare silicon, or a slurry having a small change in polishing rate depending on the polishing pressure and the linear velocity of the polishing pad. The uniformity of the polishing amount can be improved.

Subsequently, although not shown in the drawing, the polysilicon layer 116 on the second field oxide film 113b in the second region B is removed during the etching process for forming the gate electrode. Therefore, the polysilicon layer 116 does not remain on the second field oxide film 113b.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the first field oxide film of the first region having a low pattern density is etched lower than the second field oxide film of the second region having a high pattern density, and then the floating gate poly A floating gate is formed between the second field oxide film of the second region by depositing a silicon layer and forming and polishing an anti-polishing film on the polysilicon layer of the second region. Thus, it is possible to reduce the second field oxide loss of the first region without increasing the height of the pad nitride film.

In addition, according to the present invention, the polysilicon layer on the first field oxide layer of the first region is removed by removing the polysilicon layer deposited on the field region of the first region, that is, the first field oxide layer during the etching process for forming the gate electrode. The layer can be prevented from remaining.

Claims (8)

Providing a semiconductor substrate defined by a first region having a high pattern density and a second region having a low pattern density; Depositing a pad oxide film and a pad nitride film on the substrate in the first and second regions; Etching the pad nitride film, the pad oxide film, and the substrate to form a plurality of trenches in the first and second regions; Forming first and second field oxide films in which the trenches of the first and second regions are buried, respectively; Etching the second field oxide layer to a predetermined depth such that the first field oxide layer in the first region is higher than the second field oxide layer in the second region; Removing the pad nitride film and the pad oxide film; Forming a tunnel oxide film on the substrate; Depositing a polysilicon layer for a floating gate on the entire structure including the tunnel oxide film; Forming an anti-polishing film on the polysilicon layer in the second region; And Polishing the polysilicon layer to form a floating gate on the tunnel oxide film in the first region Floating gate forming method of a semiconductor device comprising a. The method of claim 1, And the first region having a high pattern density has a greater number of field oxide films formed than the second region having a low pattern density, and has a narrower width of the field oxide film than at the second region. The method according to claim 1 or 2, And etching the field oxide film in the second region so that the field oxide film protrudes from the substrate by a thickness of 100 to 250 microns. The method of claim 1 or 2, wherein the removing of the pad nitride layer and the pad oxide layer comprises: Removing the pad nitride film; Etching both sidewalls of the first and second field oxide films to reduce the widths of the first and second field oxide films to a desired width; And Removing the pad oxide layer A floating gate forming method of a semiconductor device. The method according to claim 1 or 2, And depositing the polysilicon layer for the floating gate to the same thickness as the height of the field oxide film protruding above the substrate in the first region. The method according to claim 1 or 2, The anti-polishing film is a floating gate forming method of a semiconductor device formed of an oxide-based material. The method of claim 1, And removing the anti-polishing film remaining after forming the floating gate. The method according to claim 1 or 7, And removing the field oxide film protruding from the top of the substrate in the first region while removing the anti-polishing film remaining after the floating gate is formed.

Images