KR100636681B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to avoid a horn phenomenon occurring in forming a recessed channel by simultaneously forming an isolation region and a trench for a recess gate. A mask layer pattern in which a pad oxide layer pattern and a pad nitride layer pattern are formed is formed on a semiconductor substrate(400). A photoresist pattern for defining a trench formation region is formed on the mask layer pattern. By using the photoresist pattern as an etch mask, first and second trenches(510,520) are formed in the semiconductor substrate. A buried insulation layer(560) is formed to bury the first and the second trenches and the semiconductor substrate. An open mask is formed to expose the second trench in the semiconductor substrate. By using the open mask as an etch mask, the buried insulation layer in the second trench is eliminated. A plurality of gates are formed to overlap the second trench.

Description

Method for manufacturing semiconductor device

1 is a view illustrating a semiconductor device having a recessed channel according to the prior art.

FIG. 2 is a view showing a portion cut out in the direction of X-X 'of FIG.

FIG. 3 is an enlarged view of a portion cut from FIG. 1 in the Y-Y 'direction.

4 to 13 are views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

14 is a view illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

400: semiconductor substrate 440: first photomask

460: second photomask 510: first trench

520: second trench 560: buried insulating film

570: open mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that prevents phenomena occurring when forming a recessed channel.

Recently, as DRAM cells are highly integrated, transistors have become smaller in size, and thus, channel lengths between source and drain are also shortened. As the channel length becomes shorter, the short channel effect of the transistor is intensified to reduce the threshold voltage. Accordingly, in order to prevent the threshold voltage from decreasing due to the short channel effect of the transistor, the doping concentration of the channel is increased to obtain a threshold voltage having a desired size.

However, such an increase in channel doping concentration causes a field concentration phenomenon at the source junction, and increases leakage current, thereby degrading the refresh characteristics of the DRAM memory cell. Accordingly, recently, studies have been conducted on recess channel structures capable of suppressing the above problems without reducing the integration density of devices by etching a portion of the substrate to a predetermined depth to increase the effective channel length.

1 is a view illustrating a semiconductor device having a recessed channel according to the prior art. FIG. 2 is a view showing a portion cut out in the direction of X-X 'of FIG. FIG. 3 is an enlarged view of a portion cut out in FIG. 1 in the Y-Y 'direction.

1 and 2, in the semiconductor device having the recessed channel, after forming the first trench 101 in the semiconductor substrate 100, the sidewall oxide film 102 and the liner nitride film in the first trench 101 are formed. After forming the 104 and the liner oxide film 106, the device isolation film 108 defining the device isolation region is formed through a predetermined process. Next, a second trench 109 is formed at a predetermined depth from the surface of the semiconductor substrate 100 in the active region defined by the device isolation layer 108, and then a gate stack is formed on the second trench 109. 118 is disposed and source / drain impurities are implanted to form channel A. The gate stack 118 may include a gate oxide film pattern 110, a conductive film pattern 112, a metal film pattern 114, and a hard mask film pattern 116. A spacer film (not shown) is disposed on the side surface of the gate stack 118. The length of the gate channel of the semiconductor device having the recessed channel A is longer than that of the semiconductor device having the planar channel. As the length of the gate channel increases, the cell threshold voltage increases accordingly. When the cell threshold voltage increases, the planar channel improves the refresh characteristics by reducing the amount of electric field, reducing the junction leakage current and the gate induced drain leakage (GIDL). It can be increased by about twice as compared to the semiconductor device having a.

Meanwhile, referring to FIG. 3, in forming a semiconductor device having a recess gate, the semiconductor substrate 100 of the active region and the device isolation layer 108 meet each other when etching to form the second trench 109. Etching is disturbed due to the sidewall oxide film 102 positioned at the portion, thereby slowing down the etching of the active region 100 at the interface with the sidewall oxide film 102. Accordingly, a phenomenon in which silicon remains sharply (hereinafter, referred to as a horn) 300 occurs due to a difference in etching rate between the semiconductor substrate 100 and the device isolation layer 108 in the active region. When the horn 300 is generated, the cell threshold voltage is severely lowered as the electric field is concentrated at the portion where the horn 300 is generated when a current passes through the gate electrode. When the cell threshold voltage is lowered, an error occurs in the operation of the device, causing a problem of deterioration of device characteristics.

An object of the present invention is to provide a method for forming a trench in a semiconductor device to prevent the phenomena occurring when the recessed channel is formed to improve the electrical characteristics of the semiconductor device.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device according to the present invention, forming a mask film pattern on a semiconductor substrate; Forming a photoresist pattern defining a trench formation region on the mask layer pattern; Forming first and second trenches on the semiconductor substrate using the photoresist pattern as an etch mask; Forming a buried insulating film filling the first and second trenches and the semiconductor substrate; Forming an open mask that exposes a second trench of the semiconductor substrate; Removing the buried insulating layer inside the second trench using the open mask as an etch mask; And forming a plurality of gates to overlap the second trenches.

In the present invention, the mask layer pattern may include a pad oxide layer pattern and a pad nitride layer pattern.

The forming of the photoresist pattern may include forming a photoresist film on the mask film pattern; Patterning a first trench formation region by performing first exposure and development on the photoresist film; And patterning the second trench formation region by performing a second exposure and development on a region other than the patterned first trench formation region.

In the forming of the photoresist pattern, the photoresist pattern may simultaneously pattern the first trench and the second trench formation region.

In the forming of the first and second trenches in the semiconductor substrate, it is preferable to use dry etching.

In forming the first and second trenches in the semiconductor substrate, it is preferable that the second trench has a shallower depth than the first trench.

The open mask exposing the second trench is formed as a circular open mask.

In the removing of the buried insulating layer inside the second trench, an etchant including HF may be used.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

4 to 13 are views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

First, referring to FIG. 4, the pad oxide film 410 and the pad nitride film 420 are sequentially deposited on the semiconductor substrate 400. Here, the pad oxide film 410 is formed to a thickness of about 110 kPa using a thermal oxidation process, and the pad nitride film 420 is formed to a thickness of about 600 kPa using a low pressure chemical vapor deposition (LPCVD) method. . The pad oxide layer 410 serves to relieve stress of the semiconductor substrate 400 due to the attraction of the pad nitride layer 420. Next, a photoresist is applied on the entire surface of the pad nitride film 420 to form a photoresist film 430.

Next, referring to FIG. 5, a first photomask (also referred to as a reticle) 440 having a pattern defining an isolation region is disposed on the semiconductor substrate 400 on which the photoresist film 430 is formed. The photomask layer 430 is exposed to the light source for exposure through the photomask 440. The pattern defining the isolation region is then transferred to the photoresist film 430. Next, the photoresist layer 430 on which the pattern defining the device isolation region is transferred through the first photomask 440 is developed using a specific developer to form a device isolation region on the photoresist layer 430. A first photoresist pattern 450 is defined, and the first photomask 440 is removed.

6, a second photomask 460 having a pattern defining a trench formation region for a recess gate on the semiconductor substrate 400 without removing the first photoresist pattern 450. ) Is disposed and exposed to the light source for exposure through the second photomask 460. Then, the pattern defining the trench forming region for the recess gate is transferred to the region 470 except for the portion in which the device isolation region is defined. Next, the photoresist film having the pattern defining the trench forming region for the recess gate is transferred through the second photomask 460 using a specific developer to develop a region except for the region where the device isolation region is defined. A second photoresist pattern 480 defining a trench formation region for a recess gate is formed on the 470.

Next, referring to FIG. 7, the exposed portions of the pad nitride layer 420 and the pad oxide layer 410 are sequentially removed using the second photoresist pattern 480 as an etch mask, and the device isolation region of the semiconductor substrate 400 may be removed. After forming the pad oxide layer pattern 490 and the pad nitride layer pattern 500 exposing the trench formation region for the recess gate, the second photoresist pattern 480 is removed.

Next, referring to FIG. 8, an etching process is performed on the exposed portion of the semiconductor substrate 400 to form a trench having a predetermined depth. In this case, the first trench 510 having a relatively narrow width is formed in the trench formation region for the recess gate, and the second trench 520 having a relatively wide width is formed in the device isolation region. When the first and second trenches 510 and 520 are formed, dry etching, for example, plasma etching, may be performed using a method. In this case, the first trench 510 is narrower than the second trench 520, so the plasma is less exposed to the second trench 520, so that the first trench 510 is etched to a shallower depth than the second trench 520. In this case, the first and second trenches 510 and 520 are simultaneously formed through a dry etching process, so that the sidewall oxide layer 102 (see FIG. 3) and the semiconductor substrate 100 (see FIG. 3) of the active region are formed in the conventional device isolation region. It is possible to prevent the horn (300, see Figure 3) caused by the etching is slow at the interface of the.

Next, referring to FIG. 9, sidewall oxide layers 530 are formed on inner walls of the first and second trenches 510 and 520. The sidewall oxide film 530 may be formed using a dry oxidation method. Next, a liner nitride film 540 and a liner oxide film 550 are formed on the entire surface of the semiconductor substrate 500 to prevent damage to the semiconductor substrate 400 in a subsequent buried insulating film forming process. In this case, the liner nitride film 540 may be formed in a furnace by using a low pressure chemical vapor deposition (LPCVD) method. Next, after loading the semiconductor substrate 400 on which the liner oxide film 550 is formed into a high density plasma apparatus, silane (SiH₄) and oxygen (O₂) are supplied as a source gas, and helium (He) is supplied as an additive gas. A high density plasma (HDP) oxide film is formed as the buried insulating film 560 so that both the first and second trenches 510 and 520 are buried through a predetermined process.

Next, referring to FIG. 10, the buried insulating film 560 is planarized to expose the surface of the pad nitride film pattern 490 and the pad nitride film pattern 490 is removed. The planarization of the buried insulating film 560 may be performed using a chemical mechanical polishing (CMP) method. In addition, the pad nitride film pattern 490 may be removed using phosphoric acid (H 3 PO₄). Next, an open mask 570 that exposes the first trench 510 formation region is formed. In this case, as shown in FIG. 11, the open mask 570 may be formed as a photoresist pattern in which only the first trench 510 forming region is exposed in a circular shape.

Next, as shown in FIG. 12, the buried insulating film 560, the liner oxide film 550, and the liner nitride film 540 of the first trench 510 are removed using the open mask 570 as an etch mask. 1 expose trench 510. In this case, the buried insulating film 560, the liner oxide film 550, and the liner nitride film 540 may be removed using an aqueous solution containing HF.

Next, referring to FIG. 13, a plurality of gate stacks 630 are formed to overlap the first trench 510. In this case, the gate stack 630 may include a gate oxide film pattern 590, a conductive film pattern 600, a metal film pattern 610, and a hard mask film pattern 620.

14 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

First, the pad oxide film 410 and the pad nitride film 420 are sequentially deposited on the semiconductor substrate 400 through the same process as in FIG. 4, and then a photoresist is coated on the entire surface of the pad nitride film 420. 430 is formed.

Next, referring to FIG. 14, a photomask 640 having a pattern defining first and second trench formation regions is disposed on the semiconductor substrate 400 on which the photoresist film 430 is formed. The mask 640 is exposed to an exposure light source. Then, patterns defining the first and second trench formation regions are transferred to the photoresist film 430. Next, the photoresist pattern 430 patterned through the photomask 640 is developed using a specific developer to define first and second trench formation regions on the photoresist layer 430. 650 is formed and the photomask 640 is removed. When the photoresist pattern 650 in which the first and second trench formation regions are simultaneously patterned is formed, the process steps may be reduced, and thus the yield of the semiconductor device may be improved. Thereafter, the process is the same as that of FIGS. 5 to 13.

As described above, according to the trench forming method of the semiconductor device according to the present invention, by forming the device isolation region and the recess gate trench at the same time to prevent the phenomena generated during the formation of the recessed channel to prevent the electrical characteristics of the semiconductor device Can be improved.

Claims (7)

Forming a mask film pattern on the semiconductor substrate; Forming a photoresist pattern defining a trench formation region on the mask layer pattern; Forming first and second trenches on the semiconductor substrate using the photoresist pattern as an etch mask; Forming a buried insulating film filling the first and second trenches and the semiconductor substrate; Forming an open mask that exposes a second trench of the semiconductor substrate; Removing the buried insulating layer inside the second trench using the open mask as an etch mask; And Forming a plurality of gates so as to overlap the second trenches. The method of claim 1, The mask layer pattern may include a pad oxide layer pattern and a pad nitride layer pattern. The method of claim 1, wherein the forming of the photoresist pattern comprises: Forming a photoresist film on the mask film pattern; Patterning a first trench formation region by performing first exposure and development on the photoresist film; And And patterning the second trench formation region by performing a second exposure and development on a region other than the patterned first trench formation region. The method of claim 1, In the forming of the photoresist pattern, the photoresist pattern is a semiconductor device manufacturing method, characterized in that the first trench and the second trench formation region is patterned at the same time. The method of claim 1, And forming first and second trenches in the semiconductor substrate, wherein the second trench has a shallower depth than the first trench. The method of claim 1, The open mask exposing the second trench is a circular open mask manufacturing method of a semiconductor device. The method of claim 1, In the removing of the buried insulating layer inside the second trench, a method of manufacturing a semiconductor device, characterized in that an etchant containing HF is used.

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