KR20070070596A - Metal etching method of semiconductor device - Google Patents
Metal etching method of semiconductor device Download PDFInfo
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- KR20070070596A KR20070070596A KR1020050133314A KR20050133314A KR20070070596A KR 20070070596 A KR20070070596 A KR 20070070596A KR 1020050133314 A KR1020050133314 A KR 1020050133314A KR 20050133314 A KR20050133314 A KR 20050133314A KR 20070070596 A KR20070070596 A KR 20070070596A
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- 239000002184 metal Substances 0.000 title claims abstract description 55
- 238000005530 etching Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 229920000642 polymer Polymers 0.000 claims abstract description 11
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 238000001020 plasma etching Methods 0.000 claims description 9
- 238000009616 inductively coupled plasma Methods 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 abstract description 9
- 239000002245 particle Substances 0.000 abstract description 6
- 238000011109 contamination Methods 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- 239000006117 anti-reflective coating Substances 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 8
- 239000010410 layer Substances 0.000 description 7
- 238000004380 ashing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- -1 BCl 3 Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000036470 plasma concentration Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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Abstract
본 발명은 반도체 소자의 금속 식각 방법에 관한 것으로, 금속 배선층 상의 자연 산화막과 BARC(bottom anti-reflective coating) 막을 제거하는 BT(break through) 단계와; 사진 공정에 의하여 금속 배선 패턴을 형성한 후, 상기 금속 배선 패턴 위에 상기 금속 배선층을 선택 식각하여 금속 배선을 형성하는 ME(main etch) 단계와; 상기 금속 배선의 식각 상태를 균일한 상태로 더 식각하는 OE(over etch) 단계와; 상기 ME 단계 및 상기 OE 단계에서 발생한 잔여 PR(photo resist)과 폴리머(polymer)를 제거하는 PET(post etching treatment) 단계를 포함하는 반도체 소자의 금속 식각 방법에 의하여, 폴리머와 PR을 제거하여 챔버(chamber)의 오염을 억제함으로써, 챔버의 세정 주기를 늘려 반도체 소자의 생산성을 향상시키는 효과가 있다. 아울러, 파티클 소스(particle source)를 원천적으로 방지하여 반도체 소자의 질을 향상시키는 효과가 있다.The present invention relates to a metal etching method of a semiconductor device, comprising: a break through (BT) step of removing a native oxide film and a bottom anti-reflective coating (BARC) film on a metal wiring layer; Forming a metal wiring pattern by a photolithography process and then selectively etching the metal wiring layer on the metal wiring pattern to form a metal wiring; An OE (over etch) step of further etching the etching state of the metal wiring in a uniform state; By the metal etching method of the semiconductor device comprising a post etching treatment (PET) step of removing the residual photoresist (PR) and the polymer (polymer) generated in the ME step and the OE step, the polymer and PR to remove the chamber ( By suppressing contamination of the chamber), the cleaning cycle of the chamber is increased to increase the productivity of the semiconductor device. In addition, there is an effect of improving the quality of the semiconductor device by preventing the particle source (particle source) at the source.
Description
도 1은 본 발명의 일실시예에 의한 반도체 소자의 금속 식각 방법의 공정 블록도이다.1 is a process block diagram of a metal etching method of a semiconductor device according to an embodiment of the present invention.
도 2a 내지 도 2f는 본 발명의 일실시예에 의한 반도체 소자의 금속 식각 방법을 나타내는 단면도이다.2A to 2F are cross-sectional views illustrating a metal etching method of a semiconductor device according to an embodiment of the present invention.
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 더 상세하게는 반도체 소자의 금속 식각 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a metal etching method of a semiconductor device.
종래의 금속 배선의 식각 공정은 크게, BT(break through) 단계, ME(main etch) 단계, OE (over etch) 단계의 순서로 구성된다. 먼저 BT 단계에서는 금속 배선층 상에 형성된 자연 산화막 또는 BARC(bottom anti-reflective coating) 막을 제거한다. 그 다음, ME 단계에서 금속 배선층을 선택 식각하며, OE 단계에서는 ME 단계에서 식각하여 형성한 금속 배선의 CD(critical dimension) 등이 균일하게 되도록 조금 더 식각하는 과정으로 식각 공정을 종료한다.The etching process of a conventional metal wiring is largely composed of a break through (BT) step, a main etch (ME) step, and an over etch (OE) step. First, in the BT step, a natural oxide film or a bottom anti-reflective coating (BARC) film formed on the metal wiring layer is removed. Next, the metallization layer is selectively etched in the ME step, and in the OE step, the etching process is terminated by etching a little more so that the CD (critical dimension) and the like of the metal wire formed by the ME step are uniform.
그리고 나서, 후속 공정이 FEOL(first end of line) 공정인 경우에는 애싱(ashing), 습식 세정을 거치며, BEOL(back end of line) 공정인 경우에는 애싱(ashing), 솔벤트 클리닝(solvent cleaning) 등을 거친다.Then, if the subsequent process is a first end of line (FEOL) process, ashing and wet cleaning are performed. In the case of a BEOL process, ashing and solvent cleaning are performed. Go through
이러한 반도체 제조 공정은 기술의 발전에 따라 초미세 구조를 형성하여 설계 규칙(design rule)이 엄격해지고, 금속 배선이 부식되거나 오염되는 것을 방지하기 위해 더욱 더 많은 폴리머(polymer)를 사용하는 공정이 불가피하게 된다. 따라서, CHF3 또는 N2 가스 등이 첨가되는데, 이는 많은 이물질(byproduct)을 발생하여 챔버 (chamber) 내부에 불규칙하게 증착된다. 한편, 이렇게 형성된 이물질은 굳기가 매우 딱딱하여 후속하는 웨이퍼(wafer) 식각 공정에서 파티클 소스(particle source)로도 작용한다. 이는 기판의 최상위 블록(top block)에서 패턴이 단락되는 패턴 브릿지(pattern bridge)를 유발하여 반도체 소자의 수율을 감소시키는 문제점이 있다. Such semiconductor manufacturing process is inevitable due to the development of technology to form an ultra-fine structure, strict design rules, and to use more and more polymers to prevent corrosion or contamination of metal wiring Done. Thus, CHF 3 or N 2 gas or the like is added, which generates many byproducts and irregularly deposits inside the chamber. On the other hand, the foreign matter thus formed is very hard and also serves as a particle source in the subsequent wafer (etch) process. This causes a pattern bridge in which a pattern is shorted at the top block of the substrate, thereby reducing the yield of the semiconductor device.
본 발명은 반도체 제조 공정에서 폴리머와 PR을 제거하여 챔버의 오염을 방지하고 챔버의 세정 주기를 늘려 반도체 소자의 생산성을 향상시키며, 파티클 소스를 원천적으로 방지하는 반도체 소자의 금속 식각 방법을 제공함에 있다.The present invention provides a metal etching method of a semiconductor device that removes polymer and PR in a semiconductor manufacturing process, thereby preventing contamination of the chamber, increasing the cleaning cycle of the chamber, and improving productivity of the semiconductor device, and preventing particle sources at the source. .
이러한 기술적 과제를 해결하기 위하여, 본 발명은 금속 배선층 상의 자연 산화막과 BARC 막을 제거하는 BT 단계와; 사진 공정에 의하여 금속 배선 패턴을 형 성한 후, 상기 금속 배선 패턴 위에 상기 금속 배선층을 선택 식각하여 금속 배선을 형성하는 ME 단계와; 상기 금속 배선의 식각 상태를 균일한 상태로 더 식각하는 OE 단계와; 상기 ME 단계 및 상기 OE 단계에서 발생한 잔여 PR과 폴리머를 제거하는 PET 단계를 포함하는 반도체 소자의 금속 식각 방법을 제공한다. 여기서, 상기 BT 단계는 CF4 또는 CHF3 가스를 이용하는 플라즈마 식각(plasma etching) 단계인 것이 바람직하다. 한편, 상기 ME 단계는 BCl3, Cl2, CHF3, N2 가스를 이용하는 플라즈마 식각 단계인 것이 바람직하다. 또한, 상기 OE 단계는 BCl3, Cl2, CHF3, N2 가스를 이용하는 플라즈마 식각 단계인 것이 바람직하다. 아울러, 상기 PET 단계는 O2와 CF4를 이용하는 유도 결합 플라즈마(couple induced plasma; CIP) 식각 단계인 것이 바람직하다. 그리고, 상기 PET(post etching treatment) 단계는 식각 장비의 챔버 내의 플라즈마의 직진성은 감소시키고, 플라즈마의 농도를 증가시키는 것이 바람직하다.In order to solve this technical problem, the present invention includes a BT step of removing the natural oxide film and the BARC film on the metal wiring layer; Forming a metal wiring pattern by a photolithography process, and then selectively etching the metal wiring layer on the metal wiring pattern to form a metal wiring; An OE step of further etching the etching state of the metal wiring in a uniform state; It provides a metal etching method of a semiconductor device comprising a PET step to remove the residual PR and the polymer generated in the ME step and the OE step. Here, the BT step is preferably a plasma etching step using a CF 4 or CHF 3 gas. On the other hand, the ME step is preferably a plasma etching step using a BCl 3 , Cl 2 , CHF 3 , N 2 gas. In addition, the OE step is preferably a plasma etching step using the BCl 3 , Cl 2 , CHF 3 , N 2 gas. In addition, the PET step is preferably a coupled induced plasma (CIP) etching step using O 2 and CF 4 . The post etching treatment (PET) may reduce the linearity of the plasma in the chamber of the etching equipment and increase the concentration of the plasma.
이하, 도 1을 참조하여, 본 발명의 일실시예에 의한 반도체 소자의 금속 식각 방법을 개략적으로 설명한다.Hereinafter, a metal etching method of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1.
도 1은 반도체 소자의 제조 공정 중 식각 공정만에 대한 블록도로서, 반도체 소자의 금속 식각 공정은 크게 BT 단계, ME 단계, OE 단계, PET 단계의 순서로 진행된다. BT 단계, ME 단계, OE 단계는 종래기술에 의한 것이나, 본 발명은 금속 식각 공정의 마지막에 PET 단계를 추가하는 것을 특징으로 한다.1 is a block diagram of only an etching process of a semiconductor device manufacturing process, and the metal etching process of the semiconductor device is generally performed in the order of the BT step, the ME step, the OE step, and the PET step. The BT step, the ME step, and the OE step are of the prior art, but the present invention is characterized by adding a PET step at the end of the metal etching process.
이하, 도 2a 내지 도 2f를 참조하여, 본 발명의 일실시예에 의한 반도체 소 자의 금속 식각 방법을 더 상세하게 설명한다.Hereinafter, a metal etching method of a semiconductor device according to an embodiment of the present invention will be described in more detail with reference to FIGS. 2A to 2F.
먼저, 도 2a를 보면 비아(via, 210)가 형성된 층간 절연막(200) 상에 금속 배선층(220), BARC 막(230), PR(240)을 순서대로 도포한다. 여기서 BARC 막(230)은 후속 사진 공정에서 빛의 반사율을 향상시키고, 금속 배선층(220)과 PR(photo resist, 240)의 접착력(adhesion)을 증가시키는 역할을 한다.First, referring to FIG. 2A, the
이어서, 도 2b와 같이 사진 공정에 의하여 금속 배선 패턴을 형성한다. 그 다음 도 2c에서 처럼 금속 배선 패턴 위에 BARC 막(230)과 자연 산화막을 제거하는 BT 단계를 거친다. 이러한 BT 단계는 CF4 또는 CHF3 가스를 이용하는 플라즈마 식각으로 진행한다.Next, as shown in FIG. 2B, a metal wiring pattern is formed by a photolithography process. Then, a BT step of removing the BARC
도 2d에서는 ME 단계로서 금속 배선 패턴 위에 금속 배선층(220)을 선택 식각하여 금속 배선(225)을 형성한다. ME 단계에서는 BCl3, Cl2, CHF3, N2 등의 가스를 이용한 플라즈마 식각을 한다.In FIG. 2D, the
한편, 도 2d에서 보는 바와 같이 중앙에 위치하는 금속 배선(225)은 CD(critical dimension)가 더 길게 형성되어 있는데, 금속 배선(225)의 CD 등에 대해 식각 균일성을 유지하기 위해 도 2e와 같은 OE 단계를 거친다. OE 단계에서는 ME 단계와 마찬가지로 BCl3, Cl2, CHF3, N2 등의 가스를 이용한 플라즈마 식각을 한다.Meanwhile, as shown in FIG. 2D, the
금속 식각 공정의 마지막 단계로서, 도 2f는 PET 단계를 나타낸다. PET 단계에서는 이전의 ME 단계 및 OE 단계에서 발생한 잔여 PR과 폴리머를 제거하는 단 계이다. 종래에는 PET 단계를 거치지 않고, 바로 애싱 및 세정을 하였으나, 본 발명에서는 PET 단계를 추가하여 이물질을 먼저 제거하는 과정을 거친다.As a final step in the metal etching process, FIG. 2F shows the PET step. The PET stage removes residual PR and polymer from previous ME and OE stages. Conventionally, the ashing and washing was performed immediately without going through the PET step, but in the present invention, the foreign material is first removed by adding the PET step.
PET 단계는 주로 CF4, O2 가스를 이용하는 유도 결합 플라즈마 식각을 한다. PET 단계는 층간 절연막 등의 산화막과의 선택비는 최대화하고, PR과 폴리머와의 선택비는 최소화하여 폴리머와 PR의 제거를 원활하게 하는 것을 특징으로 한다.The PET step is mainly inductively coupled plasma etching using CF 4 , O 2 gas. The PET step is characterized by maximizing the selectivity of the oxide film such as an interlayer insulating film and minimizing the selectivity between the PR and the polymer to facilitate the removal of the polymer and the PR.
한편, PET 단계에서는 식각 장비에서 주로 웨이퍼에 인가되는 바이어스 파워(bias power)는 인가하지 않고, 주로 챔버의 탑(top)에 인가되는 소스 파워(source power)만 인가한다. 여기서, 바이어스 파워는 주로 식각의 직진성과 식각률에 영향을 주는 것으로 실질적으로 식각이 이루어지게 하는 것이고, 소스 파워는 주로 플라즈마 농도를 증가시키는 역할을 하는 것으로서 식각 특성을 저하시키고 식각의 직진성도 상실시킨다. 따라서, PET 단계에서는 바이어스 파워는 인가하지 않고, 소스 파워만 인가하는 것에 의해서 금속 배선 및 층간 절연막을 거의 식각하지 않고, 금속 배선 상부와 챔버의 측벽에 있는 PR과 이물질만을 제거하게 된다.On the other hand, in the PET step, the bias power is mainly applied to the wafer in the etching equipment, and only the source power applied to the top of the chamber is applied. Here, the bias power mainly affects the straightness and the etching rate of the etching, and the etching is substantially performed. The source power mainly serves to increase the plasma concentration, thereby deteriorating the etching characteristics and losing the straightness of the etching. Therefore, in the PET step, the bias power is not applied, and only the source power is applied, thereby almost eliminating the metal wiring and the interlayer insulating film, and removing only the PR and the foreign substances on the upper side of the metal wiring and the chamber.
따라서, PET 단계의 추가에 의해 이물질에 의한 챔버의 오염을 억제할 수 있으며, 이로 인해, 챔버의 세정 주기가 더 연장된다. 일반적인 경우 챔버의 세정에 많은 시간이 소요됨에 비추어, 세정 주기가 연장되면 반도체 소자의 생산성을 향상하는 효과를 가진다. 그리고, 이물질이 챔버 내벽에 딱딱하게 굳어 파티클 소스로 작용하는 것을 억제한다.Therefore, the addition of the PET step can suppress contamination of the chamber by foreign matters, thereby extending the cleaning cycle of the chamber further. In general, since the cleaning of the chamber takes a long time, if the cleaning cycle is extended has the effect of improving the productivity of the semiconductor device. In addition, the foreign matter hardens on the inner wall of the chamber to suppress the particle source.
이후, 반도체 소자의 금속 식각 공정에 이어서 애싱 공정 및 세정 공정을 거 친다.Thereafter, the metal etching process of the semiconductor device is followed by an ashing process and a cleaning process.
지금까지 본 발명의 바람직한 실시예에 대해 설명하였으나, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명의 본질적인 특성을 벗어나지 않는 범위 내에서 변형된 형태로 구현할 수 있을 것이다. 그러므로 여기서 설명한 본 발명의 실시예는 한정적인 관점이 아니라 설명적인 관점에서 고려되어야 하고, 본 발명의 범위는 상술한 설명이 아니라 특허청구범위에 나타나 있으며, 그와 동등한 범위 내에 있는 모든 차이점은 본 발명에 포함되는 것으로 해석되어야 한다.Although a preferred embodiment of the present invention has been described so far, those skilled in the art will be able to implement in a modified form without departing from the essential characteristics of the present invention. Therefore, the embodiments of the present invention described herein are to be considered in descriptive sense only and not for purposes of limitation. Should be interpreted as being included in.
본 발명에 따르면, 반도체 소자의 금속 식각 공정에서 마지막 공정으로 PET 단계를 추가하는 구성에 의하여, 폴리머와 PR을 제거하여 챔버의 오염을 억제함으로써, 챔버의 세정 주기를 늘려 반도체 소자의 생산성을 향상시키는 효과가 있다. 아울러, 파티클 소스를 원천적으로 방지하여 반도체 소자의 질을 향상시키는 효과가 있다.According to the present invention, by adding a PET step as a final step in the metal etching process of the semiconductor device, by removing the polymer and PR to suppress the contamination of the chamber, to increase the cleaning cycle of the chamber to improve the productivity of the semiconductor device It works. In addition, by preventing the source of particles at the source has the effect of improving the quality of the semiconductor device.
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| KR19980060606A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Metal wiring formation method of semiconductor device |
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| WO2020072762A1 (en) * | 2018-10-05 | 2020-04-09 | Lam Research Corporation | Removing metal contamination from surfaces of a processing chamber |
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