KR100434312B1 - Method for making contact hole in semiconductor device - Google Patents
Method for making contact hole in semiconductor device Download PDFInfo
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- KR100434312B1 KR100434312B1 KR10-2000-0079675A KR20000079675A KR100434312B1 KR 100434312 B1 KR100434312 B1 KR 100434312B1 KR 20000079675 A KR20000079675 A KR 20000079675A KR 100434312 B1 KR100434312 B1 KR 100434312B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 캐패시터의 콘택홀을 식각할 때 감광층 패턴과의 고선택비를 확보는 물론 균일한 프로파일이 가능한 반도체 소자의 캐패시터의 제조 방법에 관한 것으로, 반도체 기판상에 제 1 산화층과 질화층과 제 2 산화층을 적층하고 제 2 산화층상에 감광층 패턴을 형성하는 제 1단계와, 상기 감광층 패턴을 마스크로 하여 제 2 산화층을 식각하는 제 2 단계와, 상기 제 2 단계에서 질화층상의 생성된 폴리머를 제거하는 제 3 단계와, 상기 감광층 패턴을 마스크로 하여 질화층과 제 1 산화층을 식각하는 제 4 단계와, 상기 제 2 단계에서 감광층 패턴상에 생성된 폴리머를 제거하는 제 5 단계를 포함하여 이루어진다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device capable of ensuring a high selectivity with a photosensitive layer pattern when etching a contact hole of a capacitor, as well as a uniform profile, and comprising a first oxide layer and a nitride layer on a semiconductor substrate. A first step of laminating a second oxide layer and forming a photosensitive layer pattern on the second oxide layer, a second step of etching the second oxide layer using the photosensitive layer pattern as a mask, and creation of a nitride layer image in the second step A third step of removing the polymer, a fourth step of etching the nitride layer and the first oxide layer using the photosensitive layer pattern as a mask, and a fifth step of removing the polymer formed on the photosensitive layer pattern in the second step. A step is made.
Description
본 발명은 반도체 소자에 관한 것으로, 특히 캐패시터의 콘택홀을 식각할 때 감광층 패턴과의 고선택비를 확보할 수 있고 균일한 프로파일이 가능한 반도체 소자의 캐패시터 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a capacitor of a semiconductor device capable of securing a high selectivity with a photosensitive layer pattern when etching a contact hole of a capacitor and having a uniform profile, and a manufacturing method thereof.
반도체 소자가 집적화되고 디자인룰(design rule)이 줄어들면서 콘택홀의 사이즈도 감소하여 재현성을 가지며 안정적인 공정으로 콘택홀을 식각하는 문제가 대두되었다.As semiconductor devices are integrated and design rules are reduced, the size of contact holes is also reduced, resulting in a problem of etching contact holes with a reproducible and stable process.
그러나 콘택홀의 사이즈가 줄어들면서 감광층 패턴과 감광층 패턴의 하지층인 산화층과의 필요한 선택비의 확보가 어렵고, 또한 식각 가스로 고탄소(high carbon) 가스를 사용하면서 발생하는 폴리머(polymer)가 제거되는 않고, 특히 층간 절연층으로 질화층이 개재된 경우는 식각 잔막이 불균일하게 되는 문제가 있다.However, as the size of the contact hole decreases, it is difficult to secure the necessary selectivity between the photosensitive layer pattern and the oxide layer, which is the underlying layer of the photosensitive layer pattern, and polymers generated by using high carbon gas as an etching gas. There is a problem that the etching residual film becomes non-uniform, in particular, when the nitride layer is interposed with the interlayer insulating layer without being removed.
이하 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 콘택 홀 형성 방법에 관하여 설명하면 다음과 같다.Hereinafter, a method for forming a contact hole in a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1a와 도 1b는 종래 기술의 반도체 소자의 콘택 홀 형성 방법의 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device of the prior art.
도 1a와 같이, 반도체 기판(1)상에 제 1 산화층(2)을 형성하고, 제 1 산화층(2)상에 질화층(3)을 형성한다.As shown in FIG. 1A, the first oxide layer 2 is formed on the semiconductor substrate 1, and the nitride layer 3 is formed on the first oxide layer 2.
그리고 질화층(3)상에 제 2 산화층(4)을 적층하고, 제 2 산화층(4)상에 감광층을 도포하고 콘택홀(6)이 형성되는 영역의 감광층을 노광 및 현상하여 감광층 패턴(5)을 형성한다.The second oxide layer 4 is laminated on the nitride layer 3, the photosensitive layer is coated on the second oxide layer 4, and the photosensitive layer in the region where the contact hole 6 is formed is exposed and developed. The pattern 5 is formed.
도 1b와 같이, 감광층 패턴(5)을 식각 마스크로 사용하여 제 2 산화층(4), 질화층(3) 그리고 제 1 산화층(2)을 식각하여 콘택홀(6)을 형성한다.As shown in FIG. 1B, the second oxide layer 4, the nitride layer 3, and the first oxide layer 2 are etched using the photosensitive layer pattern 5 as an etching mask to form a contact hole 6.
이때 콘태홀(6)을 식각할 때 식각가스는 CF4와 CHF3 가스의 유량비를 이용하거나 고탄소(high carbon)가스를 사용한다.At this time, when etching the contact hole 6, the etching gas uses a flow ratio of CF4 and CHF3 gas or uses a high carbon gas.
이와 같은 종래 기술의 반도체 소자의 캐패시터는 다음과 같은 문제가 있다.Such a capacitor of a semiconductor device of the prior art has the following problems.
첫 번째, 산화층과 산화층사이에 500 Å이상의 질화층이 개재되어 있는 절연층을 식각할 때 식각 선택비를 확보하는 데 한계가 있다.First, there is a limit in securing an etch selectivity when etching an insulating layer having a nitride layer of 500 mV or more interposed between the oxide layer and the oxide layer.
즉, CF4와 CHF3의 유량비를 이용하여 선택비를 조절하지만, 가능한 선택비가 한계가 있으므로 식각시 고탄소(high carbon)의 가스를 이용하여 선택비를 높이는 데, 이 경우 질화층은 식각되지 않아 콘택홀 형성이 불가능하다.두 번째, 고탄소 가스를 사용함으로 인해 발생되는 폴리머를 제거하기 어렵다.In other words, the selectivity is controlled using the flow rate ratio of CF 4 and CHF 3 , but the selectivity is limited, so the selectivity is increased by using high carbon gas during etching, in which case the nitride layer is not etched. It is impossible to form contact holes, and secondly, it is difficult to remove polymers generated by using high carbon gas.
세 번째, 고집적 소자에 적용하는 콘택홀 크기가 급격하게 감소함에 따라 감광층 패턴의 두께가 얇아지고 선택비는 4 : 1 이상이 되기 어려워 선택비가 낮아져 식각 조건이 열악하여 진다.Third, as the contact hole size applied to the highly integrated device is drastically reduced, the thickness of the photosensitive layer pattern becomes thinner and the selectivity is less than 4: 1, so the selectivity is lowered and the etching conditions become poor.
도 1a와 도 1b는 종래 기술의 반도체 소자의 콘택홀 형성 방법의 공정 단면도1A and 1B are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device of the related art.
도 2a내지 도 2d는 본 발명에 따른 반도체 소자의 콘택홀 제조 방법의 공정 단면도2A to 2D are cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 제 1 산화층21 semiconductor substrate 22 first oxide layer
23 : 질화층 24 : 제 2 산화층23 nitride layer 24 second oxide layer
25 : 감광층 패턴 26 : 콘택홀25 photosensitive layer pattern 26 contact hole
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 콘택홀 형성 방법은 반도체 기판상에 제 1 산화층과 질화층과 제 2 산화층을 적층하고 제 2 산화층상에 감광층 패턴을 형성하는 제 1 단계와, 상기 감광층 패턴을 마스크로 하여 제 2 산화층을 식각하는 제 2 단계와, 상기 제 2 단계에서 질화층상의 생성된 폴리머를 제거하는 제 3 단계와, 상기 감광층 패턴을 마스크로 하여 질화층과 제 1 산화층을 식각하는 제 4 단계와, 상기 제 2 단계에서 감광층 패턴상에 생성된 폴리머를 제거하는 제 5 단계를 포함하여 이루어짐을 특징을 한다.이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 콘택홀 형성 방법에 관하여 상세히 설명하면 다음과 같다.A method of forming a contact hole in a semiconductor device according to the present invention for achieving the above object comprises a first step of laminating a first oxide layer, a nitride layer and a second oxide layer on a semiconductor substrate and forming a photosensitive layer pattern on the second oxide layer. And a second step of etching the second oxide layer using the photosensitive layer pattern as a mask, a third step of removing the polymer formed on the nitride layer in the second step, and a nitride layer using the photosensitive layer pattern as a mask. And a fourth step of etching the first oxide layer and a fifth step of removing the polymer formed on the photosensitive layer pattern in the second step. Hereinafter, the present invention will be described with reference to the accompanying drawings. The contact hole forming method of the semiconductor device according to the present invention will be described in detail as follows.
도 2a내지 도 2d는 본 발명에 따른 반도체 소자의 콘택홀 형성 방법의 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.
도 2a와 같이, 반도체 기판(21)상에 제 1 산화층(22)을 형성하고, 제 1 산화층(22)상에 질화층(23)을 형성한다.As shown in FIG. 2A, the first oxide layer 22 is formed on the semiconductor substrate 21, and the nitride layer 23 is formed on the first oxide layer 22.
그리고 질화층(23)상에 제 2 산화층(24)을 적층하고, 제 2 산화층(24)상에 감광층을 도포하고 콘택홀(26)이 형성되는 영역의 감광층을 노광 및 현상하여 감광층 패턴(25)을 형성한다.The second oxide layer 24 is laminated on the nitride layer 23, the photosensitive layer is coated on the second oxide layer 24, and the photosensitive layer in the region where the contact hole 26 is formed is exposed and developed. The pattern 25 is formed.
계속해서 감광층 패턴(25)을 식각 마스크로 사용하여 1 단계로 감광층 패턴(25)과 하지층인 제 2 산화층(24)간에 높은 선택비를 확보하고 수직 프로파일을 얻기 위해 고탄소(high carbon)가스인 CxFy와 CxHyFz와 O2, Ar 가스 조합을 이용하여 제 2 산화층(24)을 식각한다.이때, 상기 감광층 패턴(25)의 상면과 상기 2 산화층(24)의 식각으로 노출되는 질화층(23)상에 폴리머(26)가 형성된다.Subsequently, using the photosensitive layer pattern 25 as an etching mask, high carbon (high carbon) is obtained in order to obtain a high selectivity and obtain a vertical profile between the photosensitive layer pattern 25 and the underlying second oxide layer 24 in one step. The second oxide layer 24 is etched using a combination of gases CxFy, CxHyFz, O 2 and Ar. At this time, the nitride layer exposed by etching the upper surface of the photosensitive layer pattern 25 and the second oxide layer 24 is etched. Polymer 26 is formed on layer 23.
이어, 이후에 진행되는 식각 공정에서 감광층 패턴(25)의 손실을 최소한으로 줄여 균일한 식각 특성을 얻기 위해 도 2b에 도시된 바와 같이 낮은 RF 파워(power)조건에서 CxHyFz, O2, Ar의 식각 가스를 이용하여 상기 질화층(23)상에 형성된 폴리머(polymer)(26)를 제거한다.즉, 질화층(23)상의 폴리머(26)를 제거함으로써 이후에 균일한 식각이 가능하다. 여기서 감광층 패턴(25)과 하지층인 제 2 산화층(24)의 식각 선택비는 10 : 1 이상이 된다.Subsequently, CxHyFz, O 2 , and Ar under low RF power conditions as shown in FIG. 2B to minimize the loss of the photosensitive layer pattern 25 in the subsequent etching process to obtain uniform etching characteristics. The etching gas is used to remove the polymer 26 formed on the nitride layer 23. That is, by removing the polymer 26 on the nitride layer 23, uniform etching is possible later. Here, the etching selectivity of the photosensitive layer pattern 25 and the second oxide layer 24 serving as the underlying layer is 10: 1 or more.
도 2c와 같이, CxHyFz, O2, Ar 가스의 조합을 이용하여 질화층(23)과 제 1 산화층(22)을 식각한다. 이때 질화층(23) 뿐만아니라 제 1 산화층(22)도 균일하게 식각된다.As illustrated in FIG. 2C, the nitride layer 23 and the first oxide layer 22 are etched using a combination of CxHyFz, O 2 and Ar gases. At this time, not only the nitride layer 23 but also the first oxide layer 22 is uniformly etched.
그리고 RF 파워 조건을 낮은 조건에서 진행함으로써 감광층 패턴(25)과의 고선택비를 확보할 수 있으며와 데미지(damage)를 감소시킬 수 있다.In addition, by performing the RF power condition in a low condition, it is possible to secure a high selectivity with the photosensitive layer pattern 25 and to reduce damage.
도 2d와 같이, 상기 감광층 패턴(25)상에 남아있는 폴리머(26)를 제거하고 콘택홀(6) 하면의 손상을 제거한다.As shown in FIG. 2D, the polymer 26 remaining on the photosensitive layer pattern 25 is removed and damage to the bottom surface of the contact hole 6 is removed.
상기 폴리머(26) 및 손상을 제거하는 방법은 CxHyFz, O2, Ar 가스의 조합으로 식각을 진행하게 되는 데 이 때 산소를 충분한 첨가하여 폴리머가 잘 제거되도록 한다.The polymer 26 and the method of removing the damage are etched by a combination of CxHyFz, O 2 , and Ar gas. At this time, sufficient oxygen is added to remove the polymer well.
식각 가스의 구성은 CxFy, CxHyFz, O2, Ar 가스의 조합으로 되어 있으며, CxFy 및 CxHyFz의 역할은 플라즈마 내에서 주요 식각 소오스(source) 가스로 작용하며, 가스 비율의 증가로 식각 가공성이 증가한다.The composition of the etching gas is a combination of CxFy, CxHyFz, O 2 , and Ar gas, and the role of CxFy and CxHyFz acts as the main etching source gas in the plasma, and the etching processability is increased by increasing the gas ratio. .
그리고 O2가스의 역할은 플라즈마 내에서 식각 보조 가스로 작용하며, 가스 플로우의 증가로 식각 가공성 및 부분적으로 프로파일의 조정이 가능하고 또한 폴리머의 제거가 가능하다.In addition, the role of the O 2 gas acts as an etch assist gas in the plasma, and the increase in gas flow enables the etching processability and the partial profile adjustment and the removal of the polymer.
Ar 가스의 역할은 플라즈마 내에서 전체 가스를 잘 희석하여 안정한 플라즈마를 생성하는 기능을 한다.The role of Ar gas functions to dilute the entire gas well in the plasma to generate a stable plasma.
이와 같은 본 발명에 따른 반도체 소자의 콘택홀 형성 방법은 다음과 같은 효과가 있다.Such a method for forming a contact hole in a semiconductor device according to the present invention has the following effects.
첫 번째, 질화막상에 생성된 폴리머를 제거하여 포토레지스트 패턴의 손실을 최소화할 수 있으므로 질화막과 제 1 산화막 식각시 균일한 식각이 가능하다.두 번째, 식각 공정을 고탄소 가스뿐만 아니라 산소 가스(O2)가 포함된 분위기에서 실시하므로 식각 가공성이 향상되고 부분적인 프로파일 조정이 가능하며 폴리머 제거가 가능해 진다.First, since the loss of the photoresist pattern can be minimized by removing the polymer formed on the nitride film, uniform etching is possible during etching of the nitride film and the first oxide film. Second, the etching process uses oxygen gas ( It is carried out in an atmosphere containing O 2 ), resulting in improved etching processability, partial profile adjustment, and polymer removal.
세 번째, 아르곤 가스(Ar)가 포함된 분위기에서 식각이 진행되므로 전체 가스를 잘 희석하여 안정한 플라즈마가 생성된다.Third, since etching proceeds in an atmosphere containing argon gas (Ar), the entire gas is well diluted to generate stable plasma.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0870043A (en) * | 1994-08-30 | 1996-03-12 | Nkk Corp | Method for manufacturing semiconductor device |
| JPH09120990A (en) * | 1995-10-25 | 1997-05-06 | Sony Corp | Formation of connecting hole |
| JPH11330045A (en) * | 1998-05-08 | 1999-11-30 | Nec Corp | Method for etching laminated film of oxide film and silicon layer |
| WO2000055903A1 (en) * | 1999-03-15 | 2000-09-21 | Koninklijke Philips Electronics N.V. | Methods for reducing semiconductor contact resistance |
| KR20010082216A (en) * | 1998-09-30 | 2001-08-29 | 리차드 에이치. 로브그렌 | Method of plasma etching dielectric materials |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0870043A (en) * | 1994-08-30 | 1996-03-12 | Nkk Corp | Method for manufacturing semiconductor device |
| JPH09120990A (en) * | 1995-10-25 | 1997-05-06 | Sony Corp | Formation of connecting hole |
| JPH11330045A (en) * | 1998-05-08 | 1999-11-30 | Nec Corp | Method for etching laminated film of oxide film and silicon layer |
| KR20010082216A (en) * | 1998-09-30 | 2001-08-29 | 리차드 에이치. 로브그렌 | Method of plasma etching dielectric materials |
| WO2000055903A1 (en) * | 1999-03-15 | 2000-09-21 | Koninklijke Philips Electronics N.V. | Methods for reducing semiconductor contact resistance |
| KR20010071259A (en) * | 1999-03-15 | 2001-07-28 | 롤페스 요하네스 게라투스 알베르투스 | Methods for reducing semiconductor contact resistance |
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