US20070128849A1 - Waferless automatic cleaning after barrier removal - Google Patents
Waferless automatic cleaning after barrier removal Download PDFInfo
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- US20070128849A1 US20070128849A1 US11/672,129 US67212907A US2007128849A1 US 20070128849 A1 US20070128849 A1 US 20070128849A1 US 67212907 A US67212907 A US 67212907A US 2007128849 A1 US2007128849 A1 US 2007128849A1
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- 238000004140 cleaning Methods 0.000 title claims abstract description 63
- 230000004888 barrier function Effects 0.000 title claims abstract description 38
- 235000012431 wafers Nutrition 0.000 claims abstract description 48
- 239000007789 gas Substances 0.000 claims abstract description 47
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 37
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 20
- 239000001301 oxygen Substances 0.000 claims abstract description 20
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 20
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 18
- 238000012545 processing Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 7
- 239000012530 fluid Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 26
- 230000008569 process Effects 0.000 description 19
- 229920000642 polymer Polymers 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 230000015654 memory Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 230000006641 stabilisation Effects 0.000 description 6
- 238000011105 stabilization Methods 0.000 description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000012546 transfer Methods 0.000 description 3
- 241000699666 Mus <mouse, genus> Species 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 241000699670 Mus sp. Species 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003121 nonmonotonic effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000003245 working effect Effects 0.000 description 1
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- B09B5/00—Operations not covered by a single other subclass or by a single other group in this subclass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- C—CHEMISTRY; METALLURGY
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61L—METHODS OR APPARATUS FOR STERILISING MATERIALS OR OBJECTS IN GENERAL; DISINFECTION, STERILISATION OR DEODORISATION OF AIR; CHEMICAL ASPECTS OF BANDAGES, DRESSINGS, ABSORBENT PADS OR SURGICAL ARTICLES; MATERIALS FOR BANDAGES, DRESSINGS, ABSORBENT PADS OR SURGICAL ARTICLES
- A61L2209/00—Aspects relating to disinfection, sterilisation or deodorisation of air
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- Y10S438/905—Cleaning of reaction chamber
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Abstract
A method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the wafer has a barrier layer over the wafer and a dielectric layer over the barrier layer. The dielectric layer is etched. The barrier layer is opened. The wafer is removed from the etch chamber. A waferless automatic cleaning of the etch chamber without the wafer is provided. The waferless automatic cleaning comprises providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.
Description
- This application is a divisional application and claims priority of U.S. patent Ser. No. 10/828,065, entitled “WAFERLESS AUTOMATIC CLEANING AFTER BARRIER REMOVAL,” filed on Apr. 19, 2004, naming Yao et al. as inventors, which is incorporated herein by reference for all purposes.
- 1. Field of the Invention
- The invention relates to semiconductor devices. Relates to the cleaning of etch chambers after a wafer has been removed to improve etch performance.
- 2. Description of the Related Art
- In the formation of semiconductor devices, a barrier layer is etched. Such barrier layers may be silicon nitride SiN. The low power etching of the barrier layer may cause deposition on the etch chamber. It would be desirable to provide a process that cleans the deposition from the etch chamber.
- To achieve the foregoing and in accordance with the purpose of the present invention, a method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the wafer has a barrier layer over a conductive layer over the wafer and a dielectric layer over the barrier layer. The dielectric layer is etched. The barrier layer is opened. The wafer is removed from the etch chamber. A waferless automatic cleaning of the etch chamber without the wafer is provided. The waferless automatic cleaning comprises providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.
- In another manifestation of the invention a method for cleaning an etch chamber after a barrier layer opening has been performed and a wafer has been removed from the etch chamber to empty the etch chamber is provided. A waferless automatic cleaning gas comprising oxygen and nitrogen is provided to the etch chamber. A waferless automatic cleaning plasma is formed from the waferless automatic cleaning gas to clean the etch chamber.
- In another manifestation of the invention, an apparatus for etching a feature in a dielectric layer and opening barrier layers for a plurality of wafers is provided. An etch chamber is provided. An upper electrode is provided within the etch chamber. A lower electrode is provided within the etch chamber. An RF source is electrically connected to at least one of the upper electrode and lower electrode. A gas source is in fluid connection with the etch chamber to provide gas into the etch chamber. A controller is controllably connected to the RF source and the gas source. The controller comprises computer readable code for etching the dielectric layer, computer readable code for opening the barrier layer, and computer readable code for providing a waferless automatic cleaning of the etch chamber after a wafer has been removed from the etch chamber to empty the etch chamber after the opening of a barrier layer. The computer readable media for providing waferless automatic cleaning comprises computer readable code for providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and computer readable code for forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.
- These and other features of the present invention will be described in more details below in the detailed description of the invention and in conjunction with the following figures.
- The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
-
FIG. 1 is a high level flow chart for part of a process for forming a feature in a dielectric layer that uses the invention. - FIGS. 2A-C are a schematic cross-sectional views of part of a wafer that may be used in the inventive process.
-
FIG. 3 is a schematic view of an etch chamber that may be used in a preferred embodiment of the invention. -
FIGS. 4A and 4B illustrate a computer system, which is suitable for implementing a controller. -
FIG. 5 is a more detailed flow chart of a waferless automatic clean process. - The present invention will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
- To facilitate understanding,
FIG. 1 is a high level flow chart for part of a process for forming a feature in a dielectric layer that uses the invention. A wafer is placed in an etch chamber (step 104). A dielectric etch is performed on the wafer (step 108). After the dielectric etch the barrier layer is opened (step 112). The wafer is then removed from the etch chamber (step 116). The empty etch chamber is then subjected to a waferless automatic clean using a plasma of oxygen and nitrogen. - In an example of the invention, a wafer is placed in an etch chamber (step 104).
FIG. 2A is a schematic cross-sectional view of part of awafer 200 that may be used in the inventive process. Thewafer 200 in this example comprises at least oneconductive contact 204 over asubstrate 208. Abarrier layer 210 is placed over theconductive contact 204. If theconductive contact 204 in this example is copper. In this example the barrier layer is silicon nitride (SiN). In other embodiments, the barrier layer may be silicon carbide (SiC). The barrier layer may have dopants. Adielectric etch layer 216 is placed over thebarrier layer 210. In this example, the dielectric etch layer is a silicon oxide based dielectric layer or a low-k (k<4.0) dielectric material. Aphotoresist mask 220 is placed over thedielectric etch layer 216. In this example, a dual damascene feature is being formed using a via first process. In such a process, a via 218 has been etched into thedielectric etch layer 216. A photoresist mask for the via etch has been removed and aphotoresist mask 220 for a trench pattern has been formed. In addition, in this example, a viaplug 212 has been formed in thevia 218. Although the discussed layers are shown to be on top of each other (i.e. the photoresist mask is directly on top of the dielectric etch layer), one or more layers may be placed between such layers, (i.e. an anti-reflective layer may be between the photoresist mask and the dielectric etch layer). This is why in the specification and claims various layers are described as being “over” other layers. Possible intermediate layers are not shown for the sake of clarity. -
FIG. 3 is a schematic view of anetch chamber 300 that may be used for opening the barrier layer. Theetch chamber 300 comprises confinement rings 302, anupper electrode 304, alower electrode 308, agas source 310, and anexhaust pump 320. Thegas source 310 comprises a dielectricetch gas source 312, a barrieropen gas source 316, anoxygen gas source 318, and anitrogen gas source 319. Various gases may be used for multiple processes. In such a case, the different gas sources may be combined. For example, nitrogen may be used during the barrier open. In such a case, only a single nitrogen source may be provided. The various gas sources are shown to schematically illustrate the workings of the invention. Thegas source 310 may comprise additional gas sources. Withinplasma processing chamber 300, thesubstrate 200 is positioned upon thelower electrode 308. Thelower electrode 308 incorporates a suitable substrate chucking mechanism (e.g., electrostatic, mechanical clamping, or the like) for holding thesubstrate 200. Thereactor top 328 incorporates theupper electrode 304 disposed immediately opposite thelower electrode 308. Theupper electrode 304,lower electrode 308, and confinement rings 302 define the confined plasma volume. Gas is supplied to the confined plasma volume by thegas source 310 and is exhausted from the confined plasma volume through the confinement rings 302 and an exhaust port by theexhaust pump 320. AnRF source 348 is electrically connected to thelower electrode 308. Theupper electrode 304 is grounded.Chamber walls 352 surround the confinement rings 302, theupper electrode 304, and thelower electrode 308. TheRF source 348 may comprise a 27 MHz power source and a 2 MHz power source. An Exelan DFC™dielectric etcher, which is made by LAM Research Corporation™ of Fremont, Calif., was used in this example of the invention. Different combinations of connecting RF power to the electrode are possible in other embodiments, such as having an RF source connected to theupper electrode 304. -
FIGS. 4A and 4B illustrate acomputer system 400, which is suitable for implementing acontroller 335 used in embodiments of the present invention.FIG. 4A shows one possible physical form of the computer system. Of course, the computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge super computer.Computer system 400 includes amonitor 402, adisplay 404, ahousing 406, adisk drive 408, akeyboard 410, and amouse 412.Disk 414 is a computer-readable medium used to transfer data to and fromcomputer system 400. -
FIG. 4B is an example of a block diagram forcomputer system 400. Attached tosystem bus 420 is a wide variety of subsystems. Processor(s) 422 (also referred to as central processing units or CPUs) are coupled to storage devices, includingmemory 424.Memory 424 includes random access memory (RAM) and read-only memory (ROM). As is well known in the art, ROM acts to transfer data and instructions uni-directionally to the CPU and RAM is used typically to transfer data and instructions in a bi-directional manner. Both of these types of memories may include any suitable of the computer-readable media described below. A fixeddisk 426 is also coupled bi-directionally toCPU 422; it provides additional data storage capacity and may also include any of the computer-readable media described below.Fixed disk 426 may be used to store programs, data, and the like and is typically a secondary storage medium (such as a hard disk) that is slower than primary storage. It will be appreciated that the information retained within fixeddisk 426 may, in appropriate cases, be incorporated in standard fashion as virtual memory inmemory 424.Removable disk 414 may take the form of any of the computer-readable media described below. -
CPU 422 is also coupled to a variety of input/output devices, such asdisplay 404,keyboard 410,mouse 412 andspeakers 430. In general, an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers.CPU 422 optionally may be coupled to another computer or telecommunications network usingnetwork interface 440. With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments of the present invention may execute solely uponCPU 422 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing. - In addition, embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
- In this example, the
dielectric etch layer 220 is a silicon oxide based dielectric. A trench etch is used to etch the dielectric etch layer (step 108) to form thetrench 230, as shown inFIG. 2B . Thephotoresist mask 220 and plug 212 may be stripped away during or after the trench etch. - The barrier layer is then opened (step 210), as shown in
FIG. 2C . An example of an etch recipe for opening a SiN barrier layer is as follows: - First, the lower electrode is cooled to 30° C. A stabilization step is provided. In this stabilization step, the chamber pressure is set to 150 mTorr. No power is provided by the
RF source 348. A barrier open stabilization gas flow of 200 sccm N2, 50 sccm CF4, and 10 sccm CHF3 is provided for 15 seconds. - Next, a plasma strike step is provided. The chamber pressure is maintained at 150 mTorr. 100 watts at 27 MHz and 100 watts at 2 MHz are provided by the
RF source 348. A strike gas flow of 200 sccm N2, 50 sccm CF4, and 10 sccm CHF3 is provided for 5 seconds. - Next, a main etch step is provided. The chamber pressure is maintained at 150 mTorr. 200 watts at 27 MHz and 400 watts at 2 MHz are provided by the
RF source 348. The lower electrode is cooled to 30° C. A main etch gas flow of 200 sccm N2, 50 sccm CF4, 10 sccm CHF3, and 5 sccm O2 is provided for 18 seconds. - Finally, an over etch step is provided. The chamber pressure is maintained at 150 mTorr. 200 watts at 27 MHz and 400 watts at 2 MHz are provided by the
RF source 348. The lower electrode is cooled to 30° C. An over etch gas flow of 200 sccm N2, 50 sccm CF4, and 10 sccm CHF3 is provided for 17 seconds. - In this example, a post etch treatment is provided after the barrier open, according to the following recipe. First, a stabilization step is provided. In this stabilization step, the chamber pressure is set to 200 mTorr. No power is provided by the
RF source 348. The lower electrode is cooled to 30° C. A post etch treatment stabilization gas flow of 800 sccm H2 and 200 sccm Ar is provided for 20 seconds. - Next, a plasma strike step is provided. The chamber pressure is maintained at 200 mTorr. 200 watts at 27 MHz and 300 watts at 2 MHz are provided by the
RF source 348. The lower electrode is cooled to 30° C. A strike gas flow of 800 sccm H2 and 200 sccm Ar is provided for 5 seconds. - Finally, a main post etch treatment step is provided. The chamber pressure is maintained at 200 mTorr. 1,000 watts at 27 MHz and 0 watts at 2 MHz are provided by the
RF source 348. The lower electrode is cooled to 30° C. A main post etch treatment gas flow of 800 sccm H2 is provided for 15 seconds. The post etch treatment may be used to clean polymer and other deposits from the wafer. - The
wafer 200 is removed from the etch chamber 300 (step 116). A waferless automatic clean is then performed on the empty etch chamber 300 (step 120). -
FIG. 5 is a more detailed flow chart of a waferless automatic clean process used in this example. A waferless automatic cleaning gas comprising oxygen and nitrogen is provided into the etch chamber 300 (step 504). In this example, 1,000 sccm of N2 and 10 sccm of O2 is provided. The pressure in the etch chamber in this example is maintained at 680 mTorr. A waferless automatic cleaning plasma is formed from the waferless automatic cleaning gas mixture (step 508). In this example, 500 watts at 27 MHz and 0 watts are 2 MHz are provided by theRF source 348 for 20 seconds. The resulting plasma cleans the chamber (step 512). - The flow ratio of oxygen to nitrogen is preferably between 1:200 to 1:50. More preferably, the flow ratio of oxygen to nitrogen is between 1:99 to 2:98. In the preferred embodiment, the waferless automatic cleaning gas consists essentially of nitrogen and oxygen. In other embodiments, other gases or diluents may be added. Preferably, the RF source provides more than 300 watts at a high frequency between 12-50 MHz and 0-50 watts at a low frequency between 0.1-10 MHz. More preferably, the RF source provides between about 300-1,000 watts at a high frequency between 12-50 MHz and 0-25 watts at a low frequency between 0.1-10 MHz. Most preferably, the RF source provides about 500 watts at a high frequency of about 27 MHz and about 0 watts at any low frequency below 10 MHz. Preferably, during the waferless automatic cleaning the chamber pressure is between 250-1,000 mTorr. More preferably, during the waferless automatic cleaning the chamber pressure is between 400-900 mTorr.
- In the preferred embodiment, the waferless automatic cleaning is done after each wafer is removed after a barrier open is performed. Other embodiments may allow less frequent waferless automatic cleaning.
- The etch rate and etch uniformity were measured for each wafer for a number wafers being processed, thus having a number of waferless automatic cleanings using the inventive waferless automatic cleaning process with a waferless automatic cleaning gas of nitrogen with 1-2% oxygen. This process was compared to other waferless automatic cleaning processes.
- The etch rate and etch uniformity were measured for the first and two hundredth wafer being processed, where oxygen only was used for the waferless automatic cleaning. Using a waferless automatic cleaning with only oxygen as the waferless automatic cleaning gas caused a process shift of 12% between the first and two hundredth wafers. Etch uniformity tests using only oxygen as the waferless automatic cleaning gas shows the uniformity changes, which indicates that either the center or edge etch rates vary during the etching of 200 wafers. In addition, it has been found that waferless automatic cleaning using only oxygen results in a build up of polymer on the upper electrode.
- A waferless automatic cleaning was also performed using only nitrogen, without any oxygen. It was found that such a waferless automatic cleaning process did not cause polymer build up on the upper electrode, but did cause polymer build up on the lower electrode.
- It has also been found that when no waferless automatic cleaning is provided the lower electrode becomes contaminated, which causes particle contamination.
- It was found that using the inventive waferless automatic cleaning that during the etching of 1500 wafers there was an etch process shift of less than 7% with a non-monotonic trend. Etch uniformity using the inventive waferless automatic cleaning was stable. Therefore the invention provides a more consistent wafer to wafer etch rate over a large number of wafers (i.e. greater than 1,500) and improves etch rate uniformity and stability for an individual wafer. It has been found that the inventive waferless automatic cleaning also prevents polymer build up on both the upper and the lower electrode.
- Without being limited by theory, it is believed that low power used in the barrier layer open step and the chemistry of SiN provide contaminants within the etch chamber that are difficult to clean. It has been found that using a waferless automatic cleaning gas of only oxygen results in a process shift and polymer build up at the top electrode area. On the other hand, it has been found that using a waferless automatic cleaning gas of only nitrogen results in polymer build up on confinement rings and the lower electrode area. The inventive waferless automatic cleaning process with a mixture of nitrogen and oxygen has been found to prevent process shift and polymer build up at both the top and lower electrode areas.
- While this invention has been described in terms of several preferred embodiments, there are alterations, permutations, modifications and various substitute equivalents, which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, modifications, and various substitute equivalents as fall within the true spirit and scope of the present invention.
Claims (10)
1. An apparatus for etching features in dielectric layers and opening barrier layers for a plurality of wafers, comprising:
an etch chamber;
an upper electrode with the etch chamber;
a lower electrode with the etch chamber;
an RF source electrically connected to at least one of the upper electrode and lower electrode;
a gas source in fluid connection with the etch chamber to provide gas into the etch chamber; and
a controller controllably connected to the RF source and the gas source comprising computer readable media, comprising:
computer readable code for etching the dielectric layer;
computer readable code for opening a barrier layer; and
computer readable code for providing a waferless automatic cleaning of the etch chamber after a wafer has been removed from the etch chamber to empty the etch chamber after the opening of a barrier layer, comprising:
computer readable code for providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber; and
computer readable code for forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.
2. The apparatus, as recited in claim 1 , wherein the computer readable code for providing the waferless automatic cleaning gas provides the waferless automatic cleaning gas with an oxygen to nitrogen flow ratio between 1:99 to 2:98.
3. The apparatus, as recited in claim 1 , wherein the computer code for providing the waferless automatically cleaning gas provides a waferless automatic cleaning gas consisting essentially of oxygen and nitrogen.
4. The apparatus, as recited in claim 1 , further comprising computer code for cleaning the etch chamber after processing and removing each wafer of the plurality of wafers.
5. The apparatus, as recited in claim 1 , wherein the barrier layer is selected from the group of SiN and SiC.
6. The apparatus, as recited in claim 1 , further comprising computer code for providing waferless automatic cleaning each time a wafer of the plurality of wafers is removed from the etch chamber to empty the etch chamber after the barrier layer opening.
7. The apparatus, as recited in claim 6 , wherein the waferless automatic cleaning is able to clean both the upper electrode and the lower electrode.
8. The apparatus, as recited in claim 1 , wherein the forming the waferless automatic cleaning plasma comprises providing more than 300 watts at a frequency between 12-50 MHz.
9. The apparatus, as recited in claim 1 , wherein the forming the waferless automatic cleaning plasma comprises maintaining a chamber pressure between 500-750 mTorr.
10. The apparatus, as recited in claim 1 , wherein the barrier layer is SiN.
Priority Applications (1)
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US11/672,129 US20070128849A1 (en) | 2004-04-19 | 2007-02-07 | Waferless automatic cleaning after barrier removal |
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US10/828,065 US7211518B2 (en) | 2004-04-19 | 2004-04-19 | Waferless automatic cleaning after barrier removal |
US11/672,129 US20070128849A1 (en) | 2004-04-19 | 2007-02-07 | Waferless automatic cleaning after barrier removal |
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US10/828,065 Division US7211518B2 (en) | 2004-04-19 | 2004-04-19 | Waferless automatic cleaning after barrier removal |
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US10/828,065 Expired - Fee Related US7211518B2 (en) | 2004-04-19 | 2004-04-19 | Waferless automatic cleaning after barrier removal |
US11/672,129 Abandoned US20070128849A1 (en) | 2004-04-19 | 2007-02-07 | Waferless automatic cleaning after barrier removal |
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---|---|
US (2) | US7211518B2 (en) |
KR (1) | KR101144020B1 (en) |
CN (1) | CN100472707C (en) |
TW (1) | TWI365479B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090114156A1 (en) * | 2007-10-11 | 2009-05-07 | Nobutake Nodera | Film formation apparatus for semiconductor process |
US20130001754A1 (en) * | 2007-05-24 | 2013-01-03 | Lam Research Corporation | In-situ photoresist strip during plasma etching of active hard mask |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US7578945B2 (en) * | 2004-09-27 | 2009-08-25 | Lam Research Corporation | Method and apparatus for tuning a set of plasma processing steps |
US20070243714A1 (en) * | 2006-04-18 | 2007-10-18 | Applied Materials, Inc. | Method of controlling silicon-containing polymer build up during etching by using a periodic cleaning step |
CN102136410B (en) * | 2010-01-27 | 2013-04-10 | 中芯国际集成电路制造(上海)有限公司 | Method for cleaning technological cavities of semiconductor |
CN103785646A (en) * | 2012-10-30 | 2014-05-14 | 中微半导体设备(上海)有限公司 | Reaction cavity cleaning method |
CN105742203B (en) * | 2014-12-10 | 2019-08-13 | 中微半导体设备(上海)股份有限公司 | A kind of device changing gas flow patterns and wafer processing method and equipment |
US20160172243A1 (en) * | 2014-12-11 | 2016-06-16 | Nxp B.V. | Wafer material removal |
JP7199279B2 (en) * | 2019-03-26 | 2023-01-05 | 東京エレクトロン株式会社 | Substrate processing apparatus and static elimination method for mounting table |
CN111118458B (en) * | 2019-12-04 | 2022-03-22 | 北京北方华创微电子装备有限公司 | Chamber cleaning method and apparatus |
TWI757013B (en) * | 2020-12-28 | 2022-03-01 | 友達光電股份有限公司 | Method for controlling consumption of cleaning gas in processing chamber and processing system |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6060397A (en) * | 1995-07-14 | 2000-05-09 | Applied Materials, Inc. | Gas chemistry for improved in-situ cleaning of residue for a CVD apparatus |
US20020052114A1 (en) * | 2000-03-30 | 2002-05-02 | Lam Research Corporation | Enhanced resist strip in a dielectric etcher using downstream plasma |
US20020117472A1 (en) * | 2001-02-23 | 2002-08-29 | Applied Materials, Inc. | Cleaning of multicompositional etchant residues |
US6559049B2 (en) * | 2001-08-08 | 2003-05-06 | Lam Research Corporation | All dual damascene oxide etch process steps in one confined plasma chamber |
US7125792B2 (en) * | 2003-10-14 | 2006-10-24 | Infineon Technologies Ag | Dual damascene structure and method |
-
2004
- 2004-04-19 US US10/828,065 patent/US7211518B2/en not_active Expired - Fee Related
-
2005
- 2005-04-18 TW TW094112311A patent/TWI365479B/en active
- 2005-04-18 CN CNB2005100762025A patent/CN100472707C/en active Active
- 2005-04-19 KR KR1020050032519A patent/KR101144020B1/en active IP Right Grant
-
2007
- 2007-02-07 US US11/672,129 patent/US20070128849A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6060397A (en) * | 1995-07-14 | 2000-05-09 | Applied Materials, Inc. | Gas chemistry for improved in-situ cleaning of residue for a CVD apparatus |
US20020052114A1 (en) * | 2000-03-30 | 2002-05-02 | Lam Research Corporation | Enhanced resist strip in a dielectric etcher using downstream plasma |
US20020117472A1 (en) * | 2001-02-23 | 2002-08-29 | Applied Materials, Inc. | Cleaning of multicompositional etchant residues |
US6559049B2 (en) * | 2001-08-08 | 2003-05-06 | Lam Research Corporation | All dual damascene oxide etch process steps in one confined plasma chamber |
US7125792B2 (en) * | 2003-10-14 | 2006-10-24 | Infineon Technologies Ag | Dual damascene structure and method |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130001754A1 (en) * | 2007-05-24 | 2013-01-03 | Lam Research Corporation | In-situ photoresist strip during plasma etching of active hard mask |
US8912633B2 (en) * | 2007-05-24 | 2014-12-16 | Lam Research Corporation | In-situ photoresist strip during plasma etching of active hard mask |
US20090114156A1 (en) * | 2007-10-11 | 2009-05-07 | Nobutake Nodera | Film formation apparatus for semiconductor process |
Also Published As
Publication number | Publication date |
---|---|
KR101144020B1 (en) | 2012-05-09 |
TW200539289A (en) | 2005-12-01 |
US7211518B2 (en) | 2007-05-01 |
CN1691276A (en) | 2005-11-02 |
TWI365479B (en) | 2012-06-01 |
US20050233590A1 (en) | 2005-10-20 |
CN100472707C (en) | 2009-03-25 |
KR20060047238A (en) | 2006-05-18 |
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