KR20070062041A - Method of manufacturing a flash memory device - Google Patents

Method of manufacturing a flash memory device Download PDF

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KR20070062041A
KR20070062041A KR1020050121710A KR20050121710A KR20070062041A KR 20070062041 A KR20070062041 A KR 20070062041A KR 1020050121710 A KR1020050121710 A KR 1020050121710A KR 20050121710 A KR20050121710 A KR 20050121710A KR 20070062041 A KR20070062041 A KR 20070062041A
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layer
hard mask
polysilicon
film
device isolation
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KR1020050121710A
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Korean (ko)
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이정웅
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for manufacturing a flash memory device is provided to lower effectively EFH(Effective Field Height) of an isolation layer without causing an attack to a floating gate. A tunnel oxide layer(102) and a first polysilicon layer(104) are formed on a semiconductor substrate(100). A trench is formed by etching partially the first polysilicon layer, the tunnel oxide layer, and the semiconductor substrate. An isolation layer(106) is formed within the trench. A second polysilicon layer(108), a hard mask nitride layer, and a head mask oxide layer are sequentially formed on the entire structure. The hard mask nitride layer and the hard mask oxide layer are patterned to expose an upper part of the second polysilicon layer. The second polysilicon layer and the isolation layer under the second polysilicon layer are etched by using the patterned hard mask oxide layer and the patterned hard mask nitride layer as etch masks.

Description

플래쉬 메모리 소자의 제조방법{Method of manufacturing a flash memory device}Method of manufacturing a flash memory device

도 1은 기존의 플래쉬 메모리 소자의 제조방법을 설명하기 위해 도시한 단면도이다.1 is a cross-sectional view illustrating a conventional method of manufacturing a flash memory device.

도 2a 내지 도 2e는 본 발명에 따른 플래쉬 메모리 소자의 제조방법을 설명하기 위해 도시한 단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

100 : 반도체 기판 102 : 터널 산화막100 semiconductor substrate 102 tunnel oxide film

104 : 제1 폴리실리콘막 106 : 소자 분리막104: first polysilicon film 106: device isolation film

108 : 제2 폴리실리콘막 110 : 하드마스크 질화막108: second polysilicon film 110: hard mask nitride film

112 : 하드마스크 산화막 114 : 포토레지스트 패턴112: hard mask oxide film 114: photoresist pattern

본 발명은 플래쉬 메모리 소자의 제조방법에 관한 것으로, 특히, SA-STI(Self Align-Shallow Trench Isolation) 스킴을 이용한 플래쉬 메모리 소자 제조시 소자분리막의 EFH(Effective Field Height)를 낮추기 위한 식각 공정시 플로팅 게이트가 어택을 받지 않도록 하면서 EFH를 효과적으로 낮추어 간섭 효과를 개선할 수 있는 플래쉬 메모리 소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to floating during an etching process to lower the effective field height (EFH) of an isolation layer when manufacturing a flash memory device using a SA-STI (Self Align-Shallow Trench Isolation) scheme. The present invention relates to a method of manufacturing a flash memory device capable of improving the interference effect by effectively lowering the EFH while preventing the gate from being attacked.

도 1은 SA-STI 스킴을 이용한 플래쉬 메모리 소자의 제조방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for describing a method of manufacturing a flash memory device using the SA-STI scheme.

도 1을 참조하면, 반도체 기판(10) 상에 터널 산화막(11), 플로팅 게이트용 제1 폴리실리콘막(12) 및 질화막(미도시)을 형성 한 후, 소정의 마스크를 이용한 사진 및 식각 공정으로 질화막, 제1 폴리실리콘막(12), 터널 산화막(11) 및 반도체 기판(10)의 일부를 식각하여 트렌치를 형성한다. 트렌치가 매립되도록 전체 구조 상부에 HDP 산화막을 형성한 후 질화막 상부가 노출될 때까지 HDP 산화막을 연마하여 소자 분리막(13)을 형성한다. 이후, 질화막을 제거한다. Referring to FIG. 1, after forming the tunnel oxide film 11, the first polysilicon film 12 for floating gate, and the nitride film (not shown) on the semiconductor substrate 10, a photo and etching process using a predetermined mask is performed. A portion of the nitride film, the first polysilicon film 12, the tunnel oxide film 11, and the semiconductor substrate 10 is etched to form a trench. An HDP oxide film is formed over the entire structure to fill the trench, and the device isolation film 13 is formed by polishing the HDP oxide film until the top of the nitride film is exposed. Thereafter, the nitride film is removed.

전체 구조 상부에 플로팅 게이트용 제2 폴리실리콘막(14)을 형성하고, 상기 소자분리막(13) 상부의 제2 폴리실리콘막(14)을 노출하는 포토레지스트(미도시)를 마스크로 상기 제 2 폴리실리콘막(14)을 식각하여 제1 폴리실리콘막(12)과 제2 폴리실리콘막(14)으로 구성된 플로팅 게이트를 형성한다. A second polysilicon film 14 for floating gate is formed on the entire structure, and the second photoresist (not shown) exposing the second polysilicon film 14 on the device isolation layer 13 is used as a mask. The polysilicon film 14 is etched to form a floating gate including the first polysilicon film 12 and the second polysilicon film 14.

반도체 소자의 고집적화에 따라 소자 분리막(13)의 폭이 줄어들게 되고, 이에 따라 서로 인접하는 제1 폴리실리콘막(12)의 간격이 줄어들게 되어 서로 인접하는 제1 폴리실리콘막(12)에 의한 기생 캐패시턴스가 증가 되며, 이로 인해 간섭 효 과가 증가 되고 있다. 또한, 기생 캐패시턴스의 증가로 인하여 프로그램시 동작 속도가 느려진다. As the semiconductor device is highly integrated, the width of the device isolation layer 13 is reduced, and thus, the distance between the first polysilicon films 12 adjacent to each other is reduced, thereby causing parasitic capacitance by the first polysilicon films 12 adjacent to each other. Is increased, which increases the interference effect. In addition, the increase in parasitic capacitance slows down the program operation.

이를 해결하기 위하여 제2 폴리실리콘막(14) 식각시 소자 분리막(13)이 제1 폴리실리콘막(12) 이하로 위치되도록 하기 위해 상기 제 2 폴리실리콘막(14) 식각 공정을 오버 에치(over etch)로 진행하여 하부의 소자분리막(13)을 50Å 내지 150Å 정도 식각하여 소자분리막(13)의 EFH를 낮춘다.In order to solve this problem, the etching process of the second polysilicon layer 14 is over-etched so that the device isolation layer 13 is positioned below the first polysilicon layer 12 when the second polysilicon layer 14 is etched. etch) to etch the lower device isolation layer 13 by about 50Å to 150Å to lower the EFH of the device isolation layer 13.

그러나, 상기 오버 에치 진행시 포토레지스트 마진이 부족하여 제2 폴리실리콘막(14) 상부가 어택(attack)을 받아 일부 손실된다(도 1의 A). However, due to the lack of photoresist margin during the over-etching process, the upper part of the second polysilicon layer 14 is attacked and partially lost (A in FIG. 1).

상기 제2 폴리실리콘막(14) 상부가 어택을 받아 일부 손실되는 것을 방지하기 위해서는 포토레지스트의 두께를 증가시키면 되나, 두꺼운 포토레지스트로는 미세 패터닝이 불가능하여 고집적 소자 제조에 어려움이 있다.In order to prevent the upper part of the second polysilicon layer 14 from being attacked, the thickness of the photoresist may be increased, but fine patterning is not possible with a thick photoresist, which makes it difficult to manufacture a highly integrated device.

상술한 문제점을 해결하기 위해 안출된 본 발명의 목적은 소자분리막의 EFH(Effective Field Height)를 낮추기 위한 식각 공정시 플로팅 게이트가 어택을 받지 않도록 하면서 EFH를 효과적으로 낮추어 간섭 효과를 개선할 수 있는 플래쉬 메모리 소자의 제조방법을 제공하는 데 있다.An object of the present invention devised to solve the above problems is a flash memory capable of improving the interference effect by effectively lowering the EFH while preventing the floating gate from being attacked during the etching process to lower the effective field height (EFH) of the device isolation layer. It is to provide a method for manufacturing a device.

본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조방법은, 반도체 기판상 에 터널 산화막 및 제1 폴리실리콘막을 형성한 후 상기 제1 폴리실리콘막, 터널 산화막 및 반도체 기판의 일부를 식각하여 트렌치를 형성하는 단계와, 상기 트렌치 내에 소자 분리막을 형성한 후 전체 구조상에 제2 폴리실리콘막, 하드마스크 질화막 및 하드마스크 산화막을 순차적으로 형성하는 단계와, 상기 소자 분리막 상의 상기 제2 폴리실리콘막 상부가 노출되도록 상기 하드 마스크 질화막 및 하드마스크 산화막을 패터닝하는 단계와, 상기 패터닝된 하드마스크 산화막과 하드마스크 질화막을 식각 마스크로 이용하여 상기 제2 폴리실리콘막과 그 하부의 상기 소자분리막을 식각하는 단계를 포함하는 플래쉬 메모리 소자의 제조방법을 제공한다.In the method of manufacturing a flash memory device according to an embodiment of the present invention, after forming a tunnel oxide film and a first polysilicon film on a semiconductor substrate, a trench is formed by etching a portion of the first polysilicon film, the tunnel oxide film and the semiconductor substrate. And forming a second polysilicon film, a hard mask nitride film, and a hard mask oxide film sequentially on the entire structure after forming the device isolation film in the trench, and exposing an upper portion of the second polysilicon film on the device isolation film. Patterning the hard mask nitride layer and the hard mask oxide layer to etch, and etching the second polysilicon layer and the device isolation layer thereunder using the patterned hard mask oxide layer and the hard mask nitride layer as etch masks. A method of manufacturing a flash memory device is provided.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조방법을 설명하기 위한 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

도 2a를 참조하면, 반도체 기판(100) 상에 터널 산화막(102), 플로팅 게이트용 제1 폴리실리콘막(104) 및 질화막(미도시)을 형성한 후, 소정의 마스크를 이용한 사진 및 식각 공정으로 질화막, 제1 폴리실리콘막(104), 터널 산화막(102) 및 반도체 기판(100)의 일부를 식각하여 트렌치를 형성한다. 이어, 상기 트렌치가 매립되도록 전체 구조상에 HDP 산화막을 형성한 후 질화막 상부가 노출될 때까지 HDP 산화막을 연마하여 소자 분리막(106)을 형성한다. Referring to FIG. 2A, after the tunnel oxide layer 102, the floating polysilicon layer 104 and the nitride layer (not shown) are formed on the semiconductor substrate 100, a photo-etching process using a predetermined mask is performed. A portion of the nitride film, the first polysilicon film 104, the tunnel oxide film 102, and the semiconductor substrate 100 is etched to form a trench. Subsequently, an HDP oxide film is formed on the entire structure to fill the trench, and the device isolation layer 106 is formed by polishing the HDP oxide film until the upper portion of the nitride film is exposed.

이후, 질화막을 제거한 후, 전체 구조 상부에 플로팅 게이트용 제2 폴리실리 콘막(108)을 형성한다. 이때, 제2 폴리실리콘막(108)은 700Å 내지 1200Å의 두께로 형성한다. Thereafter, after the nitride film is removed, the second polysilicon film 108 for floating gate is formed on the entire structure. In this case, the second polysilicon film 108 is formed to a thickness of 700 kPa to 1200 kPa.

제2 폴리실리콘막(108) 상에 하드마스크 질화막(110)을 형성한다. 이때, 하드마스크 질화막(110)은 PE-CVD(Plasma Enhanced Chemical Vapor Deposition) 방식을 이용하여 100Å 내지 200Å의 두께로 형성한다. The hard mask nitride film 110 is formed on the second polysilicon film 108. At this time, the hard mask nitride film 110 is formed to a thickness of 100 ~ 200Å by using a plasma enhanced chemical vapor deposition (PE-CVD) method.

하드마스크 질화막(110) 상에 하드마스크 산화막(112)을 형성하고, 상기 소자분리막(106) 상부의 하드마스크 산화막(112)를 노출하는 포토레지스트 패턴(114)을 형성한다. 이때, 하드마스크 산화막(112)은 PE-CVD 방식을 이용하여 100Å 내지 200Å의 두께로 형성한다. A hard mask oxide film 112 is formed on the hard mask nitride film 110, and a photoresist pattern 114 is formed to expose the hard mask oxide film 112 on the device isolation layer 106. At this time, the hard mask oxide film 112 is formed to a thickness of 100 ~ 200Å by PE-CVD method.

도 2b를 참조하면, 포토레지스트 패턴(114)을 식각 마스크로 하는 식각 공정으로 하드마스크 산화막(112) 및 하드마스크 질화막(110)을 패터닝한다. 이후, 세정 공정을 실시하여 포토레지스트 패턴(114)을 제거한다. Referring to FIG. 2B, the hard mask oxide layer 112 and the hard mask nitride layer 110 are patterned by an etching process using the photoresist pattern 114 as an etching mask. Thereafter, a cleaning process is performed to remove the photoresist pattern 114.

도 2c를 참조하면, 패터닝된 하드마스크 산화막(112)을 식각 마스크로 이용하여 제2 폴리실리콘막(108)을 식각한다. 이때, 제2 폴리실리콘막(108) 식각 공정시 HBr 가스 또는 HBr 및 O2를 혼합한 혼합 가스를 이용하여 제2 폴리실리콘막(108)과 하드마스크 산화막(112)의 식각 선택비가 10:1 내지 50:1이 되게 한다. 제2 폴리실리콘막(108) 식각 공정시 하드마스크 질화막(110) 상에 형성된 하드마스크 산화막(112)은 완전히 제거되게 된다.Referring to FIG. 2C, the second polysilicon layer 108 is etched using the patterned hard mask oxide layer 112 as an etching mask. In this case, the etching selectivity of the second polysilicon layer 108 and the hard mask oxide layer 112 is 10: 1 by using HBr gas or a mixed gas of HBr and O 2 during the etching process of the second polysilicon layer 108. To 50: 1. During the etching process of the second polysilicon layer 108, the hard mask oxide layer 112 formed on the hard mask nitride layer 110 is completely removed.

도 2d를 참조하면, 패터닝된 하드마스크 질화막(110)을 식각 마스크로 이용 하여 상기 소자분리막(106)의 EFH를 낮추기 위하여 소자 분리막(106)을 식각한다. 이때, C5F8 또는 CH2F2 가스를 이용하여 소자 분리막(106)과 하드마스크 질화막(110)의 식각 선택비가 10:1 내지 50:1이 되게 한다. 소자 분리막(104) 식각 공정을 실시한 후 제2 폴리실리콘막(108)상에 하드마스크 질화막(110)이 일부 잔류하게 된다. 이때, 잔류하는 하드마스크 질화막(110)의 두께는 50Å 내지 150Å이 되도록 한다.Referring to FIG. 2D, the device isolation layer 106 is etched to lower the EFH of the device isolation layer 106 by using the patterned hard mask nitride layer 110 as an etching mask. In this case, the etching selectivity of the device isolation layer 106 and the hard mask nitride layer 110 may be 10: 1 to 50: 1 using C 5 F 8 or CH 2 F 2 gas. After the etching process of the device isolation layer 104, the hard mask nitride layer 110 remains partially on the second polysilicon layer 108. At this time, the thickness of the remaining hard mask nitride film 110 is 50 kPa to 150 kPa.

도 2e를 참조하면, 제2 폴리실리콘막(108) 상에 잔류하는 하드마스크 질화막(110)을 습식 식각하여 제거한다. 이때, 잔류하는 하드마스크 질화막 패턴(110)은 150℃ 내지 250℃의 온도에서 H3PO4 용액을 이용하여 제거한다.Referring to FIG. 2E, the hard mask nitride layer 110 remaining on the second polysilicon layer 108 is wet-etched and removed. At this time, the remaining hard mask nitride film pattern 110 is removed using a H 3 PO 4 solution at a temperature of 150 ℃ to 250 ℃.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주지하여야 한다. 또한, 본 발명의 기술 분야에서 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이 본 발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.

첫째, 폴리실리콘막과의 식각 선택비가 우수한 하드마스크 산화막과 소자분리막과 식각 선택비가 우수한 하드마스크 질화막을 마스크로 하여 플로팅 게이트용 폴리실리콘막 식각 공정 및 소자분리막의 EFH를 낮추기 위한 소자분리막 식각 공정을 실시하므로 플로팅 게이트용 폴리실리콘막 상부가 어택을 받지 않으면서 소자 분리막의 EFH를 효과적으로 낮추어 간섭 효과를 개선할 수 있다.First, the polysilicon film etching process for floating gate and the device isolation film etching process for lowering the EFH of the device isolation film are used as a mask using a hard mask oxide film having excellent etching selectivity with a polysilicon film, a device isolation film and a hardmask nitride film having an excellent etching selectivity. Therefore, the interference effect can be improved by effectively lowering the EFH of the device isolation layer without the attack of the upper portion of the polysilicon layer for the floating gate.

둘째, 간섭 효과를 개선시킬 수 있으므로 프로그램시 동작 속도를 향상시킬 수 있다.Second, since the interference effect can be improved, the operation speed during programming can be improved.

Claims (13)

반도체 기판상에 터널 산화막 및 제1 폴리실리콘막을 형성한 후 상기 제1 폴리실리콘막, 터널 산화막 및 반도체 기판의 일부를 식각하여 트렌치를 형성하는 단계;Forming a tunnel oxide film and a first polysilicon film on a semiconductor substrate, and then etching a portion of the first polysilicon film, the tunnel oxide film and the semiconductor substrate to form a trench; 상기 트렌치 내에 소자 분리막을 형성한 후 전체 구조상에 제2 폴리실리콘막, 하드마스크 질화막 및 하드마스크 산화막을 순차적으로 형성하는 단계;Forming a second polysilicon film, a hard mask nitride film, and a hard mask oxide film sequentially on the entire structure after the device isolation film is formed in the trench; 상기 소자 분리막 상의 상기 제2 폴리실리콘막 상부가 노출되도록 상기 하드 마스크 질화막 및 하드마스크 산화막을 패터닝하는 단계; 및Patterning the hard mask nitride layer and the hard mask oxide layer to expose an upper portion of the second polysilicon layer on the device isolation layer; And 상기 패터닝된 하드마스크 산화막과 하드마스크 질화막을 식각 마스크로 이용하여 상기 제2 폴리실리콘막과 그 하부의 상기 소자분리막을 식각하는 단계를 포함하는 플래쉬 메모리 소자의 제조방법.And etching the second polysilicon layer and the device isolation layer thereunder using the patterned hard mask oxide layer and the hard mask nitride layer as etching masks. 제1항에 있어서, 상기 제2 폴리실리콘막을 700Å 내지 1200Å의 두께로 형성하는 플래쉬 메모리 소자의 제조방법.The method of claim 1, wherein the second polysilicon layer is formed to have a thickness of 700 GPa to 1200 GPa. 제1항에 있어서, 상기 하드마스크 질화막은 PE-CVD 방식을 이용하여 100Å 내지 200Å의 두께로 형성하는 플래쉬 메모리 소자의 제조방법.The method of claim 1, wherein the hard mask nitride layer is formed to have a thickness of 100 μs to 200 μs using a PE-CVD method. 제1항에 있어서, 상기 하드마스크 산화막은 PE-CVD 방식을 이용하여 100Å 내지 200Å의 두께로 형성하는 플래쉬 메모리 소자의 제조방법.The method of claim 1, wherein the hard mask oxide layer is formed to have a thickness of 100 μs to 200 μs using a PE-CVD method. 제1항에 있어서, 상기 제2 폴리실리콘막 식각 공정시 상기 제2 폴리실리콘막과 상기 하드마스크 산화막의 식각 선택비가 10:1 내지 50:1이 되도록 설정하는 플래쉬 메모리 소자의 제조방법.The method of claim 1, wherein the etching selectivity of the second polysilicon layer and the hard mask oxide layer is set to be 10: 1 to 50: 1 during the second polysilicon layer etching process. 제5항에 있어서, 상기 제2 폴리실리콘막 식각 공정시 HBr 가스 또는 HBr 및 O2를 혼합한 혼합 가스를 이용하는 플래쉬 메모리 소자의 제조방법.The method of claim 5, wherein HBr gas or a mixed gas of HBr and O 2 is used in the second polysilicon film etching process. 제1항에 있어서, 상기 제2 폴리실리콘막 식각 공정시 상기 패터닝된 하드마스크 산화막은 완전히 제거되는 플래쉬 메모리 소자의 제조방법.The method of claim 1, wherein the patterned hard mask oxide layer is completely removed during the second polysilicon layer etching process. 제1항에 있어서, 상기 소자 분리막 식각 공정시 상기 소자 분리막과 상기 하 드마스크 질화막의 식각 선택비가 10:1 내지 50:1이 되게 설정하는 플래쉬 메모리 소자의 제조방법.The method of claim 1, wherein the etching selectivity of the device isolation layer and the hard mask nitride layer is set to be 10: 1 to 50: 1 during the device isolation process. 제8항에 있어서, 상기 소자 분리막 식각 공정시 C5F8 또는 CH2F2 가스를 이용하는 플래쉬 메모리 소자의 제조방법.The method of claim 8, wherein C 5 F 8 or CH 2 F 2 gas is used in the device isolation process. 제1항에 있어서, 상기 소자 분리막 식각 공정 이후, 상기 제2 폴리실리콘막 상부에 잔류하는 상기 패터닝된 하드마스크 질화막을 50Å 내지 150Å의 두께가 되도록 하는 플래쉬 메모리 소자의 제조방법.The method of claim 1, wherein the patterned hardmask nitride layer remaining on the second polysilicon layer after the device isolation layer etching process has a thickness of about 50 μs to about 150 μs. 제1항에 있어서, 상기 소자 분리막 식각 공정 이후, 상기 제2 폴리실리콘막 상에 잔류하는 상기 패터닝된 하드마스크 질화막을 제거하는 단계를 더 포함하는 플래쉬 메모리 소자의 제조방법.The method of claim 1, further comprising removing the patterned hard mask nitride layer remaining on the second polysilicon layer after the device isolation layer etching process. 제11항에 있어서, 잔류하는 상기 패터닝된 하드 마스크 질화막을 150℃ 내지 250℃의 온도에서 H3PO4 용액을 이용하여 제거하는 플래쉬 메모리 소자의 제조방법.The method of claim 11, wherein the remaining patterned hard mask nitride layer is removed using a H 3 PO 4 solution at a temperature of 150 ° C. to 250 ° C. 13. 제 1항에 있어서,상기 소자분리막 식각 공정을 상기 소자분리막이 상기 제 1 폴리실리콘막 이하가 되도록 실시하는 플래쉬 메모리 소자의 제조방법.The method of claim 1, wherein the device isolation layer etching process is performed so that the device isolation layer is less than or equal to the first polysilicon layer.
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