KR20070002646A - Method for forming semiconductor device - Google Patents

Abstract

A method for forming a semiconductor device is provided to prevent asymmetry and deviation of cell threshold voltage of a gate by previously forming a buffer layer before forming a recess gate region. A buffer layer(135) is formed on a substrate(100) having an active and an isolation regions. A photoresist pattern is formed on the buffer layer to expose a recess gate forming region. A recess gate region(140) is formed by etching the buffer layer and the substrate using the photoresist pattern as a mask. After the photoresist pattern is removed, a gate oxide layer(150) is formed on the recess gate region and the buffer layer. A polysilicon layer(160) is filled in the recess gate region. A metal film(170) and a hard mask(180) are formed on the polysilicon layer and patterned, thereby forming a recess gate(190).

Description

Method of forming a semiconductor device {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

2A to 2H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and in particular, in forming a recess gate to increase the channel length of the gate, a polysilicon layer buried in the recess gate region due to misalignment of the gate and the recess gate region is lost. In order to solve the problem of lowering the electrical characteristics of the semiconductor device, a buffer layer is formed in advance before the recess gate region is formed to induce the loss of the polysilicon layer only on the semiconductor substrate, thereby asymmetrical and fluctuation of the cell threshold voltage of the gate. The present invention relates to a method of forming a semiconductor device that can solve a problem or a problem of lowering refresh characteristics.

As the semiconductor devices are highly integrated, the line width of the gate is narrowed, and thus, the electrical characteristics of the semiconductor devices are deteriorated due to the decrease in the channel length. In particular, this problem is greatly affected in the sub-nm process, and recess gates are used to overcome this problem. The recess gate is a technique capable of increasing the gate channel length by etching the active region semiconductor substrate, which is the channel region of the gate predetermined region, by increasing the contact area between the gate and the active region and the gate.

1A to 1E are cross-sectional views illustrating a method of forming a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer 30 defining an active region 20 is formed on a semiconductor substrate 10.

Referring to FIG. 1B, a photoresist pattern (not shown) for exposing a recess gate predetermined region is formed on the semiconductor substrate 10, and the active region 20 of the semiconductor substrate 10 is defined by using the photoresist pattern as an etch mask. The depth is etched to form the recess gate region 40.

Referring to FIG. 1C, the polysilicon layer 60 may be formed to remove the photoresist pattern, form the gate oxide layer 50 on the recess gate region 40 and the surface of the semiconductor substrate 10, and fill the recess gate region 40. ). Next, the metal layer 70 and the hard mask layer 80 are sequentially formed on the polysilicon layer 60.

Referring to FIG. 1D, the hard mask layer 80, the metal layer 70, the polysilicon layer 60, and the gate oxide layer 50 are patterned to form a gate 90. Here, the polysilicon layer 60 is lost due to a misalignment between the mask (not shown) patterning the gate 90 and the recess gate region 40.

FIG. 1E is an enlarged view of a portion ⓐ where the loss of the polysilicon layer 60 occurs in the step of FIG. 1D. As shown in FIG. 1E, the loss of the polysilicon layer 60 causes the channel region of the gate 90 to be formed. Occurred in part. This causes the channel threshold voltages left and right of the cell transistors formed by the gate 90 and the source / drain regions (not shown) to be asymmetric with each other, cause variations, and reduce the refresh characteristics of the transistors.

In addition, when the line width of the gate 90 is larger than the width of the recess gate region 40, the problem due to the misalignment does not occur, but the top of the recess gate region 40 and the gate 90 and the semiconductor substrate ( 10) There is a problem in that a strong electric field is generated in the area where the surface is in contact with each other to reduce the electrical characteristics of the semiconductor device.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and forms a buffer layer before forming the recess gate region to induce the loss of the polysilicon layer to occur only on the semiconductor substrate, thereby causing asymmetry and fluctuation of the cell threshold voltage of the gate. It is an object of the present invention to provide a method of forming a semiconductor device capable of solving the problem or the problem of lowering the refresh characteristics, increasing the production yield of the highly integrated semiconductor device, and improving the characteristics of the semiconductor device.

In order to achieve the above object, a method of forming a semiconductor device according to the present invention,

Forming a buffer layer on a semiconductor substrate having an active region and an isolation region;

Forming a photoresist pattern on the buffer layer to expose a recess gate predetermined region;

Etching the buffer layer and the semiconductor substrate using the photoresist pattern as an etch mask to form a recess gate region;

Removing the photoresist pattern and forming a gate oxide layer on a surface of the recess gate region and the buffer layer;

Forming a polysilicon layer filling the recess gate region;

Forming a metal layer and a hard mask layer on the polysilicon layer;

Patterning the hard mask layer, the metal layer, and the polysilicon layer to form a gate.

Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, a pad oxide layer (not shown) and a pad nitride layer (not shown) are sequentially formed on an entire surface of a semiconductor substrate 100, and a device isolation region is formed by using a device isolation mask defining an active region 120. A trench (not shown) is formed in the trench.

Next, an oxide film filling the trench is formed on the entire surface, and the device isolation film 130 is separated by performing a CMP process. At this time, it is preferable to remove both the pad oxide film and the nitride film.

Referring to FIG. 2B, a buffer layer 135 is formed on the entire surface of the semiconductor substrate 100. In this case, the buffer layer 135 serves to prevent the polysilicon layer of the recess gate region from being lost in a subsequent gate forming process. The buffer layer 135 may be formed of a single insulating layer or a double insulating layer.

Referring to FIG. 2C, a photoresist pattern (not shown) is formed on the buffer layer 135 to expose a predetermined region of the recess gate, and the photoresist pattern is etched using an etch mask to form an active region of the buffer layer 135 and the semiconductor substrate 100. The 120 is etched to form the recess gate region 140.

Referring to FIG. 2D, the polysilicon layer 160 may be formed by removing the photoresist pattern, forming a gate oxide layer 150 on the recess gate region 140 and the buffer layer 135, and filling the recess gate region 140. To form.

Referring to FIG. 2E, the polysilicon layer 160 buried in the recess gate region 140 is insulated. In this case, the insulating of the polysilicon layer 160 may be performed using any one selected from a CMP process and an etch back process, so that the buffer layer 140 remains a predetermined thickness.

Referring to FIG. 2F, the metal layer 170 and the hard mask layer 180 are formed on the polysilicon layer 160.

Referring to FIG. 2G, the hard mask layer 180, the metal layer 170, and the polysilicon layer 160 are patterned to form the gate 190. Here, the problem that the polysilicon layer 160 is lost due to a misalignment between the mask (not shown) patterning the gate 190 and the recess gate region 140 may be alleviated.

FIG. 2H is an enlarged view of a portion ⓑ in which the loss of the polysilicon layer 160 occurs in the step of FIG. 2G. As shown in FIG. 2H, the loss of the polysilicon layer 160 occurs only in the buffer layer 135. . That is, a problem occurs in the upper portion of the semiconductor substrate 100, which does not directly damage the channel region of the gate 160. Therefore, it is possible to prevent the electrical characteristics of the semiconductor device from decreasing.

As described above, in the method of forming a semiconductor device according to the present invention, a problem of asymmetry and fluctuation of cell threshold voltage or a problem of reducing refresh characteristics caused by misalignment by forming a buffer layer on a semiconductor substrate before forming a recess gate region is described. Can be prevented. In addition, when the gate width of the gate is thicker than that of the recess gate region, a strong electric field may be prevented from occurring at a portion where the gate of the recess gate region and the semiconductor substrate meet each other. In addition, since the method of forming a semiconductor device can apply conventional equipment and processes as it is, it can secure stable production competitiveness and increase the production yield that can form a highly integrated semiconductor device without investing in new equipment and process technology. It provides the effect.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (2)

Forming a buffer layer on a semiconductor substrate having an active region and an isolation region; Forming a photoresist pattern on the buffer layer to expose a recess gate predetermined region; Etching the buffer layer and the semiconductor substrate using the photoresist pattern as an etch mask to form a recess gate region; Removing the photoresist pattern and forming a gate oxide layer on a surface of the recess gate region and the buffer layer; Forming a polysilicon layer filling the recess gate region; Forming a metal layer and a hard mask layer on the polysilicon layer; And And forming a gate by patterning the hard mask layer, the metal layer, and the polysilicon layer. The method of claim 1, And the buffer layer is a single insulating layer or a double insulating layer.

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