KR20060135126A - Method of forming pattern of a semiconductor device - Google Patents

Abstract

A method for forming a pattern in a semiconductor device is provided to form a pattern of a micro pattern by repeating a series of deposition and etching processes. A first sacrificial layer is formed on a substrate, and then is patterned to form a line type sacrificial pattern on the substrate. A spacer film is deposited along a profile of an upper portion of the sacrificial pattern in a uniform thickness. The spacer film is partially removed to expose the substrate and thus form spacer having a first line width on sidewalls of the sacrificial pattern and a second pattern(112) having a second line width wider than the first line width. A second sacrificial film is formed to sufficiently bury the spacers and the second pattern. The spacers and the second pattern are subjected to a planarization process to form first pattern(116).

Description

Method of forming pattern of a semiconductor device

1 to 7 are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100 semiconductor substrate 102 first sacrificial film

104: sacrificial pattern 106: spacer film

108: photoresist pattern 110: spacer

112: second pattern 114: second sacrificial film

116: first pattern

The present invention relates to a method of forming a pattern of a semiconductor device. More specifically, the present invention relates to a method of forming a pattern of a semiconductor device, which is advantageous in high integration of a device by forming a pattern having a fine line width through a series of deposition and etching processes.

In general, in the manufacturing process of a semiconductor device, a photolithography process transfers a pattern of a main mask to a photoresist film applied on a semiconductor substrate through an insulating film or a metal film, and then patternes and removes the photoresist film to remove the semiconductor. The process of forming a work mask on a substrate.

According to a conventional photolithography process, a photoresist film is formed on a target layer on which a pattern is to be formed, such as an insulating film, a conductive film, or the like on a semiconductor substrate, and the photoresist film is irradiated with light such as X-rays or ultraviolet rays, thereby Different solubility is imparted to the set and unset areas of the resist film. Next, a photoresist pattern is formed by removing a portion having high solubility, and active regions, wirings, contact holes, and the like are formed in the target layer using the formed photoresist pattern as a mask. The target layer pattern for forming is formed.

Photolithography technology has made great strides since mass production of semiconductor products based on DRAM (Dynamic Random Access Memory) began. Typically, the density of DRAM has quadrupled every three years, and other memory or logic technologies are steadily advancing. As a result, a non-photolithographic etching technique is being developed through a design rule (minimum pattern size) of a product from about 0.8 μm of 4Mb DRAM to about 0.18 μm of 1Gb DRAM.

However, even in the case of combining several technologies to increase the resolution in the photolithography process, it is not easy to implement a fine pattern of 0.1 μm or less, and various techniques such as the development of a new light source have been attempted.

A simple method of overcoming the limitations of current critical dimensions to form finer patterns would be the introduction of new equipment.

However, the introduction of new equipment has a problem that increases the production cost, there is a problem that must be changed to a new process according to the introduction of new equipment.

Without the introduction of such new equipment, there are thermal flow processes and chemical attached processes (CAP) to overcome the resolution limitations of current photolithography equipment.

The thermal flow process is a technique of reducing the line width of a pattern by sequentially forming an oxide film and a photoresist pattern on a semiconductor substrate, and heat treating the photoresist pattern to impart fluidity to the photoresist pattern. The thermal flow process may appropriately reduce the critical dimension of the pattern by adjusting the process temperature and time according to the characteristics of the photoresist constituting the photoresist pattern.

However, since the method of the thermal flow process is essentially dependent on the resolution of the photolithography equipment, it cannot be expected to overcome a certain resolution limit.

In addition, performing the thermal flow process at excessively high temperatures may degrade the uniformity of the photoresist pattern. That is, as the temperature increases, the fluidity of the photoresist increases, and at a high temperature above the glass transition temperature, the fluid flows almost close to the liquid, and may block a fine pattern such as a contact hole.

Specifically, the photoresist may change its properties rapidly in a high temperature environment, which means that the thermal flow process at a high temperature changes significantly sensitive to temperature changes. In addition, since the pattern line width can be remarkably changed even at a very small temperature change, there is a problem that it is difficult to control the line width according to the temperature change.

Another method for overcoming the resolution limitation of photolithography equipment is a chemical attached process (CAP), and Korean Patent Application Publication No. 2000-001567 and Korean Patent Application Publication No. 2000-009374 are disclosed. It is.

In the chemical adhesion process, a curable material such as a water-soluble polymer is applied to a photoresist pattern formed on a semiconductor substrate, and both materials react with each other at an interface between the applied curable material and the photoresist pattern to form a cured layer. By attaching the cured layer to the interface of the pattern, the photoresist pattern can obtain the effect of reducing the line width by a predetermined amount.

The chemical adhesion process is less affected by the resolution limit of the equipment than the thermal flow process, and the amount of adhesion is stable according to the photoresist and the water-soluble polymer applied thereon, so that the current equipment is currently maintained without introducing new equipment. It is usefully used to overcome the resolution limitation of.

However, the chemical adhesion process also has a limit to attach a hardened layer, if the hardened layer is attached more than a certain limit rather than the process may be unstable, may not be applicable to the actual product production. In addition, since the chemical adhesion process depends on the shape of the pattern, the density of the pattern, etc., there is a limit of conditions that can be applied stably.

The conventional methods as described above have a problem that the process is complicated and the process reproducibility is difficult to apply to the mass production stage of the actual production process of the high integration device.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to repeat a series of photolithography processes and, due to the limitations of photolithography equipment, a semiconductor device capable of forming a pattern having a fine line width that cannot be formed, stably and reproducibly. It is to provide a method of forming a pattern.

According to an aspect of the present invention for achieving the above object, the step of forming a first sacrificial film on the substrate and patterning the first sacrificial film to form a sacrificial pattern in the form of a line on the substrate and the top of the sacrificial pattern Depositing a spacer film with a uniform thickness along a profile of, and partially removing the spacer film to expose the substrate to form spacers having a first line width on sidewalls of the sacrificial pattern, wherein the spacers have a first line width that is wider than the first line width. Forming a second pattern having a second line width, forming a second sacrificial layer to sufficiently fill the spacers and the second pattern, and performing a planarization process to expose the spacers and the second pattern. It provides a pattern forming method of a semiconductor device comprising the step of forming the first pattern from the.

According to an embodiment of the present invention, an etch stop layer is formed on the substrate, and the removing of the spacer layer is performed through anisotropic etching using the etch stop layer.

The spacers and the second pattern may form a photoresist pattern having the second line width on a spacer layer in a region adjacent to the sacrificial pattern, and the surface of the sacrificial pattern using the second photoresist pattern as an etching mask. The spacer layer may be formed by partially removing the spacer layer to expose the spacer layer.

The method may further include removing a portion of the substrate except for the first pattern and the second pattern to expose the substrate.

The pattern formation method of the semiconductor element which concerns on this invention comprised in this way can form the pattern of the semiconductor element which has a fine line width with high stability and reproducibility.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 are cross-sectional views illustrating a method of forming a pattern of a semiconductor device according to an embodiment of the present invention.

1 and 2, the first sacrificial layer 102 is formed on the semiconductor substrate 100. Subsequently, the first sacrificial layer 102 is patterned to form a sacrificial pattern 104 having a line shape on the semiconductor substrate 100. The sacrificial pattern 104 is formed in a region where the first pattern 116 to be described later is defined.

In addition, the first sacrificial pattern 104 may be formed through a conventional etching process, or may be formed through a photo process.

In this case, the line width of the sacrificial pattern 104 defines an interval between the first patterns 116. That is, when a plurality of first patterns 116 are formed, the first patterns 116 are formed at an interval equal to the line width of the sacrificial pattern 104.

Referring to FIG. 3, a spacer layer 106 is deposited to have a uniform thickness along a profile on the sacrificial pattern 104. In this case, the thickness of the spacer layer 106 defines the line width of the first pattern 116.

Therefore, in order to form the first pattern 116 finely, the spacer layer 106 may be formed thin.

In addition, in order to minimize the line width variation of the first pattern 116, the spacer layer 106 may be formed using a method capable of precisely adjusting the thickness thereof.

To this end, the spacer layer 106 may be formed by atomic layer deposition (ALD), but may be formed using conventional chemical vapor deposition.

In this case, the atomic layer deposition technique may accurately adjust the thickness of the spacer film 106 to a range of several to several tens of microseconds.

In addition, the spacer layer 106 is a material forming the first pattern 116 and the second pattern 112 to be described later, and has an etching selectivity difference from the sacrificial pattern 104.

Referring to FIG. 4, the photoresist pattern 108 is formed on the spacer layer 106. In this case, the photoresist pattern 108 defines the line width of the second pattern 112. That is, the photoresist pattern 108 having the second line width is formed on the spacer layer 106 in the region adjacent to the sacrificial pattern 104.

Referring to FIG. 5, the spacer layer 106 is partially removed to expose the semiconductor substrate 100, thereby forming spacers 110 having a first line width on sidewalls of the sacrificial pattern 104. The second pattern 112 is formed.

In this case, an etch stop layer (not shown) is formed on the semiconductor substrate 100, and the removing of the spacer layer 106 is performed through anisotropic etching using the etch stop layer.

In detail, the spacer layer 106 is partially etched to expose the surface of the sacrificial pattern 104 by using the photoresist pattern 108 as an etching mask, and the photoresist pattern 108 is removed to remove the spacers. The process of forming the 110 and the second pattern 112 is performed.

Referring to FIG. 6, a second sacrificial layer 114 is formed on the entire surface of the structure such that both the spacers 110 and the second patterns 112 are embedded.

Referring to FIG. 7, the planarization process is performed to form the first pattern 116. Subsequently, portions except the first pattern 116 and the second pattern 112 are removed so that the semiconductor substrate 100 is exposed, and finally, the first pattern 116 and the second pattern 112 having a desired line width. ).

In this case, the planarization process may be performed using chemical mechanical polishing (CMP) or etch back technology.

Alternatively, before forming the first sacrificial layer 102, a step of forming a lower layer (not shown) on the semiconductor substrate 100 may be further performed. In this case, the lower layer may be a conductive layer, and the conductive layer may be used as a conductive layer for a gate pattern or a wiring.

In this case, after forming the first pattern 116 formed from the spacer 110, the sacrificial layer pattern 104 using an etching recipe having an etch selectivity with respect to the first pattern 116 and the lower layer. ). Subsequently, a gate pattern (not shown) or a wiring (not shown) may be formed by patterning the lower layer using the first pattern 116 as an etching mask.

Meanwhile, the first pattern 116 may be used as an etching mask for forming trenches. In more detail, after the first pattern 116 is formed, the sacrificial pattern 104 is removed, and the semiconductor substrate 100 is etched using the spacer 110 as an etching mask. A trench (not shown) is formed in 100.

In addition, in the removing of the sacrificial pattern 104, an etch recipe having an etch selectivity with respect to the first pattern 116 may be used.

In this case, the sacrificial pattern 104 and the spacers 110 may be formed of a silicon oxide film and a silicon nitride film, respectively.

According to the present invention as described above, by repeating a series of deposition and etching process, it is possible to form a pattern having a fine line width. This makes it possible to form a pattern having a size below the limit capability of the photolithography process stably and with excellent reproducibility.

As a result, it is advantageous to the high integration of the semiconductor element as described above, and the operation characteristics of the semiconductor device can be greatly improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (4)

Forming a first sacrificial film on the substrate; Patterning the first sacrificial layer to form a sacrificial pattern in a line shape on the substrate; Depositing a spacer layer with a uniform thickness along a profile over the sacrificial pattern; Partially removing the spacer layer to expose the substrate to form spacers having a first line width on sidewalls of the sacrificial pattern, and forming a second pattern having a second line width wider than the first line width; Forming a second sacrificial layer to sufficiently fill the spacers and the second pattern; And Forming a first pattern from the spacers by performing a planarization process to expose the spacers and the second pattern. The method of claim 1, wherein an etch stop layer is formed on the substrate, and the removing of the spacer layer is performed through anisotropic etching using the etch stop layer. The method of claim 1, wherein the forming of the spacers and the second pattern comprises: Forming a photoresist pattern having the second line width on a spacer layer in a region adjacent to the sacrificial pattern; And forming the spacers and the second pattern by partially removing the spacer layer so that the surface of the sacrificial pattern is exposed using the second photoresist pattern as an etching mask. Way. The method of claim 1, further comprising removing the substrate except for the first pattern and the second pattern to expose the substrate.

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