KR20090067369A - Method for forming a micro pattern in semiconductor device - Google Patents

Method for forming a micro pattern in semiconductor device Download PDF

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Publication number
KR20090067369A
KR20090067369A KR1020070135008A KR20070135008A KR20090067369A KR 20090067369 A KR20090067369 A KR 20090067369A KR 1020070135008 A KR1020070135008 A KR 1020070135008A KR 20070135008 A KR20070135008 A KR 20070135008A KR 20090067369 A KR20090067369 A KR 20090067369A
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KR
South Korea
Prior art keywords
hard mask
pattern
mask pattern
forming
semiconductor device
Prior art date
Application number
KR1020070135008A
Other languages
Korean (ko)
Inventor
김태형
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070135008A priority Critical patent/KR20090067369A/en
Publication of KR20090067369A publication Critical patent/KR20090067369A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a method for forming a micropattern of a semiconductor device having a line width of 40 nm or less. The method for forming a micropattern of a semiconductor device according to the present invention includes forming a first hard mask film on an etching target layer; Forming a second hard mask pattern on the first hard mask layer; Forming a third hard mask pattern to fill the second hard mask patterns; Removing the second hard mask pattern; And etching the first hard mask layer using the third hard mask pattern as an etch barrier to form a first hard mask pattern, and etching the etch target layer using the first hard mask pattern as an etch barrier. Through this, the present invention has the effect of realizing a fine pattern having a line width of less than 40nm using a commercialized photolithography equipment.

Description

METHOD FOR FORMING A MICRO PATTERN IN SEMICONDUCTOR DEVICE}

The present invention relates to a manufacturing technology of a semiconductor device, and more particularly to a method of forming a fine pattern of a semiconductor device.

As semiconductor devices are highly integrated, pattern intervals and pattern widths are narrowing to form more patterns on semiconductor substrates. In particular, as the design rule of the semiconductor device is reduced to 100 nm or less, the space in which the pattern can be formed becomes more narrow.

1 is a cross-sectional view showing a pattern of a semiconductor device according to the prior art.

Referring to FIG. 1, a method of forming a pattern of a semiconductor device according to the related art is described. After forming a hard mask film on an etching target layer 11, a photoresist pattern Photo Resist 13 is formed on the hard mask film. In this case, the hard mask layer is formed of an amorphous carbon layer (ACL).

Next, after forming the hard mask pattern 12 by etching the hard mask layer using the photoresist pattern 13 as an etch barrier, the hard mask pattern 12 is etched using the etch barrier, although not shown in the drawing. The target layer 11 is etched to form a desired pattern.

Currently, when the design rule of a semiconductor device is 100 nm or less, since the resolution of the KrF exposure source having a wavelength of 248 nm is limited, the photoresist pattern described above using a photolithography apparatus using an ArF exposure source having a wavelength of 193 nm is used. (13) is formed.

However, the limit of the critical dimension (CD) of the photoresist pattern 13 which can be implemented by a photolithography apparatus using an ArF exposure source is about 40 nm and forms the photoresist pattern 13 having a threshold dimension of less than that. Is very difficult. Therefore, in order to form a fine pattern having a critical dimension of 40 nm or less, a new method of forming a fine pattern of a semiconductor device is required.

The present invention has been proposed to solve the above problems of the prior art, and provides a method for forming a micropattern of a semiconductor device capable of realizing a micropattern having a critical dimension of 40 nm or less using photolithography equipment currently commercialized. There is a purpose.

According to an aspect of the present invention, there is provided a method of forming a fine pattern of a semiconductor device, the method comprising: forming a first hard mask layer on an etching target layer; Forming a second hard mask pattern on the first hard mask layer; Forming a third hard mask pattern to fill the second hard mask patterns; Removing the second hard mask pattern; And etching the first hard mask layer using the third hard mask pattern as an etch barrier to form a first hard mask pattern, and etching the etch target layer using the first hard mask pattern as an etch barrier.

The first, second and third hard mask patterns may be formed of materials having different selectivity. For example, the first hard mask pattern may be an amorphous carbon film, and the second hard mask pattern may be an oxide film. The third hard mask pattern may be formed of a polysilicon film.

The forming of the third hard mask pattern may include forming an insulating film for a third hard mask pattern on the entire surface of the resultant including the second hard mask pattern and exposing an upper surface of the second hard mask pattern. And etching the insulating film for the third hard mask pattern.

The present invention described above has the effect of realizing a fine pattern having a line width of 40 nm or less by using a plurality of hard mask patterns, currently available photolithography equipment.

As a result, there is an effect to implement a more highly integrated semiconductor device.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2A through 2E are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, the first hard mask layer 22 is formed on the etching target layer 21. In this case, the first hard mask layer 22 may be formed using an amorphous carbon layer (ACL) having excellent physical properties as a hard mask layer, and may have a thickness in the range of 200 μs to 1500 μs.

Next, a second hard mask film 23 is formed on the first hard mask film 22. In this case, the second hard mask film 23 may be formed using an oxide film, and may be formed to have a thickness in a range of 200 μs to 1500 μs. Preferably, the second hard mask layer 23 may be formed using TEOS (Tetra Ethyle Ortho Silicate) having excellent interfacial properties with the first hard mask layer 22, that is, the amorphous carbon layer.

As shown in FIG. 2B, a photoresist pattern 24 is formed on the second hard mask film 23. In this case, the photoresist pattern 24 may be formed using a lithography apparatus currently used, for example, a photolithography apparatus using a KrF exposure source or an ArF exposure source.

Next, the second hard mask layer 23 is etched using the photoresist pattern 24 as an etch barrier to form the second hard mask pattern 23A.

As shown in FIG. 2C, the photoresist pattern 24 is removed. In this case, the photoresist pattern 24 may be removed by an ashing process using an O 2 plasma.

Next, the third hard mask film 25 is formed to cover the second hard mask pattern 23A. In this case, the third hard mask layer 25 may be formed of a material having an etching selectivity with respect to the second hard mask pattern 23A. For example, the third hard mask layer 25 may be formed of a polysilicon layer.

As illustrated in FIG. 2D, the third hard mask layer 25 is etched to form a third hard mask pattern 25A using a target exposing the top surface of the second hard mask pattern 23A. In this case, the etching process for forming the third hard mask pattern 25A may be performed by using CF 4 gas or O 2 gas alone for a time ranging from 10 seconds to 200 seconds, or mixing CF 4 gas and O 2 gas. It can be carried out using the mixed gas.

Specifically, in the etching process for forming the third hard mask pattern 25A, CF 4 gas and O 2 gas are flowed in a range of 100 sccm to 1000 sccm, 100 sccm, respectively, while maintaining the chamber pressure within a range of 5 mT to 30 mT. Dry etching using a flow rate in the range of ˜2000 sccm may be performed using a plasma etching process. In this case, the etching characteristics may be controlled by applying a bias power in a range of 0V to 50V to the chamber bottom electrode in the state where the plasma is formed. Here, the bias power of 0 V means that the etching process is performed in a state in which the bias power is not applied to the chamber bottom electrode.

As a result, the third hard mask pattern 25A buried between the second hard mask patterns 23A can be formed, and compared with the line width of the second hard mask pattern 23A formed through the photoresist pattern 24. A third hard mask pattern 25A having a fine line width, that is, a line width of 40 nm or less can be formed.

As shown in FIG. 2E, the second hard mask pattern 23A is removed to leave only the third hard mask pattern 25A on the first hard mask layer 12. In this case, the second hard mask pattern 23A may be removed using an HF solution.

Next, the first hard mask layer 22 is etched using the third hard mask pattern 25A as an etch barrier to form the first hard mask pattern 22A. At this time, the etching process may be carried out using a flow rate of 10sccm ~ 500sccm mixed gas mixed with O 2 gas and N 2 gas for a time range of 10 seconds to 50 seconds.

Next, although not shown in the drawing, the etching target layer 21 is etched using the first hard mask pattern 22A as an etch barrier to form a desired pattern.

As described above, the present invention may implement a fine pattern having a line width of 40 nm or less by using a conventional photolithography apparatus by forming a plurality of hard mask patterns, thereby realizing a more highly integrated semiconductor device.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view showing a pattern of a semiconductor device according to the prior art.

2A through 2E are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

21: etching target layer 22A: the first hard mask pattern

23A: second hard mask pattern 24: photoresist pattern

25A: third hard mask pattern

Claims (7)

Forming a first hard mask layer on the etching target layer; Forming a second hard mask pattern on the first hard mask layer; Forming a third hard mask pattern to fill the second hard mask patterns; Removing the second hard mask pattern; Forming a first hard mask pattern by etching the first hard mask layer using the third hard mask pattern as an etch barrier; And Etching the etch target layer using the first hard mask pattern as an etch barrier; Method of forming a fine pattern of a semiconductor device comprising a. The method of claim 1, The first, second and third hard mask patterns are formed with a material having a different selectivity ratio. The method of claim 1, The first hard mask pattern is formed of an amorphous carbon film fine pattern of a semiconductor device. The method of claim 1, The second hard mask pattern is a fine pattern forming method of a semiconductor device formed of an oxide film. The method of claim 1, The third hard mask pattern is a method of forming a fine pattern of a semiconductor device formed of a polysilicon film. The method of claim 1, Wherein the first hard mask pattern is an amorphous carbon film, the second hard mask pattern is an oxide film, and the third hard mask pattern is a polysilicon film. The method of claim 1, Forming the third hard mask pattern, Forming an insulating film for a third hard mask pattern on the entire surface of the resultant including the second hard mask film pattern; And Etching the insulating film for the third hard mask pattern to expose an upper surface of the second hard mask pattern. Method of forming a fine pattern of a semiconductor device comprising a.
KR1020070135008A 2007-12-21 2007-12-21 Method for forming a micro pattern in semiconductor device KR20090067369A (en)

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Application Number Priority Date Filing Date Title
KR1020070135008A KR20090067369A (en) 2007-12-21 2007-12-21 Method for forming a micro pattern in semiconductor device

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Application Number Priority Date Filing Date Title
KR1020070135008A KR20090067369A (en) 2007-12-21 2007-12-21 Method for forming a micro pattern in semiconductor device

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376536A (en) * 2010-08-04 2012-03-14 海力士半导体有限公司 Method Of Manufacturing Fine Patterns
CN103187243A (en) * 2011-12-31 2013-07-03 中芯国际集成电路制造(北京)有限公司 Manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376536A (en) * 2010-08-04 2012-03-14 海力士半导体有限公司 Method Of Manufacturing Fine Patterns
CN103187243A (en) * 2011-12-31 2013-07-03 中芯国际集成电路制造(北京)有限公司 Manufacturing method of semiconductor device

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