KR100935252B1 - Method for manufacturing nano pattern of the semiconductor device - Google Patents

Method for manufacturing nano pattern of the semiconductor device Download PDF

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KR100935252B1
KR100935252B1 KR1020030047379A KR20030047379A KR100935252B1 KR 100935252 B1 KR100935252 B1 KR 100935252B1 KR 1020030047379 A KR1020030047379 A KR 1020030047379A KR 20030047379 A KR20030047379 A KR 20030047379A KR 100935252 B1 KR100935252 B1 KR 100935252B1
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pattern
insulating layer
metal
hard mask
nano
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KR20050007779A (en
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최선호
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2

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Abstract

본 발명은 반도체 소자의 나노 패턴 제조 방법에 관한 것으로서, 특히 반도체 기판 상부에 제 1절연막과, 금속막과, 제 2절연막을 순차적으로 형성하는 단계와, 제 2절연막을 선택 식각하여 나노 패턴의 간격을 조정하기 위한 식각 패턴을 형성하는 단계와, 제 2절연막의 식각 패턴 측면에 나노 폭을 갖으며 제 2절연막에 대해 식각 선택성이 있는 물질로 하드 마스크를 형성하는 단계와, 금속막 상부에 하드 마스크를 남겨두고 제 2절연막의 식각 패턴을 제거하는 단계와, 하드 마스크로 금속막을 패터닝하여 제 1절연막 상부에 나노 폭을 갖으며 인접된 패턴과의 간격이 동일 또는 상이한 금속 패턴을 형성하는 단계와, 하드 마스크를 제거하는 단계를 포함한다. 그러므로 본 발명은 고가의 노광 장비를 이용하지 않고서도 정밀한 나노 폭과 이들 패턴 간격을 조정할 수 있는 금속 패턴을 확보할 수 있다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nanopattern of a semiconductor device. In particular, the steps of sequentially forming a first insulating film, a metal film, and a second insulating film on an upper surface of a semiconductor substrate, and selectively etching the second insulating film are performed to space the nanopattern. Forming an etch pattern for adjusting the etch rate, forming a hard mask with a material having a nano width on the etch pattern side of the second insulating layer and having an etch selectivity with respect to the second insulating layer, and a hard mask on the upper portion of the metal layer Removing the etch pattern of the second insulating layer, leaving a gap; patterning a metal layer with a hard mask to form a metal pattern having nano width on the first insulating layer and having the same or different intervals from adjacent patterns; Removing the hard mask. Therefore, the present invention can secure a precise nano width and a metal pattern that can adjust the pattern spacing without using expensive exposure equipment.

나노 패턴, 패턴 간격, 절연막, 금속막Nano pattern, pattern spacing, insulating film, metal film

Description

반도체 소자의 나노 패턴 제조 방법{Method for manufacturing nano pattern of the semiconductor device} Method for manufacturing nano pattern of semiconductor device             

도 1 내지 도 7은 본 발명에 따른 고집적 반도체 소자의 나노 패턴 제조 과정을 나타낸 공정 순서도.
1 to 7 are process flowcharts illustrating a nanopattern manufacturing process of a highly integrated semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10 : 반도체 기판 12 : 제 1절연막10 semiconductor substrate 12 first insulating film

14 : 금속막 14a : 나노 폭을 갖는 금속 패턴14 metal film 14a metal pattern with nano width

14b : 일반 금속 패턴 16 : 제 2절연막14b: general metal pattern 16: second insulating film

16a, 16b : 식각 패턴 17, 20 : 포토레지스트 패턴16a and 16b etching patterns 17 and 20 photoresist patterns

18a : 하드 마스크 p1, p2 : 나노 폭 금속 패턴의 간격
18a: hard mask p1, p2: nano-width metal pattern spacing

본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 나노 크기(nano scale) 패턴 및 그 패턴 간격(pitch)을 제어하여 제한된 영역에서 소자의 집적도를 향상시킬 수 있는 반도체 소자의 나노 패턴 제조 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a nano pattern of a semiconductor device capable of improving the integration degree of a device in a limited region by controlling a nano scale pattern and a pattern pitch thereof. will be.

최근에는 반도체 소자의 고집적화 기술에 따라 반도체 소자의 선폭이 대략 수십 나노 미터(nanor meter) 정도의 선폭(CD : Critical Dimension)까지 도달하기에 이르렀다.Recently, according to the high integration technology of the semiconductor device, the line width of the semiconductor device has reached a line width (CD: Critical Dimension) of about several tens of nanometers (nanor meter).

이에 고집적화된 반도체 소자에서는 나노 미터 크기로 미세화된 배선의 패턴이 필요하며 패턴 사이의 간격(pitch) 또한 다양하게 조정할 수 있는 기술이 요구된다.
Accordingly, in the highly integrated semiconductor device, a pattern of a wiring fined to a nanometer size is required, and a technique for adjusting the pitch between the patterns in various ways is required.

본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 나노 패턴의 간격을 제어하는 식각 패턴을 형성하고 그 측면에 수직 스페이서로 하드 마스크를 형성한 후에 식각 패턴을 제거하여 하드 마스크로 금속을 패터닝함으로써 나노 선폭을 갖으며 패턴 간격이 동일 또는 서로 다른 금속 패턴을 제조함으로써 고가의 노광 장비를 이용하지 않고서도 정밀한 나노 폭과 패턴 간격을 갖는 금속 패턴을 확보할 수 있는 반도체 소자의 나노 패턴 제조 방법을 제공하는데 있다.
An object of the present invention is to form an etching pattern to control the gap of the nano-pattern in order to solve the problems of the prior art as described above and to form a hard mask with a vertical spacer on the side after removing the etching pattern to form a metal with a hard mask Method of manufacturing nano-pattern of semiconductor device that can secure metal pattern with precise nano-width and pattern spacing without using expensive exposure equipment by manufacturing metal pattern with nano-line width and pattern spacing with same or different patterning by patterning To provide.

상기 목적을 달성하기 위하여 본 발명은 반도체 기판 상부에 제 1절연막과, 금속막과, 제 2절연막을 순차적으로 형성하는 단계와, 제 2절연막을 선택 식각하여 나노 패턴의 간격을 조정하기 위한 식각 패턴을 형성하는 단계와, 제 2절연막의 식각 패턴 측면에 나노 폭을 갖으며 제 2절연막에 대해 식각 선택성이 있는 물질로 하드 마스크를 형성하는 단계와, 금속막 상부에 하드 마스크를 남겨두고 제 2절연막의 식각 패턴을 제거하는 단계와, 하드 마스크로 금속막을 패터닝하여 제 1절연막 상부에 나노 폭을 갖으며 인접된 패턴과의 간격이 동일 또는 상이한 금속 패턴을 형성하는 단계와, 하드 마스크를 제거하는 단계를 포함한다.
In order to achieve the above object, the present invention sequentially forms a first insulating film, a metal film, and a second insulating film on an upper surface of the semiconductor substrate, and selectively etches the second insulating film to adjust an etching pattern of the nanopattern. Forming a hard mask with a material having a nano width on an etch pattern side of the second insulating layer and having an etch selectivity with respect to the second insulating layer, and leaving a hard mask on the upper portion of the metal layer; Removing an etch pattern of the metal layer, patterning a metal layer with a hard mask to form a metal pattern having a nano width on the first insulating layer and having the same or different intervals from adjacent patterns, and removing the hard mask; It includes.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 7은 본 발명에 따른 고집적 반도체 소자의 나노 패턴 제조 과정을 나타낸 공정 순서도이다. 이들 도면들을 참조하면 본 발명의 나노 패턴 제조 방법은 다음과 같다.1 to 7 are process flowcharts illustrating a nanopattern manufacturing process of a highly integrated semiconductor device according to the present invention. Referring to these drawings, the nanopattern manufacturing method of the present invention is as follows.

우선 도 1에 도시된 바와 같이, 반도체 기판(10)으로서 실리콘 기판 상부에 제 1절연막(12)과, 금속막(14)과, 제 2절연막(16)을 순차적으로 적층한다. 이때 제 1절연막(12) 및 제 2절연막(16)은 동일 절연 물질로 형성하되, 본 실시예에서는 실리콘 산화막(SiO2), PE-TEOS(Plasma Enhanced-Ttetraethlyorthosilicate), BPSG(Boro Phospho Silicate Glass), SOG(Silicon On the Glass), 또는 FSG(Fluorine doped Silicate Glass)로 형성한다.First, as shown in FIG. 1, the first insulating film 12, the metal film 14, and the second insulating film 16 are sequentially stacked on the silicon substrate as the semiconductor substrate 10. At this time, the first insulating film 12 and the second insulating film 16 are formed of the same insulating material, but in this embodiment, silicon oxide film (SiO2), PE-TEOS (Plasma Enhanced-Ttetraethlyorthosilicate), BPSG (Boro Phospho Silicate Glass), It is formed of Silicon On the Glass (SOG) or Fluorine doped Silicate Glass (FSG).

그리고 사진 공정을 진행하여 제 2절연막(16) 상부에 나노 패턴의 간격을 정 의하는 포토레지스트 패턴(17)을 형성하고 이 패턴(17)을 이용한 건식 식각 공정을 진행하여 제 2절연막(16)을 패터닝한다. 이로 인해 도 2와 같이, 나노 패턴의 간격(pitch)을 조정하기 위한 제 2절연막의 식각 패턴(16a, 16b)이 형성되는데, 식각 패턴인 16a 및 16b는 설정된 나노 패턴의 간격에 의해 서로 다른 간격을 갖음을 보이고 있다. 이후 포토레지스트 패턴을 제거한다.Then, a photoresist pattern 17 is formed on the second insulating layer 16 to define the nanopattern gap on the second insulating layer 16, and a dry etching process using the pattern 17 is performed to form the second insulating layer 16. Pattern. Accordingly, as shown in FIG. 2, etching patterns 16a and 16b of the second insulating layer for adjusting the pitch of the nanopatterns are formed, and the etching patterns 16a and 16b are different from each other by the set intervals of the nanopatterns. Is showing. The photoresist pattern is then removed.

그 다음 도 3에 도시된 바와 같이, 제 2절연막의 식각 패턴(16a, 16b) 상부면 및 측면과 더불어 금속막(14) 상부 전면에 하드 마스크(hard mask)로 사용되는 절연막(18)을 얇게 형성한다. 여기서 절연막(18) 제 2절연막과 식각 선택성이 있는 물질로서, 본 실시예에서는 실리콘 질화막(Si3N4)으로 형성한다. Next, as shown in FIG. 3, the insulating film 18 used as a hard mask on the upper surface and the side surfaces of the second insulating film along with the upper and side surfaces of the etching patterns 16a and 16b of the second insulating film is thinned. Form. Here, the insulating film 18 is formed of a silicon nitride film (Si3N4) as a material having an etching selectivity with the second insulating film.

그 다음 전면 식각(etch back) 등의 식각 공정으로 제 2절연막의 식각 패턴(16a, 16b) 상부면 및 금속막(14) 상부의 절연막(18)이 제거되도록 식각하여 도 4와 같이 제 2절연막의 식각 패턴(16a, 16b) 측면에 나노 폭을 갖으며 스페이서(spacer) 형태의 하드 마스크(18a)를 형성한다.Next, the second insulating layer is etched such that an upper surface of the etch patterns 16a and 16b of the second insulating layer and the insulating layer 18 on the metal layer 14 are removed by an etching process such as an entire surface etch back. Etch patterns (16a, 16b) of the nano-width having a spacer (spacer) form a hard mask (18a) to form.

이어서 도 5에 도시된 바와 같이, 금속막(14) 상부에 하드 마스크만(18a)을 남겨두고 제 2절연막의 식각 패턴을 제거한다. 여기서, 하드 마스크(18a)는 서로 동일한 나노 폭을 갖으며 이들 마스크(18a) 패턴 사이의 간격(p1, p2)은 서로 상이하다. 하지만, 본 실시예에서는 마스크(18a) 패턴 사이의 간격(p1, p2)을 서로 상이하게 하였으나, 다른 실시예에서는 동일하게도 할 수 있음은 당업자라면 능히 알 수 있다. Subsequently, as shown in FIG. 5, the etching pattern of the second insulating layer is removed while leaving only the hard mask 18a on the metal layer 14. Here, the hard masks 18a have the same nano widths, and the intervals p1 and p2 between the patterns of the masks 18a are different from each other. However, in the present embodiment, the intervals p1 and p2 between the mask 18a patterns are different from each other, but it can be understood by those skilled in the art that the same can be done in other embodiments.

그 다음 도 6에 도시된 바와 같이, 사진 공정을 진행하여 금속막(14) 상부에 식각 대상 영역을 오픈(open)하는 포토레지스트 패턴(20)을 형성하고, 하드 마스크(18a)를 이용한 식각 공정을 진행하여 하부의 금속막(14)을 패터닝한다.Next, as shown in FIG. 6, a photoresist pattern 20 is formed on the metal layer 14 to open the etching target region on the metal layer 14, and the etching process using the hard mask 18a is performed. Next, the lower metal film 14 is patterned.

이로 인해 도 7과 같이, 제 1절연막(12) 상부에 나노 폭을 갖으며 인접된 패턴과의 간격(p1, p2)이 서로 상이(혹은 동일)한 금속 패턴(14a)이 형성된다. 그리고나서 도 6의 하드 마스크(18a) 및 포토레지스트 패턴(20)을 제거하면 본 발명에 따른 나노 패턴의 제조 공정이 완료된다.
As a result, as shown in FIG. 7, a metal pattern 14a having a nano width on the first insulating layer 12 and having different intervals (or the same) from adjacent patterns (p1, p2) is formed. Then, the hard mask 18a and the photoresist pattern 20 of FIG. 6 are removed to complete the nanopattern manufacturing process according to the present invention.

이상 상술한 바와 같이, 본 발명은 나노 패턴의 간격을 제어하는 식각 패턴을 형성하고 그 측면에 수직 스페이서로 하드 마스크를 형성한 후에 식각 패턴을 제거하여 하드 마스크로 금속을 패터닝함으로써 나노 선폭을 갖으며 패턴 간격이 동일 또는 서로 다른 금속 패턴을 제조함으로써 고가의 노광 장비를 이용하지 않고서도 정밀한 나노 폭과 이들 패턴 간격을 조정할 수 있는 금속 패턴을 확보할 수 있다.As described above, the present invention has a nanoline width by forming an etching pattern for controlling the interval of the nanopattern, and forming a hard mask with vertical spacers on the side thereof, and then removing the etching pattern to pattern the metal with the hard mask. By manufacturing metal patterns having the same or different pattern spacing, it is possible to secure precise nano widths and metal patterns that can adjust these pattern spacings without using expensive exposure equipment.

한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (5)

반도체 기판 상부에 제 1절연막과, 금속막과, 제 2절연막을 순차적으로 형성하는 단계;Sequentially forming a first insulating film, a metal film, and a second insulating film on the semiconductor substrate; 제 2절연막을 선택 식각하여 나노 패턴의 간격을 조정하기 위한 식각 패턴을 형성하는 단계;Selectively etching the second insulating layer to form an etching pattern for adjusting a gap of the nanopattern; 상기 제 2절연막의 식각 패턴 측면에 나노 폭을 갖으며 상기 제 2절연막에 대해 식각 선택성이 있는 물질로 하드 마스크를 형성하는 단계;Forming a hard mask with a material having a nano width on an etch pattern side of the second insulating layer and having an etch selectivity with respect to the second insulating layer; 상기 금속막 상부에 하드 마스크를 남겨두고 제 2절연막의 식각 패턴을 제거하는 단계;Removing an etching pattern of a second insulating layer by leaving a hard mask on the metal layer; 상기 하드 마스크로 상기 금속막을 패터닝하여 상기 제 1절연막 상부에 나노 폭을 갖으며 인접된 패턴과의 간격이 동일 또는 상이한 금속 패턴을 형성하는 단계; 및 Patterning the metal layer using the hard mask to form a metal pattern having a nano width on the first insulating layer and having the same or different intervals from adjacent patterns; And 상기 하드 마스크를 제거하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 나노 패턴 제조 방법. And removing the hard mask to form a nano pattern of the semiconductor device. 제 1항에 있어서, 상기 제 1절연막 및 제 2절연막은 동일 절연 물질인 것을 특징으로 하는 반도체 소자의 나노 패턴 제조 방법. The method of claim 1, wherein the first insulating layer and the second insulating layer are made of the same insulating material. 제 1항에 있어서, 상기 제 1절연막 및 제 2절연막은 산화 물질로 이루어지고, 상기 하드 마스크는 질화 물질로 이루어진 것을 특징으로 하는 반도체 소자의 나노 패턴 제조 방법.The method of claim 1, wherein the first insulating layer and the second insulating layer are made of an oxidized material, and the hard mask is made of a nitride material. 제 3항에 있어서, 상기 산화 물질은 실리콘 산화막, PE-TEOS, BPSG, SOG, 또는 FSG로 이루어진 것을 특징으로 하는 반도체 소자의 나노 패턴 제조 방법.The method of claim 3, wherein the oxidizing material is formed of a silicon oxide film, PE-TEOS, BPSG, SOG, or FSG. 제 1항에 있어서, 상기 하드 마스크로 상기 금속막을 패터닝하는 단계는, 상기 금속막 상부에 식각 대상 영역을 오픈하는 포토레지스트 패턴을 형성한 후에 진행하고 상기 금속 패턴을 형성한 후에 상기 포토레지스트 패턴을 제거하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 나노 패턴 제조 방법.The method of claim 1, wherein the patterning of the metal layer with the hard mask is performed after forming a photoresist pattern that opens an etch target region on the metal layer, and after forming the metal pattern, the photoresist pattern is formed. The method of manufacturing a nano-pattern of a semiconductor device further comprising the step of removing.
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