KR20060134342A - Method for manufacturing flash memory device - Google Patents

Abstract

A method for fabricating a flash memory device is provided to prevent polysilicon scum from being left on a substrate on which a floating gate doesn't need to be formed by forming an isolation layer whose lateral upper corners have a round type to remove a negative slope and by etching a polysilicon layer deposited as a floating gate. A pad oxide layer(111) and a pad nitride layer(112) are deposited on a semiconductor substrate(110). The pad nitride layer, the pad oxide layer and the substrate are etched to form a trench in the substrate. An isolation layer(113) is formed to fill the trench. The pad nitride layer is recessed. Both corners of the isolation layer protruding from the upper part of the recessed pad nitride layer are rounded by an isotropic etch process(115) using fluorine-based gas. The pad nitride layer and the pad oxide layer are removed.

Description

Flash memory device manufacturing method {METHOD FOR MANUFACTURING FLASH MEMORY DEVICE}

1 and 2 are process cross-sectional views showing a flash memory device manufacturing process according to the prior art.

3 to 6 are process cross-sectional views showing a flash memory device manufacturing process according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor substrate

11, 111: pad oxide film

12, 112: pad nitride film

13, 113: device isolation film

15: polysilicon residue

115: isotropic etching process

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a 0.07 탆 NAND flash memory device.

Recently, the demand for flash memory devices that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals is increasing. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

NAND flash memory devices (NAND-) in which a plurality of memory cells are connected in series (ie, structures in which drains or sources are shared with each other) to form a string for high integration of memory devices. type flash memory device) has been developed. Unlike NOR-type flash memory devices, NAND flash memory devices are memory devices that read information sequentially. The NAND flash memory device is programmed and erased by controlling the threshold voltage (Vt) of the memory cell while injecting or emitting electrons into a floating gate using an F-N tunneling method.

Meanwhile, in the case of a 0.07 μm technology-class NAND flash memory device, as illustrated in FIG. 1, after the pad oxide film 11 and the pad nitride film 12 are sequentially deposited on the substrate 10, the shallow trench is STI. Isolation is performed to form trenches (not shown). Then, an HDP (High Density Plasma) oxide film is deposited to fill the trench. Next, the HDP oxide film is planarized through a chemical mechanical polishing (CMP) process to form an isolation layer 13 isolated inside the trench.

Then, as shown in FIG. 2, after removing the pad nitride film 12 (see FIG. 1) and the pad oxide film 11 (see FIG. 1), the polysilicon for floating gate is formed on the entire structure including the device isolation layer 13. A film (not shown) is deposited. In addition, during the etching process for removing the polysilicon film in a region where the floating gate does not need to be formed, the polysilicon waste 15 remains on the sidewalls of the device isolation layer 13 protruding onto the substrate 10. The cause of such polysilicon waste 15 is as follows.

In the STI process, the pad nitride film 12 is used as an etch barrier layer. In the etching process, an upper sidewall of the pad nitride film 12 is lost by plasma, so that the shape changes from a square shape to a trapezoidal shape. do. When the pad nitride layer 12 is removed after the HDP oxide layer is deposited in this state, the top of the pad oxide layer 11 is deformed into a short trapezoidal shape, and thus the slope of the device isolation layer 13 has a negative slope. . Thus, the polysilicon film that was buried on the substrate 10 between the device isolation films 13 is not etched and thus remains on the substrate 10 along the negative slope of the device isolation film 13.

As such, the remaining polysilicon waste 15 adversely affects the subsequent process, and there is a problem of lowering the yield of the semiconductor device.

Accordingly, an object of the present invention is to provide a method for manufacturing a flash memory device capable of improving the yield of a semiconductor device, which is devised to solve the above problems of the prior art.

According to an aspect of the present invention, a pad oxide film and a pad nitride film are deposited on a semiconductor substrate, and the pad nitride film, the pad oxide film, and the substrate are etched to form trenches in the substrate. Forming a device isolation film in which the trench is buried, recessing the pad nitride film, rounding both edges of the device isolation film protruding over the recessed pad nitride film, and It provides a flash memory device manufacturing method comprising the step of removing the nitride film and the pad oxide film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if a layer is said to be "on" another layer or substrate it may be formed directly on another layer or substrate. Or a third layer may be interposed therebetween.

Example

3 to 6 are cross-sectional views illustrating a process of manufacturing a flash memory device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 3 to 6 are the same elements having the same function.

First, as shown in FIG. 3, the pad oxide layer 111 and the pad nitride layer 112 are sequentially deposited on the semiconductor substrate 110, and then a trench (not shown) is formed in the substrate 110 by performing an STI process. Form.

Subsequently, an HDP (High Density Plasma) oxide film is deposited so that the trench is embedded, and then a chemical mechanical polishing (CMP) process is performed to planarize the trench.

Subsequently, the pad nitride layer 112 and the pad oxide layer 111 are removed to form the device isolation layer 113 protruding above the substrate 110. At this time, the device isolation layer 113 has a negative slope as shown in the figure.

Subsequently, as illustrated in FIG. 4, the etching process 114 is performed to recess the exposed pad nitride layer 112 to a predetermined depth. Here, the etching process 114 uses HBr gas to secure a high etching selectivity with the pad oxide layer 111.

Subsequently, as shown in FIG. 5, an isotropic etching process 115 is performed to round both corner portions of the device isolation layer 113 protruding over the recessed pad nitride layer 112 (see 'R' region). Let's do it. As a result, the negative slope of the device isolation layer 113 is removed. In this case, the isotropic etching process 115 uses a fluorine (F) -based gas.

Subsequently, as shown in FIG. 6, a wet etching process is performed to remove the remaining pad nitride film 112 (see FIG. 5) and the pad oxide film 111 (see FIG. 5).

Subsequently, although not shown in the drawing, after depositing the polysilicon film for floating gate, an etching process for removing the polysilicon film in an unnecessary area is performed.

At this time, since the device isolation layer having rounded shapes at both upper edges is formed so that the negative slope is removed, the polysilicon film in a region where the floating gate does not need to be formed does not remain on the substrate. Therefore, the yield of a semiconductor element can be improved.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, after forming a device isolation film having a rounded shape at both upper corners so that the negative slope is removed, the floating gate does not need to be formed by etching the polysilicon film deposited for the floating gate. Prevents polysilicon residues from remaining on the substrate in the region. Therefore, the yield of a semiconductor element can be improved.

Claims (6)

Depositing a pad oxide film and a pad nitride film on the semiconductor substrate; Etching the pad nitride film, the pad oxide film, and the substrate to form a trench in the substrate; Forming an isolation layer in which the trench is buried; Recessing the pad nitride film; Rounding both edges of the device isolation layer protruding from the recessed pad nitride layer; And Removing the pad nitride film and the pad oxide film Flash memory device manufacturing method comprising a. The method of claim 1, Rounding both edges of the device isolation layer is a flash memory device manufacturing method using an isotropic etching process. The method of claim 2, The isotropic etching process is a flash memory device manufacturing method using a fluorine-based gas. The method according to any one of claims 1 to 3, And recessing the pad nitride layer using HBr gas to secure an etch selectivity with the pad oxide layer. The method according to any one of claims 1 to 3, Removing the pad nitride layer is performed by performing a wet etching process using a phosphoric acid solution at a temperature of 150 to 160 ℃. The method according to any one of claims 1 to 3, The removing of the pad oxide layer is performed by performing a wet etching process using a diluted HF solution.

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