KR20060133804A - Fbga package - Google Patents

Fbga package Download PDF

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Publication number
KR20060133804A
KR20060133804A KR1020050053647A KR20050053647A KR20060133804A KR 20060133804 A KR20060133804 A KR 20060133804A KR 1020050053647 A KR1020050053647 A KR 1020050053647A KR 20050053647 A KR20050053647 A KR 20050053647A KR 20060133804 A KR20060133804 A KR 20060133804A
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KR
South Korea
Prior art keywords
substrate
window
semiconductor chip
ball
fbga package
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KR1020050053647A
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Korean (ko)
Inventor
윤종필
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주식회사 하이닉스반도체
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Priority to KR1020050053647A priority Critical patent/KR20060133804A/en
Publication of KR20060133804A publication Critical patent/KR20060133804A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

An FBGA package is provided to prevent the degradation of a package reliability by restraining a molding resin from penetrating into a ball land region in a molding process using a teflon coating. An FBGA package comprises a center pad type semiconductor chip, a substrate, a metal wire, a molding material, and solder balls. The substrate includes a window(23) at a center portion, a plurality of bond fingers electrically connected with bonding pads of the semiconductor chip and ball lands(22). The metal wire is used for connecting the bonding pad of the semiconductor chip with the bond finger of the substrate through the substrate window. The molding material is used for sealing selectively the resultant structure. The solder balls are attached to the ball lands. A teflon coating(25) is formed at a boundary between the window region and the ball land region on the substrate.

Description

ＦＢＧＡ 패키지{FBGA package}FBA package {FBGA package}

도 1은 종래의 FBGA 패키지에 사용된 기판의 저면도.1 is a bottom view of a substrate used in a conventional FBGA package.

도 2는 본 발명에 따른 FBGA 패키지용 기판의 저면도.2 is a bottom view of a substrate for an FBGA package according to the present invention.

도 3은 본 발명에 따른 FBGA 패키지의 단면도.3 is a cross-sectional view of an FBGA package according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

20: 기판 21: 윈도우20: substrate 21: window

22: 볼 랜드 23: 윈도우 영역22: Borland 23: Window Area

24: 볼 랜드 영역 25: 테프론 코팅24: Borland area 25: Teflon coating

30: 반도체 칩 40: 몰딩 수지30: semiconductor chip 40: molding resin

본 발명은 반도체 패키지에 관한 것으로써, 더욱 상세하게는, 테플론(teflon) 코팅이 된 기판을 사용한 FBGA 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to an FBGA package using a substrate having a Teflon coating.

일반적으로 FBGA 패키지는 센터 패드형의 반도체 칩이 윈도우 및 다수개의 본드 핑거를 구비한 기판 상에 페이스-다운 타입으로 부착되고, 상기 본딩패드와 본드 핑거는 상기 기판의 윈도우를 관통하는 금속와이어를 통해 전기적으로 연결된다. 이후, 상기 반도체 칩을 포함한 기판의 상부면과 기판 윈도우 부분은 몰딩수지로 밀봉되며, 상기 기판 하부면의 볼 랜드에는 솔더 볼이 부착된다.In general, an FBGA package has a center pad-type semiconductor chip attached face-down on a substrate having a window and a plurality of bond fingers, and the bonding pad and the bond finger are formed through metal wires passing through the window of the substrate. Electrically connected. Thereafter, the upper surface of the substrate including the semiconductor chip and the substrate window portion are sealed with a molding resin, and solder balls are attached to the ball lands on the lower surface of the substrate.

그러나, 이와 같은 구조를 갖는 종래의 FBGA 패키지는 몰딩 공정시 기판의 윈도우 영역에서 몰드 플레쉬가 발생할 수 있다. 이러한 문제를 도 1을 참조하여 살펴보면, 도 1은 종래의 FBGA 패키지에 사용된 기판의 저면도로서, 와이어 본딩이 실시된 기판의 윈도우 영역이 몰딩 수지로 밀봉된 상태를 도시한다.However, in the conventional FBGA package having such a structure, mold flash may occur in the window region of the substrate during the molding process. Referring to this problem with reference to Figure 1, Figure 1 is a bottom view of a substrate used in a conventional FBGA package, the window area of the substrate subjected to the wire bonding is shown sealed with a molding resin.

도시한 바와 같이, 기판의 윈도우 영역(10) 상의 몰딩 수지(11)가 기판의 볼랜드 영역(12)까지 침범하는 현상인 몰드 플레쉬가 발생하는 것을 알 수 있다. 이는, 몰딩 공정시 기판의 윈도우 영역(10)과 볼랜드 영역(12) 사이에 트랜스터의 압력 차이 또는 패턴의 불균일성 등으로 인해 발생하는 것으로서, 패키지 자체의 신뢰성을 저하시킨다.As shown, it can be seen that a mold flash, which is a phenomenon in which the molding resin 11 on the window region 10 of the substrate invades the ballland region 12 of the substrate, occurs. This is caused due to the pressure difference of the transmitter or the non-uniformity of the pattern between the window region 10 and the borland region 12 of the substrate during the molding process, thereby lowering the reliability of the package itself.

따라서, 본 발명은 상기한 바와 같은 선행 기술에 내재되었던 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은, 테플론 코팅이 실시된 기판을 사용함으로써, 몰드 플레쉬를 방지할 수 있는 FBGA 패키지를 제공함에 있다.Accordingly, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to provide a FBGA package which can prevent mold flash by using a substrate having a Teflon coating applied thereto. Is in.

상기한 바와 같은 목적을 달성하기 위해, 본 발명의 일면에 따라, FBGA 패키지가 제공되며: 이 패키지는, 센터패드형 반도체 칩; 상기 반도체 칩이 페이스-다 운 타입으로 부착되며, 중심부에 윈도우를 구비하고, 하부면에 반도체 칩의 본딩패드와 전기적으로 연결되는 다수의 본드핑거와 볼 랜드를 구비한 기판; 상기 기판 윈도우를 관통하여 반도체 칩의 본딩패드와 기판 본드핑거 간을 연결하는 금속와이어; 상기 반도체 칩을 포함한 기판 상부면과 기판 윈도우 부분을 밀봉하는 봉지제; 및 상기 기판 하부면의 볼 랜드에 부착된 솔더 볼;을 포함하며, 상기 기판은 상기 윈도우 영역과 상기 볼 랜드 영역의 경계면에 테플론(teflon) 코팅이 되어 있는 것을 특징으로 한다.In order to achieve the above object, in accordance with an aspect of the present invention, there is provided an FBGA package comprising: a center pad type semiconductor chip; A substrate having a plurality of bond fingers and ball lands to which the semiconductor chip is attached in a face-down type, the window having a center portion and electrically connected to a bonding pad of the semiconductor chip on a lower surface thereof; A metal wire penetrating the substrate window to connect a bonding pad of the semiconductor chip to a substrate bond finger; An encapsulant for sealing a substrate upper surface and the substrate window portion including the semiconductor chip; And a solder ball attached to a ball land of the lower surface of the substrate, wherein the substrate has a Teflon coating on an interface between the window area and the ball land area.

(실시예)(Example)

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상술하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 FBGA 패키지용 기판의 저면도이다.2 is a bottom view of a substrate for an FBGA package according to the present invention.

도시한 바와 같이, 본 발명에 따른 FBGA 패키지용 기판은 중심부에 형성된 윈도우(21), 및 윈도우(21)를 중심으로 기판 양측에 형성된 다수의 볼 랜드(22)를 포함하며, 특히, 윈도우 영역(23)과 볼 랜드 영역(24)의 경계면에는 테프론(teflon) 코팅(25)이 되어있다. 여기서, 테프론 코팅(25)은 불소수지를 도료화하여 페인트처럼 표면에 적당량 스프레이한 후, 일정한 온도에서 가열, 소성을 거치면 비활성의 단단한 코팅층을 형성하는 것을 지칭한다. 이러한, 테프론 코팅(25)은 패키지의 몰딩 공정시 윈도우 영역(23) 상의 몰딩 수지가 볼 랜드 영역(24)으로 침범하는 현상인 몰드 플레쉬를 방지하기 위함이다.As shown, the FBGA package substrate according to the present invention includes a window 21 formed at the center and a plurality of ball lands 22 formed at both sides of the substrate 21, and in particular, the window area ( At the interface between the 23 and the ball land region 24 is a Teflon coating 25. Here, the Teflon coating 25 refers to forming an inert hard coating layer by coating a fluorine resin and spraying an appropriate amount on the surface like paint, and then heating and baking at a constant temperature. The Teflon coating 25 is to prevent mold flash, which is a phenomenon in which the molding resin on the window region 23 invades the ball land region 24 during the molding process of the package.

상기와 같이 테프론 코팅이 실시된 FBGA 패키지용 기판의 제작이 완료되면, 일련의 공정을 통해 FBGA 패키지를 제작한다. When the fabrication of the substrate for the FBGA package subjected to the Teflon coating as described above is completed, the FBGA package is manufactured through a series of processes.

이러한 일련의 공정을, 도 3을 참조하여 살펴보면, 본 발명에 따른 FBGA 패키지는, 테프론 코팅이 실시된 기판(20) 상에 센터 패드형 반도체 칩(30)이 페이스-다운 타입으로 부착되고, 반도체 칩(30)의 본딩패드(31)와 기판의 본드 핑거(도시안됨)는 기판(20)의 윈도우(21)를 관통하는 금속와이어(32)를 통해 전기적으로 연결된다. 그리고, 반도체 칩(30)을 포함한 기판(20) 상부면과 기판 윈도우 영역(23)은 몰딩수지(40)로 밀봉되고, 기판(20) 하부면의 볼 랜드(22)에는 솔더 볼(26)이 부착된다. 이 때, 기판(20) 상에 실시된 테플론 코팅은 몰딩 수지가 볼 랜드 영역(24)까지 침범하는 현상인 몰드 플레쉬의 발생을 방지한다.Referring to this series of processes, referring to Figure 3, the FBGA package according to the present invention, the center pad-type semiconductor chip 30 is attached to the teflon coating substrate 20 is a face-down type, the semiconductor The bonding pad 31 of the chip 30 and the bond finger (not shown) of the substrate are electrically connected through the metal wire 32 passing through the window 21 of the substrate 20. The upper surface of the substrate 20 including the semiconductor chip 30 and the substrate window region 23 are sealed with a molding resin 40, and solder balls 26 are formed on the ball lands 22 of the lower surface of the substrate 20. Is attached. At this time, the Teflon coating applied on the substrate 20 prevents the occurrence of mold flash, a phenomenon in which the molding resin invades the ball land region 24.

이상에서 살펴본 바와 같이, 본 발명에 따른 FBGA 패키지는 기판의 윈도우 영역과 볼랜드 영역의 경계면에 테플론 코팅이 실시된 FBGA 패키지용 기판을 사용함으로써, 몰딩 공정시 기판의 저면에서 발생할 수 있는 몰드 플레쉬를 방지할 수 있다.As described above, the FBGA package according to the present invention uses a FBGA package substrate having a Teflon coating on the interface between the window region and the borland region of the substrate, thereby preventing mold flash that may occur at the bottom of the substrate during the molding process. can do.

본 발명의 상기한 바와 같은 구성에 따라, 몰딩 공정시 윈도우 영역 상의 몰딩 수지가 볼 랜드 영역으로 침범하는 몰드 플레쉬를 방지함으로써, 패키지의 신뢰성 저하를 방지할 수 있다.According to the configuration as described above of the present invention, by preventing the mold flash in which the molding resin on the window area invades the ball land area during the molding process, it is possible to prevent the degradation of the package reliability.

본 발명을 특정의 바람직한 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the invention has been shown and described with reference to certain preferred embodiments, the invention is not so limited, and the invention is not limited to the spirit and scope of the invention as set forth in the following claims. It will be readily apparent to those skilled in the art that these various modifications and variations can be made.

Claims (1)

센터패드형 반도체 칩; A center pad semiconductor chip; 상기 반도체 칩이 페이스-다운 타입으로 부착되며, 중심부에 윈도우를 구비하고, 하부면에 반도체 칩의 본딩패드와 전기적으로 연결되는 다수의 본드핑거와 볼 랜드를 구비한 기판; A substrate having a plurality of bond fingers and ball lands to which the semiconductor chip is attached in a face-down type, having a window at a center thereof, and electrically connected to a bonding pad of the semiconductor chip at a lower surface thereof; 상기 기판 윈도우를 관통하여 반도체 칩의 본딩패드와 기판 본드핑거 간을 연결하는 금속와이어; A metal wire penetrating the substrate window to connect a bonding pad of the semiconductor chip to a substrate bond finger; 상기 반도체 칩을 포함한 기판 상부면과 기판 윈도우 부분을 밀봉하는 봉지제; 및 An encapsulant for sealing a substrate upper surface and the substrate window portion including the semiconductor chip; And 상기 기판 하부면의 볼 랜드에 부착된 솔더 볼;을 포함하며,It includes; solder ball attached to the ball land of the lower surface of the substrate, 상기 기판은 상기 윈도우 영역과 상기 볼 랜드 영역의 경계면에 테플론 코팅이 되어 있는 것을 특징으로 하는 FBGA 패키지.The substrate is a FBGA package, characterized in that the Teflon coating on the interface between the window region and the ball land region.
KR1020050053647A 2005-06-21 2005-06-21 Fbga package KR20060133804A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8116088B2 (en) 2007-05-09 2012-02-14 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same, and printed circuit board
US8304892B2 (en) 2009-06-10 2012-11-06 Samsung Electronics Co., Ltd. Semiconductor package having substrate with solder ball connections and method of fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8116088B2 (en) 2007-05-09 2012-02-14 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same, and printed circuit board
US8304892B2 (en) 2009-06-10 2012-11-06 Samsung Electronics Co., Ltd. Semiconductor package having substrate with solder ball connections and method of fabricating the same
US8828795B2 (en) 2009-06-10 2014-09-09 Samsung Electronics Co., Ltd. Method of fabricating semiconductor package having substrate with solder ball connections

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