KR100251864B1 - Dispensing method of glob top for semiconductor package - Google Patents

Dispensing method of glob top for semiconductor package Download PDF

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KR100251864B1
KR100251864B1 KR1019970064124A KR19970064124A KR100251864B1 KR 100251864 B1 KR100251864 B1 KR 100251864B1 KR 1019970064124 A KR1019970064124 A KR 1019970064124A KR 19970064124 A KR19970064124 A KR 19970064124A KR 100251864 B1 KR100251864 B1 KR 100251864B1
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South Korea
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semiconductor chip
circuit pattern
applying
circuit board
printed circuit
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KR1019970064124A
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Korean (ko)
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KR19990043137A (en
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강원준
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김규현
아남반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A method for applying a liquid encapsulant for a semiconductor package is provided to minimize the formation of voids. CONSTITUTION: For the semiconductor package(100), the liquid encapsulant(50) is separately applied to a circuit pattern(11) of a printed circuit board(10) and a top surface of a semiconductor chip(30) by using a dispenser(60). The liquid encapsulant(50) applied flows spontaneously toward a conductive wire(40) and then collects below and over the conductive wire(40) without forming voids. The application of the liquid encapsulant(50) may be performed in twice within the confines of a dam(80). The circuit pattern(11) is partly exposed outside the dam(80) and thus the circuit forms a land(12) for a solder ball.

Description

반도체패키지용 액상봉지재의 도포 방법Application Method of Liquid Encapsulant for Semiconductor Package

본 발명은 반도체패키지용 액상봉지재의 도포 방법에 관한 것으로, 보다 상세하게 설명하면 인쇄회로기판의 회로패턴, 반도체칩 및 전도성와이어 등의 상부에서 액상봉지재를 도포하는 방법을 개선하여 그 전도성와이어의 주변 및 그 하단의 보이드 발생을 최소화할 수 있는 반도체패키지용 액상봉지재의 도포 방법에 관한 것이다.The present invention relates to a method for applying a liquid encapsulant for a semiconductor package, and more particularly, to improve a method for applying a liquid encapsulant on a printed circuit board, such as a circuit pattern, a semiconductor chip, and a conductive wire. The present invention relates to a method of applying a liquid encapsulant for a semiconductor package which can minimize the generation of voids at the periphery and at the bottom thereof.

일반적으로 액상봉지재(Glob Top)는 반도체칩, 전도성와이어, 리드프레임 또는 인쇄회로기판 등을 외부의 환경으로부터 보호하기 위해 사용되는 봉지수단으로써 에폭시몰드컴파운드(Epoxy Mold Compound)와 함께 가장 많이 사용되고 있는 것 중의 하나이다. 여기서 상기 에폭시몰드컴파운드를 이용한 봉지공정은 일정한 모양을 가진 금형이 필요하게 됨으로써 초기 투자 비용이 많이 소비되고 또한 고압으로 에폭시몰드컴파운드를 상기 금형내에 충진하여야 함으로써 금형 내부에 위치된 반도체패키지의 한 구성 요소인 전도성와이어가 휘어져서 서로 쇼트되는 현상이 비교적 쉽게 발생하는 단점이 있다. 그러나 상기 액상봉지재는 상기 에폭시몰드컴파운드와 비교해 볼 때 금형이 필요하지 않음으로써 초기 투자 비용이 적게 들며, 또한 상부에서 단순히 디스펜서를 이용하여 액상봉지재를 도포하는 방법을 사용함으로써 전도성와이어의 휘어지는 현상(스위핑, Sweeping)을 제거할 수 있음으로써 최근 많이 이용되고 있는 봉지수단이다.In general, a liquid encapsulant (Glob Top) is an encapsulation means used to protect a semiconductor chip, a conductive wire, a lead frame or a printed circuit board from an external environment, and is most commonly used with an epoxy mold compound. It is one of the things. Here, the encapsulation process using the epoxy mold compound requires a mold having a certain shape, which requires a high initial investment cost, and also requires that the epoxy mold compound be filled into the mold at a high pressure, thereby forming a component of a semiconductor package located inside the mold. Phosphorus conductive wires are bent and shorted to each other, which is a disadvantage that occurs relatively easily. However, the liquid encapsulant does not require a mold as compared to the epoxy mold compound, and thus, the initial investment cost is low, and the bending phenomenon of the conductive wire is achieved by simply applying a liquid encapsulant using a dispenser at the top ( It is an encapsulation means that is widely used in recent years by being able to eliminate sweeping.

이러한 액상봉지재는 특히 원사이드몰딩(One Side Molding, 한면만을 몰딩하는 방법)을 채택한 반도체패키지들 예를 들면, 볼그리드어레이(Ball Grid Array)반도체패키지, 핀그리드어레이(Pin Grid Array)반도체패키지의 봉지수단으로 사용되고 있으며, 이중 상기 볼그리드어레이반도체패키지를 중심으로 그것의 간단한 구조와 더불어 액상봉지재를 도포하는 방법을 설명하면 다음과 같다.Such liquid encapsulant is particularly suitable for semiconductor packages employing one side molding, for example, ball grid array semiconductor packages, pin grid array semiconductor packages, or the like. It is used as an encapsulation means, and a method of applying a liquid encapsulant with its simple structure centering on the ball grid array semiconductor package is as follows.

액상봉지재(50)를 사용하는 반도체패키지(100)의 구조는 도1a에 도시한 바와 같이, 저면에 히트싱크(20)가 위치되어 있고, 상기 히트싱크(20)의 상면 중앙부에는 반도체칩(30)이 접착제로 접착되어 있으며, 상기 히트싱크(20)의 상면 즉, 반도체칩(30)의 외주변에는 소정의 회로패턴(11)이 형성된 인쇄회로기판(10)이 접착제로 접착되어 있다. 상기 반도체칩(30)은 인쇄회로기판(10)의 회로패턴(11)에 전도성와이어(40)로 본딩되어 전기적 신호를 입/출력할 수 있도록 되어 있으며, 상기 인쇄회로기판(10)의 상면에는 솔더볼(70)이 융착되어 있어 메인보드로 각종 신호를 입/출력할 수 있도록 되어 있다.In the structure of the semiconductor package 100 using the liquid encapsulant 50, as shown in FIG. 1A, a heat sink 20 is positioned on a bottom surface of the semiconductor package 100, and a semiconductor chip ( 30 is bonded with an adhesive, and a printed circuit board 10 having a predetermined circuit pattern 11 is attached to the upper surface of the heat sink 20, that is, the outer periphery of the semiconductor chip 30. The semiconductor chip 30 is bonded to the circuit pattern 11 of the printed circuit board 10 with the conductive wires 40 so as to input and output electrical signals. The upper surface of the printed circuit board 10 Since the solder ball 70 is fused, various signals can be input / output to the main board.

도면중 미설명 부호 13은 회로패턴 등을 보호하기 위해 얇게 코팅된 솔더마스크이고, 12는 솔더볼이 융착된 솔더볼랜드이며, 31은 반도체칩의 표면에 형성된 입/출력패드이다.In the drawings, reference numeral 13 denotes a solder mask thinly coated to protect a circuit pattern and the like, 12 denotes a solder ball land in which solder balls are fused, and 31 denotes an input / output pad formed on a surface of a semiconductor chip.

한편, 상기 반도체칩(30), 전도성와이어(40) 등의 상부에는 외부의 전기적, 기계적, 화학적 환경으로부터 격리하여 보호하기 위해 액상봉지재(50)가 도포되어 있으며, 상기 액상봉지재(50)가 인쇄회로기판(10)의 솔더볼(70)쪽으로 더이상 진행하지 못하도록 상기 인쇄회로기판(10)에는 일정높이의 댐(80)이 구비되어 있다.Meanwhile, the liquid encapsulant 50 is coated on the semiconductor chip 30 and the conductive wire 40 to protect the electronic chip from the external electrical, mechanical, and chemical environment, and the liquid encapsulant 50. The printed circuit board 10 is provided with a dam 80 having a predetermined height such that the printed circuit board 10 does not proceed further toward the solder ball 70 of the printed circuit board 10.

이러한 구조의 반도체패키지(100)에 있어서 상기 액상봉지재(50)가 도포되기 전의 상태는 도1b의 평면도에 도시되어 있으며, 상기 반도체패키지(100)에 액상봉지재(50)가 도포되는 상태는 도1c에 도시되어 있다.In the semiconductor package 100 having such a structure, the state before the liquid encapsulant 50 is applied is shown in the plan view of FIG. 1B, and the state in which the liquid encapsulant 50 is applied to the semiconductor package 100 is shown. It is shown in Figure 1c.

도시된 바와 같이 종래의 도포 방법은 인쇄회로기판(10)에 형성된 사각 댐(80)의 내측에 연속적으로 나선형의 모양으로 도포하는 방법을 사용하였다. 즉, 상기 사각 댐(80)의 내주변에서부터 반도체칩(30)의 중앙부를 향하여 그 휘어지는 길이가 축소되면서 나선형으로 도포를 실시하던지 또는 상기 반도체칩(30)의 중앙에서 댐(80)의 내변을 향하여 확장하면서 연속적으로 도포를 하였다.As shown in the related art, a conventional coating method uses a method of continuously applying spirally inside the square dam 80 formed on the printed circuit board 10. That is, the curved length is reduced from the inner periphery of the rectangular dam 80 toward the central portion of the semiconductor chip 30 while spirally applying or the inner side of the dam 80 at the center of the semiconductor chip 30. The coating was applied continuously while expanding toward.

이와 같이 인쇄회로기판(10)의 회로패턴(11), 전도성와이어(40) 및 반도체칩(30) 등에 연속적으로 액상봉지재(50)를 도포하게 되면 상기 도포된 액상봉지재(50)는 골고루 퍼지면서 평평한 상태로 되고 소정의 시간이 지난후에는 딱딱하게 굳어짐으로써 상기 회로패턴(11), 전도성와이어(40), 반도체칩(30) 등을 외부 환경과 격리시켜 보호하게 된다.As such, when the liquid encapsulant 50 is continuously applied to the circuit pattern 11, the conductive wire 40, and the semiconductor chip 30 of the printed circuit board 10, the coated liquid encapsulant 50 is evenly distributed. After spreading to a flat state and hardening after a predetermined time, the circuit pattern 11, the conductive wire 40, the semiconductor chip 30, and the like are isolated and protected from the external environment.

그러나 이러한 액상봉지재(50)의 도포 방법은 액상봉지재(50)를 인쇄회로기판(10)의 회로패턴(11), 반도체칩(30)의 상면뿐만 아니라 상기 반도체칩(30)과 회로패턴(11)을 연결시키고 있는 얇은 전도성와이어(40)에도 직접 도포됨으로써 상기 전도성와이어(40)가 휘어지거나 또는 상기 전도성와이어(40) 하단 및 그 주변에 다수의 보이드(Void)가 형성되는 문제점이 있다. 즉, 인쇄회로기판(10)의 회로패턴(11) 내측과 반도체칩(30)의 외주변 사이는 움푹 패인 형상을 하고 또한 상부에는 촘촘하게 연결된 전도성와이어(40)가 위치함으로써 상기 전도성와이어(40)의 상부에서 액상봉지재(50)를 강제로 도포하게 되면 상기 움푹파인 부분의 공기가 미처 빠져나가지 못하게 됨으로써 다수의 보이드가 발생되는 것이다. 이렇게 보이드가 다량 발생하게 되면 차후에 반도체패키지의 보관 및 사용중에 상기 보이드가 수분을 흡수하여 저장하는 수단이 됨으로써 반도체패키지의 작동중 발생하는 열에 의해 팝콘(Pop Corn)현상 또는 크랙(Crack)을 유발시키고 그 액상봉지재의 표면 외관미도 저하시키는 문제점이 있다.However, the method of applying the liquid encapsulation member 50 includes the liquid encapsulant 50 as well as the circuit pattern 11 of the printed circuit board 10 and the upper surface of the semiconductor chip 30 as well as the semiconductor chip 30 and the circuit pattern. Directly applied to the thin conductive wire 40 connecting the 11, there is a problem that the conductive wire 40 is bent or a plurality of voids (Void) is formed at the bottom and the periphery of the conductive wire 40 . That is, the conductive wire 40 has a recessed shape between the inside of the circuit pattern 11 of the printed circuit board 10 and the outer periphery of the semiconductor chip 30, and the conductive wire 40 is closely connected to the upper portion thereof. When the liquid encapsulation material 50 is forcibly applied at the upper portion of the hollow portion, the voids are prevented from escaping. When a large amount of voids are generated, the voids become means of absorbing and storing moisture during storage and use of the semiconductor package, thereby causing pop corn phenomenon or cracks due to heat generated during operation of the semiconductor package. There is a problem of reducing the surface appearance of the liquid encapsulant.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 인쇄회로기판의 회로패턴, 반도체칩 및 전도성와이어 등의 상부를 액상봉지재로 도포하는 방법을 개선하여 보이드 발생을 최소화할 수 있는 반도체패키지용 액상봉지재의 도포 방법을 제공하는데 있다.Therefore, the present invention has been made to solve the above-mentioned conventional problems, it is possible to minimize the generation of voids by improving the method of applying the upper portion of the circuit pattern of the printed circuit board, semiconductor chips and conductive wires, etc. with a liquid encapsulation material. There is provided a method of applying a liquid encapsulant for a semiconductor package.

도1a는 액상봉지재가 도포된 볼그리드어레이반도체패키지의 구조를 도시한 단면도이고, 도1b는 솔더볼의 융착 및 액상봉지재의 도포 전 상태를 도시한 평면도이며, 도1c는 액상봉지재가 도포되는 상태를 도시한 상태도이다.Figure 1a is a cross-sectional view showing the structure of the ball grid array semiconductor package coated with a liquid encapsulation material, Figure 1b is a plan view showing the state before fusion of the solder ball and the liquid encapsulation material, Figure 1c is a state in which the liquid encapsulation material is applied It is a state figure shown.

도2a는 본 발명에 의한 액상봉지재 도포 방법을 도시한 상태도이다.Figure 2a is a state diagram showing a liquid sealing material coating method according to the present invention.

도2b은 본 발명의 액상봉지재 도포 방법에 의해 도포되는 상태를 도시한 상태도이다.Figure 2b is a state diagram showing a state applied by the liquid sealing material coating method of the present invention.

- 도면중 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

100 ; 반도체패키지(Package) 10 ; 인쇄회로기판100; Semiconductor package 10; Printed circuit board

11 ; 회로패턴(Pattern) 12 ; 솔더볼랜드(Solder Ball Land)11; Pattern 12; Solder Ball Land

13 ; 솔더마스크(Solder Mask) 20 ; 히트싱크(Heat Sink)13; Solder Mask 20; Heat Sink

30 ; 반도체칩(Chip) 31 ; 입/출력패드(Pad)30; A semiconductor chip 31; Input / Output Pads

40 ; 전도성와이어(Wire) 50 ; 액상봉지재40; Conductive wire 50; Liquid Encapsulant

60 ; 디스펜서(Dispensor) 70 ; 솔더볼(Solder Ball)60; Dispenser 70; Solder Ball

80 ; 댐(Dam)80; Dam

상기한 목적을 달성하기 위해 본 발명은 내측에는 액상봉지재가 외측으로 흘러가지 못하도록 댐이 형성되어 있고, 상기 댐의 외측에는 다수의 솔더볼이 안착될 수 있도록 솔더볼랜드가 형성되어 있으며, 상기 솔더볼랜드에 연결되어 회로패턴이 댐의 내측에서 외부로 노출되어 있는 인쇄회로기판과; 상기 인쇄회로기판의 회로패턴 내측에 다수의 입/출력패드가 형성된 채 접착제로 접착된 반도체칩과; 상기 반도체칩의 입/출력패드와 인쇄회로기판의 회로패턴을 연결하는 전도성와이어를 포함하여 이루어진 반도체패키지에서 상기 회로패턴, 전도성와이어 및 반도체칩의 상부를 액상봉지재로 도포하는 방법에 있어서, 상기 액상봉지재를 인쇄회로기판의 회로패턴과 반도체칩의 상면에만 도포하여 상기 전도성와이어 및 그 하부에는 액상봉지재가 스스로 흘러들어가게 하는 방법을 특징으로 한다.In order to achieve the above object, the present invention is formed with a dam to prevent the liquid encapsulant from flowing outward, and a solder ball land is formed at the outside of the dam to allow a plurality of solder balls to be seated thereon. A printed circuit board connected with the circuit pattern exposed from the inside of the dam to the outside; A semiconductor chip bonded with an adhesive while a plurality of input / output pads are formed inside a circuit pattern of the printed circuit board; In the semiconductor package comprising a conductive wire connecting the input / output pad of the semiconductor chip and the circuit pattern of the printed circuit board, the method for applying the circuit pattern, the conductive wire and the upper portion of the semiconductor chip with a liquid sealing material, The liquid encapsulation material is applied to only a circuit pattern of a printed circuit board and an upper surface of a semiconductor chip so that the liquid encapsulation material flows on the conductive wire and its lower portion by itself.

여기서 상기 인쇄회로기판의 회로패턴과 반도체칩의 상면에 액상봉지재를 도포하는 순서는 상기 회로패턴의 상면을 1차로 도포하고, 상기 반도체칩의 상면은 2차로 도포하거나 또는 상기 반도체칩의 상면을 1차로 도포하고, 상기 회로패턴의 상면은 2차로 도포하는 방법이 이용될 수 있다.The order of applying the liquid encapsulant to the circuit pattern of the printed circuit board and the upper surface of the semiconductor chip is to apply the upper surface of the circuit pattern firstly, and to apply the upper surface of the semiconductor chip to the second surface or the upper surface of the semiconductor chip. Applying primarily, and the upper surface of the circuit pattern may be applied in a secondary manner.

이하 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

먼저 도2a는 본 발명에 의한 반도체패키지용 액상봉지재(50)의 도포 방법을 도시한 평면도이고, 도2b은 본 발명에 의한 반도체패키지용 액상봉지재(50)의 도포방법의 작용 상태를 도시한 단면도이다.First, Figure 2a is a plan view showing a coating method of the semiconductor package liquid sealing material 50 according to the present invention, Figure 2b is a working state of the coating method of the semiconductor package liquid sealing material 50 according to the present invention. One cross section.

도시된 바와 같은 본 발명에 의한 도포 방법이 적용된 반도체패키지(100)의 구성을 간단히 설명하면 다음과 같다.The configuration of the semiconductor package 100 to which the coating method according to the present invention is applied will be described briefly as follows.

내측에는 액상봉지재(50)가 외측으로 넘쳐 흐르지 못하도록 댐(80)이 형성되어 있고, 상기 댐(80)의 외측에는 다수의 솔더볼이 안착될 수 있도록 솔더볼랜드(12)가 형성되어 있으며, 상기 솔더볼랜드(12)에 연결되어서는 회로패턴(11)이 댐(80)의 내측 하단에서 상부를 향하여 노출되어 있는 인쇄회로기판(10)이 구비되어 있다. 상기 인쇄회로기판(10)의 회로패턴(11) 내측에는 다수의 입/출력패드(31)가 형성된 채 접착제로 반도체칩(30)이 하단에 구비된 히트싱크(20)에 접착되어 있는데 상기 인쇄회로기판(10)도 마찬가지로 상기 히트싱크(20)에 접착되어 있다. 그리고 상기 반도체칩(30)의 입/출력패드(31)와 인쇄회로기판(10)의 회로패턴(11)은 전도성와이어(40)로 본딩되어 반도체패키지(100)가 준비되어 있다.A dam 80 is formed on the inside to prevent the liquid encapsulant 50 from overflowing to the outside, and a solder ball land 12 is formed on the outside of the dam 80 to allow a plurality of solder balls to be seated thereon. The printed circuit board 10 having the circuit pattern 11 exposed from the lower end of the dam 80 toward the upper part is provided to be connected to the solder borland 12. A plurality of input / output pads 31 are formed inside the circuit pattern 11 of the printed circuit board 10, and the semiconductor chip 30 is adhered to the heat sink 20 provided at the bottom with an adhesive. The circuit board 10 is likewise adhered to the heat sink 20. The input / output pad 31 of the semiconductor chip 30 and the circuit pattern 11 of the printed circuit board 10 are bonded to the conductive wire 40 to prepare the semiconductor package 100.

이러한 구성을 하는 반도체패키지(100)의 상부에 액상봉지재(50)를 도포하는 방법은 상기 액상봉지재(50)가 충진되어 있는 디스펜서(60)를 이용하여 인쇄회로기판(10)의 회로패턴(11)과 반도체칩(30)의 상면에 각각 도포하여 상기 전도성와이어(40) 및 그 하부에는 액상봉지재(50)가 스스로 흘러들어가게 하는 것이다.The method for applying the liquid encapsulation material 50 to the upper portion of the semiconductor package 100 having such a configuration is a circuit pattern of the printed circuit board 10 by using the dispenser 60 filled with the liquid encapsulation material 50. (11) and the upper surface of the semiconductor chip 30, respectively, so that the liquid sealing material 50 flows into the conductive wire 40 and the lower portion by itself.

즉, 상기 전도성와이어(40)의 상부에서는 액상봉지재(50)를 직접 도포하지 않고 그 양측면의 회로패턴(11)과 반도체칩(30) 상면에만 도포를 실시하여 자연스럽게 상기 전도성와이어(40) 쪽으로 액상봉지재(50)가 흘러들어가게 한 것이다.That is, the upper portion of the conductive wire 40 is not applied directly to the liquid encapsulation material 50, but only to the upper surface of the circuit pattern 11 and the semiconductor chip 30 on both sides thereof, and naturally toward the conductive wire 40. Liquid encapsulant 50 is to flow.

여기서 상기 인쇄회로기판(10)의 회로패턴(11)과 반도체칩(30)의 상면에 액상봉지재(50)를 도포하는 순서는 상기 회로패턴(11)의 상면에 1차로 도포를 실시하고, 이어서 상기 반도체칩(30)의 상면에 2차로 도포를 실시하거나 또는 상기 반도체칩(30)의 상면에 먼저 1차로 도포하고, 상기 회로패턴(11)에 2차로 도포할 수 있으며 그 순서에 제한이 있는 것은 아니다.Here, the order of applying the liquid encapsulant 50 to the circuit pattern 11 of the printed circuit board 10 and the upper surface of the semiconductor chip 30 is applied first to the upper surface of the circuit pattern 11, Subsequently, the upper surface of the semiconductor chip 30 may be applied secondly or the first surface may be firstly applied to the upper surface of the semiconductor chip 30, and the second application may be applied to the circuit pattern 11. It is not there.

이와 같은 방법의 작용 효과는 도2b에 도시된 바와 같이 인쇄회로기판(10)의 회로패턴(11)과 반도체칩(30)의 상면에만 액상봉지재(50)를 도포함으로써 액체성의 상기 액상봉지재(50)가 인쇄회로기판(10)과 반도체칩(30) 사이의 움푹 패인 부분으로 자연스럽게 흘러내려 가고 그럼으로써 공기가 모두 빠져나갈 시간을 제공함으로써 촘촘하게 연결된 전도성와이어(40) 주변 및 그 하부에 보이드가 형성되지 않는 것이다.As shown in FIG. 2B, the operation and effect of the method may be achieved by applying the liquid encapsulant 50 to only the upper surface of the circuit pattern 11 and the semiconductor chip 30 of the printed circuit board 10. 50 flows naturally into the recessed portion between the printed circuit board 10 and the semiconductor chip 30, thereby providing time for all air to escape and voids around and below the tightly coupled conductive wire 40 Is not formed.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며 본 발명의 범주와 사상을 벗어남에 없이 당업자에 의해 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, various modifications may be made by those skilled in the art without departing from the scope and spirit of the present invention.

즉, 본 발명은 상기 볼그리드러어레이반도체패키지를 중심으로 설명하였지만, 그 밖에 액상봉지재를 이용하여 도포 또는 봉지작업을 실시하는 모든 반도체패키지에도 본 발명에 의한 방법이 적용될 수 있다.That is, the present invention has been described based on the ball grid array semiconductor package, but the method according to the present invention can be applied to any semiconductor package that performs the coating or sealing operation using the liquid encapsulant.

따라서 본 발명에 의한 반도체패키지용 액상봉지재의 도포 방법에 의하면, 전도성와이어의 상면에는 직접 액상봉지재를 도포하지 않고 그 양측의 회로패턴 및 반도체칩의 상면에만 도포를 실시함으로써 액상봉지재가 자연스럽게 상기 전도성와이어 및 그 하부에 퍼지게 되어 보이드 발생을 최대한 억제할 수 있는 효과가 있다.Therefore, according to the method for applying the liquid encapsulant for a semiconductor package according to the present invention, the liquid encapsulant is naturally conductive by applying only to the upper surface of the circuit pattern and the semiconductor chip on both sides thereof without directly applying the liquid encapsulant to the upper surface of the conductive wire. Spread on the wire and its lower part has the effect of suppressing the generation of voids as much as possible.

Claims (3)

내측에는 액상봉지재가 외측으로 흘러가지 못하도록 댐이 형성되어 있고, 상기 댐의 외측에는 다수의 솔더볼이 안착될 수 있도록 솔더볼랜드가 형성되어 있으며, 상기 솔더볼랜드에 연결되어 회로패턴이 댐의 내측에서 외부로 노출되어 있는 인쇄회로기판과; 상기 인쇄회로기판의 회로패턴 내측에 다수의 입/출력패드가 형성된 채 접착제로 접착된 반도체칩과; 상기 반도체칩의 입/출력패드와 인쇄회로기판의 회로패턴을 연결하는 전도성와이어를 포함하여 이루어진 반도체패키지의 상면에서 상기 회로패턴, 전도성와이어 및 반도체칩의 상면에 액상봉지재를 도포하는 방법에 있어서,A dam is formed on the inside to prevent the liquid encapsulation material from flowing outward, and a solder ball land is formed on the outside of the dam to allow a plurality of solder balls to be seated, and a circuit pattern is connected to the solder ball land from the inside of the dam. A printed circuit board exposed to the substrate; A semiconductor chip bonded with an adhesive while a plurality of input / output pads are formed inside a circuit pattern of the printed circuit board; In the method of applying a liquid encapsulant to the circuit pattern, the conductive wire and the upper surface of the semiconductor chip on the upper surface of the semiconductor package comprising a conductive wire connecting the input / output pad of the semiconductor chip and the circuit pattern of the printed circuit board , 상기 액상봉지재를 인쇄회로기판의 회로패턴과 반도체칩의 상면에만 도포하여 상기 전도성와이어 및 그 하부에는 액상봉지재가 스스로 흘러들어가게 한 것을 특징으로 하는 반도체패키지용 액상봉지재의 도포 방법.And applying the liquid encapsulant only to the circuit pattern of the printed circuit board and the upper surface of the semiconductor chip so that the liquid encapsulation material flows into the conductive wire and the lower portion thereof. 제1항에 있어서, 상기 인쇄회로기판의 회로패턴과 반도체칩의 상면에 액상봉지재를 도포하는 순서는 상기 회로패턴의 상면에 1차 도포를 실시한후, 상기 반도체칩의 상면에 2차 도포를 실시하는 것을 특징으로 하는 반도체패키지용 액상봉지재의 도포 방법.The method of claim 1, wherein the liquid encapsulant is applied to the circuit pattern of the printed circuit board and the upper surface of the semiconductor chip by applying a first coating on the upper surface of the circuit pattern, and then applying a second coating on the upper surface of the semiconductor chip. The coating method of the liquid sealing material for semiconductor packages characterized by the above-mentioned. 제1항에 있어서, 상기 인쇄회로기판의 회로패턴과 반도체칩의 상면에 액상봉지재를 도포하는 순서는 상기 반도체칩의 상면에 1차 도포를 실시한후, 상기 회로패턴에 2차 도포를 실시하는 것을 특징으로 하는 반도체패키지용 액상봉지재의 도포 방법.The method of claim 1, wherein the liquid encapsulation material is applied to the circuit pattern of the printed circuit board and the upper surface of the semiconductor chip by applying the first coating on the upper surface of the semiconductor chip, and then applying the second coating on the circuit pattern. A method of applying a liquid encapsulant for a semiconductor package.
KR1019970064124A 1997-11-28 1997-11-28 Dispensing method of glob top for semiconductor package KR100251864B1 (en)

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