KR20020057699A - chip scale package(csp) manufactured by grinding process and method for fabricating the same - Google Patents

chip scale package(csp) manufactured by grinding process and method for fabricating the same Download PDF

Info

Publication number
KR20020057699A
KR20020057699A KR1020010000675A KR20010000675A KR20020057699A KR 20020057699 A KR20020057699 A KR 20020057699A KR 1020010000675 A KR1020010000675 A KR 1020010000675A KR 20010000675 A KR20010000675 A KR 20010000675A KR 20020057699 A KR20020057699 A KR 20020057699A
Authority
KR
South Korea
Prior art keywords
bump
bumps
csp
chip
manufactured
Prior art date
Application number
KR1020010000675A
Other languages
Korean (ko)
Inventor
서경민
홍종락
Original Assignee
박덕흥
에스티에스반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박덕흥, 에스티에스반도체통신 주식회사 filed Critical 박덕흥
Priority to KR1020010000675A priority Critical patent/KR20020057699A/en
Publication of KR20020057699A publication Critical patent/KR20020057699A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: A CSP(Chip Scale Package) manufactured by a polishing process is provided to reduce a size and a manufacturing cost and to simplify manufacturing processes by forming a semiconductor package having the same size of wafer level. CONSTITUTION: A CSP manufactured by a polishing process comprises a semiconductor chip(100) formed with bond pads(102), a plurality of bumps(104) respectively formed on the bond pads(102), an encapsulant(106B) having the same height with the bumps(104) enclosing the front surface of the semiconductor chip(100), a solder mask(108) enclosing the entire surface of the resultant structure, while exposing only the bumps(104), and a solder balls(110) respectively connected with the exposed bumps(104). At this point, the bumps(104) are formed without a die bonding, a wire bonding or an encapsulation process, thereby reducing the chip size.

Description

연마방식에 의해 제조된 씨. 에스. 피 패키지 및 그 제조방법{chip scale package(csp) manufactured by grinding process and method for fabricating the same}Seed manufactured by polishing method. s. Chip scale package (csp) manufactured by grinding process and method for fabricating the same}

본 발명은 반도체 소자에 관한 것으로, 더욱 상세하게는 씨. 에스. 피(CSP: Chip Scale Package, 이하 'CSP') 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly to Mr .. s. The present invention relates to a chip scale package (CSP), and a method of manufacturing the same.

전자 제품들이 점차 소형 경박화 됨에 따라, 전자제품을 구성하는 반도체 소자의 크기 역시 점차 소형 경박화되는 추세이다. 따라서 반도체 패키지의 발전 방향도 기존의 DIP(Dual In line Package), SO(Small Out line), QFP(Quad Flat Package) 형태에서, BGA(Ball Grid Array) 혹은 실제 칩(Chip)의 1.2배 이하 크기인 CSP쪽으로 개발이 급진전되고 있다.As electronic products are gradually miniaturized, the size of semiconductor devices constituting the electronic products is also gradually miniaturized. Therefore, the direction of development of semiconductor package is 1.2 times smaller than that of conventional ball grid array (BGA) or actual chip (DIP), small out line (SO), quad flat package (QFP). Development is moving forward toward CSP.

이렇게 진보된 형태의 BGA, CSP 패키지에서는 가급적 반도체 패키지의 크기를 소형화시키기 위해, 기존에 사용하던 리드(lead) 대신 솔더볼(solder ball)을 사용하고 패키지의 크기를 칩(chip) 정도의 크기까지 줄이기 위해 끊임없는 연구 개발이 진행되고 있다.In this advanced type of BGA and CSP package, in order to reduce the size of the semiconductor package as much as possible, use solder balls instead of the conventional lead and reduce the package size to the size of the chip. There is constant research and development going on.

상술한 진보된 형태의 반도체 패키지가운데, CSP 패키지의 제조방식은 반도체 칩을 폴리이미드(polyimide) 기판에 구리로 된 인쇄회로 패턴이 형성된 고형의 기판(rigid substrate)에 부착하여 패키징을 완료한 후, CSP 패키지를 단위 유닛(unit)으로 개별화(singulation)하는 공정을 통해 만들어진다.Among the above-described advanced types of semiconductor package, the manufacturing method of the CSP package is to attach the semiconductor chip to a solid substrate (printed circuit board) formed with a printed circuit pattern of copper on a polyimide substrate to complete the packaging, The CSP package is created through a process of singulating the unit into units.

그러나, 고형의 기판을 사용하는 종래 기술에 의한 CSP 패키지는 다음과 같은 문제점을 지니고 있다.However, the CSP package according to the prior art using a solid substrate has the following problems.

첫째, 고형의 기판을 사용하기 때문에 제조원가가 올라가고, CSP 제조공정이 복잡해진다.First, the use of solid substrates increases manufacturing costs and complicates the CSP manufacturing process.

둘째, 고형의 기판을 사용하기 때문에 반도체 패키지의 크기를 줄이는데 한계가 있다.Second, there is a limit to reducing the size of the semiconductor package because it uses a solid substrate.

본 발명이 이루고자 하는 기술적 과제는 웨이퍼 레벨(wafer level) 크기의 반도체 패키지를 구현함으로써 반도체 패키지의 크기를 줄이고, 제조비용을 줄이며, 제조공정을 단순화할 수 있는 연마방식에 의해 제조된 CSP 패키지를 제공하는데 있다.An object of the present invention is to provide a CSP package manufactured by a polishing method that can reduce the size of the semiconductor package, reduce the manufacturing cost, and simplify the manufacturing process by implementing a wafer level semiconductor package. It is.

본 발명이 이루고자 하는 다른 기술적 과제는 상기 연마방식에 의해 제조된 CSP 패키지의 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method for manufacturing a CSP package manufactured by the polishing method.

도 1 내지 도 7은 본 발명의 바람직한 실시예에 따른 연마방식에 의해 제조된 CSP 패키지의 제조방법 및 그 구조적 특징을 설명하기 위해 도시한 도면들이다.1 to 7 are diagrams for explaining the manufacturing method and the structural features of the CSP package produced by the polishing method according to a preferred embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100: 칩(chip), 102: 본드패드,100: chip, 102: bond pad,

104: 범프(bump), 106: 봉합수지(encapsulant),104: bump, 106: encapsulant,

108: 솔더마스크, 110: 솔더볼,108: solder mask, 110: solder balls,

112: 웨이퍼 고정용 링, 114: 웨이퍼 접착용 테이프.112: wafer fixing ring, 114: wafer bonding tape.

상기 기술적 과제를 달성하기 위하여 본 발명은, 본드패드가 형성되어 있는 반도체 칩과, 상기 본드패드 위에 형성된 복수개의 범프(bump)와, 상기 본드패드가 있는 반도체 칩의 표면을 덮으면서 두께가 상기 범프의 높이와 동일한 봉합 수지(encapsulant)와, 상기 범프만을 노출시켜면서 상기 봉합수지 전면을 덮는 솔더마스크와, 상기 솔더마스크에 의해 노출된 범프와 연결된 솔더볼을 구비하는 것을 특징으로 하는 연마방식에 의해 제조된 CSP 패키지를 제공한다.In order to achieve the above technical problem, the present invention provides a semiconductor chip including a bond pad, a plurality of bumps formed on the bond pad, and a thickness of the bump while covering a surface of the semiconductor chip with the bond pad. The encapsulant having the same height as that of, a solder mask covering the front surface of the sealing resin while exposing only the bump, and a solder ball connected to the bump exposed by the solder mask. The CSP package.

본 발명의 바람직한 실시예에 의하면, 상기 범프는 알루미늄을 포함하는 도전물질인 것이 적합하다.According to a preferred embodiment of the present invention, the bump is preferably a conductive material containing aluminum.

상기 다른 기술적 과제를 달성하기 위하여 본 발명은, 웨이퍼 상태에 있는 칩의 본드패드에 범프(bump)를 형성하는 공정과, 상기 범프가 형성된 웨이퍼에 액체상태의 봉합수지(encapsulant)를 상기 범프 높이 이상으로 코팅(coating)하는 공정과, 상기 범프의 표면이 노출되도록 상기 봉합수지를 일정두께로 연마(grinding)하는 공정과, 상기 범프의 표면이 노출되도록 상기 봉합수지 위에 솔더마스크를 형성하는 공정과, 상기 노출된 범프에 솔더볼을 부착하는 공정 및 상기 솔더볼 부착이 완료된 웨이퍼를 블레이드(blade)로 개별화(singulation)하는 공정을 구비하는것을 특징으로 하는 연마방식에 의해 제조된 CSP 패키지 제조방법을 제공한다.In order to achieve the above technical problem, the present invention provides a process of forming a bump on a bond pad of a chip in a wafer state, and a liquid encapsulant on the wafer on which the bump is formed, the bump height or more. Coating (coating), grinding the sealing resin to a predetermined thickness so that the surface of the bump is exposed, forming a solder mask on the sealing resin so that the surface of the bump is exposed, And a process of attaching solder balls to the exposed bumps and a process of singulating the wafers on which the solder balls are attached to each other by blades, thereby manufacturing a CSP package manufactured by a polishing method.

또한, 본 발명의 바람직한 실시예에 의하면, 상기 개별화 공정(singulation process)이 완료된 후, 상기 솔더볼이 부착되지 않은 칩의 밑면에 레이저(LASER)를 이용한 마킹(marking)을 수행하는 공정을 더 진행하는 것이 적합하다.In addition, according to a preferred embodiment of the present invention, after the singulation process (singulation process) is completed, the process of performing a marking (marking) using a laser (LASER) on the bottom surface of the chip not attached to the solder ball Is suitable.

본 발명에 따르면, CSP 패키지의 제조원가중 많은 부분을 차지하는 고형의 기판을 사용하지 않고도 CSP 패키지를 만들 수 있기 때문에 제조원가를 줄일 수 있으며, 고형의 기판을 캐리어(carrier)에 부착하는 공정을 비롯하여 이를 취급하는 공정등을 생략할 수 있기 때문에 제조공정을 단순화 할 수 있으며, 웨이퍼에 있는 실제 단위 칩의 크기와 동일한 크기를 갖는 CSP 패키지를 제조할 수 있기 때문에 반도체 패키지의 크기를 경박 단소화시킬 수 있다.According to the present invention, since the CSP package can be made without using a solid substrate that takes up a large part of the manufacturing cost of the CSP package, the manufacturing cost can be reduced, and the process of attaching the solid substrate to a carrier is handled. Since the process can be omitted, the manufacturing process can be simplified, and since the CSP package having the same size as that of the actual unit chip on the wafer can be manufactured, the size of the semiconductor package can be made light and small.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

그러나, 아래의 상세한 설명에서 개시되는 실시예는 본 발명을 한정하려는 의미가 아니라, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자에게, 본 발명의 개시가 실시 가능한 형태로 완전해지도록 발명의 범주를 알려주기 위해 제공되는 것이다. 본 발명은 그 정신의 특징사항으로부터 이탈하지 않고 다른 방식으로 실시할 수 있다. 예를 들면, 아래의 바람직한 실시예에 있어서는 범프의 크기가 본드패드보다 작지만, 이는 솔더마스크에 의해 노출되는 범프의 크기가 본드패드와 같거나, 혹은 더 커도 무방하다. 따라서, 아래의 바람직한 실시예에서 기재한 내용은 예시적인 것이며 본 발명을 한정하는 의미가 아니다.However, the embodiments disclosed in the following detailed description are not meant to limit the present invention, but to those skilled in the art to which the present invention pertains, the disclosure of the present invention may be completed in a form that can be implemented. It is provided to inform the category. The present invention can be practiced in other ways without departing from the spirit features. For example, in the following preferred embodiment, the bumps are smaller than the bond pads, but the bumps exposed by the solder mask may be equal to or larger than the bond pads. Therefore, the contents described in the following preferred embodiments are exemplary and are not meant to limit the present invention.

도 1 내지 도 7은 본 발명의 바람직한 실시예에 따른 CSP 패키지의 제조방법 및 그 구조적 특징을 설명하기 위해 도시한 도면들이다.1 to 7 are diagrams for explaining the manufacturing method and the structural features of the CSP package according to an embodiment of the present invention.

먼저, 도 6을 참조하여 본 발명의 바람직한 실시예에 의한 CSP 패키지의 구성요소 및 구조적 특징을 설명하기로 한다.First, the components and structural features of the CSP package according to the preferred embodiment of the present invention will be described with reference to FIG. 6.

본 발명에 따른, 연마방식에 의해 제조된 CSP 패키지의 구성은, ① 본드패드(102)가 형성되어 있는 반도체 칩(100), ② 상기 본드패드(102) 위에 형성된 복수개의 범프(104)), ③ 상기 본드패드(102)가 있는 반도체 칩(100)의 표면을 덮으면서 두께가 상기 범프의 높이와 동일한 봉합 수지(encapsulant, 106B), ④ 상기 범프(104)만을 노출시켜면서 상기 봉합수지(106B) 전면을 덮는 솔더마스크(108), ⑤ 상기 솔더마스크(108)에 의해 노출된 범프(104)와 연결된 솔더볼(110)로 이루어진다.The structure of the CSP package manufactured by the polishing method according to the present invention includes (1) a semiconductor chip (100) on which bond pads (102) are formed, (2) a plurality of bumps (104) formed on the bond pads (102), (3) an encapsulant (106B) having a thickness equal to that of the bump while covering the surface of the semiconductor chip (100) with the bond pad (102), (4) exposing only the bump (104) and the suture resin (106B). A solder mask 108 covering the entire surface, ⑤ is made of a solder ball 110 connected to the bump 104 exposed by the solder mask 108.

본 발명에 의한 연마방식에 의해 제조된 CSP 패키지의 구조적 특징은, 별도의 와이어 본딩(wire bonding), 다이본딩(die bonding), 몰딩공정(encapsulation process)을 진행하지 않고, 웨이퍼 상태에서 범프(104)를 형성하고, 봉합수지(106B)를 코딩한 후, 연마(grinding)로 상기 범프(104)를 노출시킨 구조에 있다. 따라서, 간단한 공정만으로 본드패드(102)와 연결된 외부연결단자, 즉 솔더볼(solder ball)을 부착할 수 있고, 이로 말미암아 CSP 패키지의 제조단가를 낮추면, 제조공정을 단순화시키며, 그 크기를 실제 반도체 칩의 크기로 축소시킬 수 있다.Structural features of the CSP package manufactured by the polishing method according to the present invention, bumps in the wafer state without a separate wire bonding (die bonding), die bonding (die bonding), molding process (encapsulation process) ), The sealing resin 106B is coded, and the bump 104 is exposed by grinding. Therefore, an external connection terminal connected to the bond pad 102, that is, a solder ball, can be attached by a simple process, thereby lowering the manufacturing cost of the CSP package, simplifying the manufacturing process, and reducing the size of the actual semiconductor chip. Can be reduced to the size of.

이하, 도 1 내지 도 6을 참조하여 본 발명의 바람직한 실시예에 의한 연마방식에 의해 제조된 CSP 패키지의 제조방법에 관해 설명한다.Hereinafter, a method of manufacturing a CSP package manufactured by a polishing method according to a preferred embodiment of the present invention will be described with reference to FIGS. 1 to 6.

도 1 내지 도 3을 참조하면, 도 1은 웨이퍼 상태에 있는 단위 반도체 칩(100)의 단면으로써, 그 상부에는 패시베이션층(passivation layer, 미도시)을 포함한 본드패드(bondpad, 102)가 형성되어 있다. 이어서, 상기 본드패드(102)가 형성된 반도체 칩에 범프(104)를 형성하되, 각각 일정한 높이를 갖도록 형성한다. 상기 범프(104)는 본드패드(102) 위에서 형성이 용이하며, 솔더볼(도6 110)의 부착이 용이한 재질이면 어느 것이나 사용이 가능하지만, 알루미늄을 포함하는 합금을 재질로 하는 것이 적당하다.1 to 3, FIG. 1 is a cross-sectional view of a unit semiconductor chip 100 in a wafer state, and a bond pad 102 including a passivation layer (not shown) is formed thereon. have. Subsequently, bumps 104 are formed on the semiconductor chip on which the bond pads 102 are formed, respectively, to have a predetermined height. The bumps 104 may be formed on the bond pads 102 and may be used as long as the solder balls (FIG. 6 110) can be easily attached. However, the bumps 104 may be formed of an alloy including aluminum.

그 후, 상기 범프(104)가 형성된 웨이퍼, 즉 반도체 칩(100) 위에 봉합수지(encapsulant, 106A)를 상기 범프(104)의 형성 높이 이상으로 코팅(coating)한다. 상기 봉합수지(106A)는, 고신뢰성인 액상의 에폭시(epoxy)를 코팅후 경화시켜 형성할 수도 있고, 다른 방법으로 세라믹(Ceramic), 플라스틱(plastic) 및 엘라스토머(elastomer)중에서 선택된 어느 하나의 물질이 액상의 에폭시에 포함된 물질을 코팅한 후, 이를 경화시켜 형성할 수 있다.Thereafter, an encapsulant 106A is coated on the wafer on which the bump 104 is formed, that is, the semiconductor chip 100, above the forming height of the bump 104. The suture resin 106A may be formed by coating and curing a highly reliable liquid epoxy and alternatively, any one material selected from ceramic, plastic, and elastomer may be used. After coating a material contained in the liquid epoxy, it may be formed by curing.

도 4 내지 도 7을 참조하면, 상기 봉합수지(106A)를 그라인딩(grinding) 방식으로 평탄화시켜, 상기 범프(104)의 표면이 노출되도록 한다. 이어서, 상기 범프(104) 표면이 그대로 노출된 상태가 되도록 상기 봉합수지(106B) 위에 절연물질로 된 솔더마스크(108)를 형성한다. 이어서, 리플로우 오븐(reflow oven)을 이용하여 상기 범프(104) 표면에 솔더볼(110)을 부착한다. 마지막으로 솔더볼(110) 부착이 끝난 웨이퍼(도7의 101)를 웨이퍼 고정용 링(Ring, 112)과 웨이퍼 접착용 테이프(Tape, 114) 및 블레이드(blade)를 이용하여 개별화(singulation)시킨다.4 to 7, the suture resin 106A is planarized by a grinding method so that the surface of the bump 104 is exposed. Subsequently, a solder mask 108 made of an insulating material is formed on the sealing resin 106B so that the surface of the bump 104 is exposed as it is. Subsequently, the solder ball 110 is attached to the bump 104 surface using a reflow oven. Finally, the wafer (101 in FIG. 7) having the solder ball 110 attached thereto is singulated using a wafer fixing ring (Ring) 112, a wafer adhesive tape (Tape) 114, and a blade.

마지막으로, 상기 개별화가 완료된 CSP 패키지에 대하여 솔더볼(110)이 부착되지 않은 반도체 칩(100)의 밑면에 레이저(LASER)를 이용한 마킹(marking)을 실시하여 제품의 식별이 가능하도록 한다.Finally, marking of the CSP package in which the individualization is completed is performed by marking the bottom surface of the semiconductor chip 100 to which the solder ball 110 is not attached by using a laser.

본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

따라서, 상술한 본 발명에 따르면, 첫째, CSP 패키지의 원가중 많은 부분을 차지하는 고형의 기판을 사용하지 않고도 CSP 패키지를 만들 수 있기 때문에 제조원가를 줄일 수 있다.Therefore, according to the present invention described above, first, the manufacturing cost can be reduced because the CSP package can be made without using a solid substrate that takes up a large portion of the cost of the CSP package.

둘째, 고형의 기판을 캐리어(carrier)에 부착하는 공정을 비롯하여 이를 취급하는 공정등을 줄일 수 있기 때문에 제조공정을 단순화 할 수 있다.Second, the manufacturing process can be simplified because the process of attaching a solid substrate to a carrier and the process of handling the same can be reduced.

셋째, 웨이퍼에 있는 실제 칩의 크기와 동일한 크기를 갖는 CSP 패키지를 구현할 수 있기 때문에 반도체 패키지의 크기를 경박 단소화시킬 수 있다.Third, since the CSP package having the same size as the actual chip on the wafer can be implemented, the size of the semiconductor package can be made light and small.

Claims (4)

본드패드가 형성되어 있는 반도체 칩;A semiconductor chip in which bond pads are formed; 상기 본드패드 위에 형성된 복수개의 범프(bump);A plurality of bumps formed on the bond pads; 상기 본드패드가 있는 반도체 칩의 표면을 덮으면서 두께가 상기 범프의 높이와 동일한 봉합 수지(encapsulant);An encapsulant having a thickness equal to that of the bump while covering the surface of the semiconductor chip with the bond pad; 상기 범프만을 노출시켜면서 상기 봉합수지 전면을 덮는 솔더마스크;A solder mask covering the entire surface of the sealing resin while exposing only the bumps; 상기 솔더마스크에 의해 노출된 범프와 연결된 솔더볼을 구비하는 것을 특징으로 하는 연마방식에 의해 제조된 CSP 패키지.And a solder ball connected to the bump exposed by the solder mask. 제1항에 있어서,The method of claim 1, 상기 범프는 알루미늄을 포함하는 도전물질인 것을 특징으로 하는 연마방식에 의해 제조된 CSP 패키지.The bump is a CSP package manufactured by a polishing method, characterized in that the conductive material containing aluminum. 웨이퍼 상태에 있는 칩의 본드패드에 범프(bump)를 형성하는 공정;Forming a bump on a bond pad of a chip in a wafer state; 상기 범프가 형성된 웨이퍼에 액체상태의 봉합수지(encapsulant)를 상기 범프 높이 이상으로 코팅(coating)하는 공정;Coating a liquid encapsulant on the bump-formed wafer above the bump height; 상기 범프의 표면이 노출되도록 상기 봉합수지를 일정두께로 연마(grinding)하는 공정;Grinding the suture resin to a predetermined thickness so that the surface of the bump is exposed; 상기 범프의 표면이 노출되도록 상기 봉합수지 위에 솔더마스크를 형성하는 공정;Forming a solder mask on the sealing resin to expose the surface of the bumps; 상기 노출된 범프에 솔더볼을 부착하는 공정; 및Attaching solder balls to the exposed bumps; And 상기 솔더볼 부착이 완료된 웨이퍼를 블레이드(blade)로 개별화(singulation)하는 공정을 구비하는 것을 특징으로 하는 연마방식에 의해 제조된 CSP 패키지 제조방법.And a step of singulating the wafer on which the solder ball attachment is completed by a blade. 제1항에 있어서,The method of claim 1, 상기 개별화 공정이 완료된 후, 상기 솔더볼이 부착되지 않은 칩의 밑면에 레이저를 이용한 마킹을 수행하는 공정을 더 진행하는 것을 특징으로 하는 연마방식에 의해 제조된 CSP 패키지 제조방법.After the individualization process is completed, the CSP package manufacturing method manufactured by a polishing method, characterized in that further performing the process of performing a marking using a laser on the bottom surface of the chip is not attached to the solder ball.
KR1020010000675A 2001-01-05 2001-01-05 chip scale package(csp) manufactured by grinding process and method for fabricating the same KR20020057699A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010000675A KR20020057699A (en) 2001-01-05 2001-01-05 chip scale package(csp) manufactured by grinding process and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010000675A KR20020057699A (en) 2001-01-05 2001-01-05 chip scale package(csp) manufactured by grinding process and method for fabricating the same

Publications (1)

Publication Number Publication Date
KR20020057699A true KR20020057699A (en) 2002-07-12

Family

ID=27690918

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010000675A KR20020057699A (en) 2001-01-05 2001-01-05 chip scale package(csp) manufactured by grinding process and method for fabricating the same

Country Status (1)

Country Link
KR (1) KR20020057699A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8836054B2 (en) 2010-12-17 2014-09-16 SK Hynix Inc. Semiconductor chip capable of improving mounting reliability and semiconductor package having the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172036A (en) * 1995-12-19 1997-06-30 Toshiba Corp Manufacturing method for semiconductor package device
KR100192759B1 (en) * 1996-03-11 1999-06-15 황인길 Method of manufacturing bump for bump chip scale package
KR100192758B1 (en) * 1996-03-11 1999-06-15 황인길 Method of manufacturing semiconductor package and structure of the same
JP2000031191A (en) * 1998-07-15 2000-01-28 Mitsui High Tec Inc Semiconductor device
US6153448A (en) * 1997-05-14 2000-11-28 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09172036A (en) * 1995-12-19 1997-06-30 Toshiba Corp Manufacturing method for semiconductor package device
KR100192759B1 (en) * 1996-03-11 1999-06-15 황인길 Method of manufacturing bump for bump chip scale package
KR100192758B1 (en) * 1996-03-11 1999-06-15 황인길 Method of manufacturing semiconductor package and structure of the same
US6153448A (en) * 1997-05-14 2000-11-28 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method
JP2000031191A (en) * 1998-07-15 2000-01-28 Mitsui High Tec Inc Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8836054B2 (en) 2010-12-17 2014-09-16 SK Hynix Inc. Semiconductor chip capable of improving mounting reliability and semiconductor package having the same

Similar Documents

Publication Publication Date Title
US7211466B2 (en) Stacked die semiconductor device
US8546184B2 (en) Package substrate having die pad with outer raised portion and interior recessed portion
KR20050071637A (en) Optical sensor package
US7846773B2 (en) Multi-chip semiconductor package
US6245598B1 (en) Method for wire bonding a chip to a substrate with recessed bond pads and devices formed
US20040188818A1 (en) Multi-chips module package
US7087459B2 (en) Method for packaging a multi-chip module of a semiconductor device
US6284566B1 (en) Chip scale package and method for manufacture thereof
US6150730A (en) Chip-scale semiconductor package
US6772510B1 (en) Mapable tape apply for LOC and BOC packages
US20100127380A1 (en) Leadframe free leadless array semiconductor packages
KR20020057699A (en) chip scale package(csp) manufactured by grinding process and method for fabricating the same
US7042078B2 (en) Semiconductor package
KR100390453B1 (en) semiconductor package with such circuit board and method for fabricating the same
KR100473336B1 (en) semiconductor package
KR100444175B1 (en) ball grid array of stack chip package
KR20050106665A (en) Semiconductor package and manufacturing method preventing a package crack defects)
KR100237329B1 (en) The structure of chip scale semiconductor package and method of manufacturing the same
KR100215118B1 (en) Manufacturing method of csp package
CN116741649A (en) Semiconductor packaging method and packaging structure
KR100542671B1 (en) Semiconductor package and its manufacturing method
KR200162892Y1 (en) Ball grid array package
KR20040060123A (en) Method for packaging semiconductor device
KR20020049821A (en) chip scale semiconductor package in wafer level and method for fabricating the same
KR19990059030A (en) Ball Grid Array Semiconductor Package Using Flexible Circuit Board

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application