KR20060010464A - Method for molding in fbga package - Google Patents

Method for molding in fbga package Download PDF

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KR20060010464A
KR20060010464A KR1020040059179A KR20040059179A KR20060010464A KR 20060010464 A KR20060010464 A KR 20060010464A KR 1020040059179 A KR1020040059179 A KR 1020040059179A KR 20040059179 A KR20040059179 A KR 20040059179A KR 20060010464 A KR20060010464 A KR 20060010464A
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substrate
window
semiconductor chip
emc
mold
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KR1020040059179A
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Korean (ko)
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현성호
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주식회사 하이닉스반도체
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Publication of KR20060010464A publication Critical patent/KR20060010464A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 발명은 기판의 상측으로 주입된 EMC가 기판의 윈도우를 통해 기판의 하측으로 유입되는 것을 방지하기 위한 FBGA 패키지의 몰딩방법을 개시한다. 개시된 본 발명은 본딩패드를 구비한 반도체 칩이 회로패턴과 중앙에 윈도우를 구비한 기판 상에 페이스-다운 형태로 부착되고, 상기 기판에 구비된 윈도우를 관통하여 상기 반도체 칩의 본딩 패드와 상기 기판의 회로패턴간을 와이어 본딩한 결과물을 하부 몰드 캡 형성을 위한 홈을 구비한 하부금형에 로딩시키는 단계와, 상기 기판 상측에 EMC(Epoxy Molding Compound) 충진 공간이 만들어지도록 하부금형 상에 상부금형을 배치시킨 상태로 금형의 일측에서 기판의 상측과 하측으로 EMC를 주입하는 단계를 포함하며, 상기 기판의 윈도우는 기판의 상측으로 주입된 EMC가 기판의 윈도우를 통해 기판의 하측으로 유입되는 것을 방지하기 위해, 상기 반도체 칩에 의해 가려지도록 반도체 칩보다 작은 크기로 구비된다. The present invention discloses a method of molding an FBGA package to prevent the EMC injected into the upper side of the substrate from flowing into the lower side of the substrate through the window of the substrate. According to the present invention, a semiconductor chip having a bonding pad is attached in a face-down manner on a circuit pattern and a substrate having a window in the center, and penetrates through a window provided in the substrate to bond the pad and the substrate of the semiconductor chip. Loading the result of wire bonding between the circuit patterns of the lower mold with grooves for forming the lower mold cap, and forming the upper mold on the lower mold to form an epoxy molding compound (EMC) filling space above the substrate. And injecting EMC from one side of the mold into the upper side and the lower side of the mold, wherein the window of the substrate prevents the EMC injected into the upper side of the substrate from flowing into the lower side of the substrate through the window of the substrate. In order to be covered by the semiconductor chip, it is provided with a smaller size than the semiconductor chip.

Description

ＦＢＧＡ 패키지의 몰딩방법{Method for molding in FBGA package}Method for molding in FBGA package

도 1은 페이스-다운 타입 FBGA 패키지를 도시한 단면도. 1 is a cross-sectional view illustrating a face-down type FBGA package.

도 2 및 도 3은 종래의 FBGA 패키지의 몰딩방법을 설명하기 위한 도면. 2 and 3 are views for explaining a molding method of a conventional FBGA package.

도 4 및 도 5는 본 발명에 따른 FBGA 패키지의 몰딩방법을 설명하기 위한 도면.4 and 5 are views for explaining a molding method of the FBGA package according to the present invention.

- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-

1, 21, 31, 41 : 기판 2, 22, 32, 42 : 반도체 칩1, 21, 31, 41: substrate 2, 22, 32, 42: semiconductor chip

3, 23, 33, 43 : 윈도우 4 : 접착제3, 23, 33, 43: Windows 4: Adhesive

5 : 본딩패드 6 : EMC 5: bonding pad 6: EMC

7 : 회로패턴 8 : 솔더 볼7: circuit pattern 8: solder ball

9 : 본딩와이어 45 : 상부금형9: bonding wire 45: upper mold

46 : 하부금형 47 : 에어벤트 46: lower mold 47: air vent

본 발명은 반도체 패키지의 제조방법에 관한 것으로, 보다 상세하게는, 기판의 상측으로 주입된 EMC가 기판의 윈도우를 통해 기판의 하측으로 유입되는 것을 방지하기 위한 FBGA 패키지의 몰딩방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor package, and more particularly, to a method of molding an FBGA package for preventing the EMC injected into the upper side of the substrate to flow into the lower side of the substrate through the window of the substrate.

최근, 전자 기기는 소형화, 경량화, 고속화, 다기능화 추세에 있고, 이를 실현하기 위한 일환으로 개발된 반도체 칩 패키지의 기술로서 볼 그리드 어레이(Ball Grid Array : 이하, BGA) 패키지가 있다. Recently, electronic devices have become smaller, lighter, faster, and more versatile, and a ball grid array (BGA) package is a technology of a semiconductor chip package developed as a part of realizing this.

이러한 BGA 패키지는 플라스틱 패키지와는 달리 리드 프레임 대신에 회로 기판을 사용하는데, 상기 회로 기판을 사용함으로써 반도체 칩이 부착되는 면의 반대쪽 면에 솔더 볼들을 배치할 수 있는 영역이 제공된다. 때문에, 실장 밀도 측면에서 매우 유리하다. 또한, 상기 BGA 패키지는 솔더 볼에 의해 외부 회로와의 전지적 연결이 이루어지므로 전기적 신호 전달 경로의 최소화를 통해 향상된 전기적 특성을 갖는다. Unlike a plastic package, such a BGA package uses a circuit board instead of a lead frame, and the circuit board provides an area in which solder balls can be disposed on the opposite side to which the semiconductor chip is attached. This is very advantageous in terms of mounting density. In addition, since the BGA package is connected to the external circuit by solder balls, the BGA package has improved electrical characteristics through minimization of an electrical signal transmission path.

아울러, 실장 밀도를 높이기 위한 형태로서 최근에 개발된 반도체 패키지로서는 FBGA(Fine-pitch Ball Grid Array) 패키지가 있다.In addition, as a form for increasing the mounting density, a recently developed semiconductor package includes a fine-pitch ball grid array (FBGA) package.

이하에서는 도 1을 참조하여 FBGA 패키지에 대하여 설명하도록 한다.Hereinafter, the FBGA package will be described with reference to FIG. 1.

도 1은 페이스-다운(face-down) 타입 FBGA 패키지의 단면을 도시한 것으로서, 도시된 바와 같이, 본딩패드(5)가 구비된 반도체 칩(2)이 회로패턴(7)과 중앙에 윈도우(3)가 구비된 기판(1) 상에 접착제(4)를 매개로 하여 페이스-다운 타입으로 부착되어 있다. FIG. 1 is a cross-sectional view of a face-down type FBGA package. As shown, a semiconductor chip 2 having a bonding pad 5 is provided with a circuit pattern 7 and a window in the center thereof. It is attached to the board | substrate 1 with which 3) was provided by the adhesive agent 4 in the face-down type.

또한, 기판(1)의 회로패턴(7)과 반도체 칩(2)의 본딩패드(5)는 기판(1)의 윈도우(3)를 관통한 본딩와이어(9)에 의해 상호 연결되어 있다. 그리고, 반도체 칩 (2)을 포함한 기판(1)의 상부면과 본딩와이어(9)를 포함한 기판(1)의 윈도우(3)는 EMC(Epoxy Molding Compound, 6)로 몰딩되어 있으며, 기판(1) 회로패턴(7)의 볼 랜드에는 솔더 볼(8)이 부착되어 있다. In addition, the circuit pattern 7 of the substrate 1 and the bonding pads 5 of the semiconductor chip 2 are connected to each other by a bonding wire 9 penetrating through the window 3 of the substrate 1. In addition, the upper surface of the substrate 1 including the semiconductor chip 2 and the window 3 of the substrate 1 including the bonding wire 9 are molded with an epoxy molding compound (EMC) 6. The solder ball 8 is attached to the ball land of the circuit pattern 7.

이와 같은 구조의 FBGA 패키지를 제조함에 있어서, 몰딩 공정은 먼저, 반도체 칩이 중앙에 윈도우를 구비한 기판 상에 부착한 후, 기판에 구비된 윈도우를 통해 반도체 칩과 기판을 와이어 본딩한 결과물을 하부금형에 로딩시킨다. 그런 다음, 상기 결과물 상측에 EMC 충진 공간이 만들어지도록 하부금형 상에 상부금형을 배치시킨 상태로 금형의 일측에서 기판의 상측과 하측으로 EMC를 주입하는 방식으로 진행한다. In manufacturing the FBGA package having the above structure, the molding process first attaches the semiconductor chip on the substrate having a window in the center, and then wires the semiconductor chip and the substrate through the window provided in the substrate. Load into the mold. Then, the EMC is injected into the upper side and the lower side of the substrate from one side of the mold with the upper mold disposed on the lower mold so that the EMC filling space is formed above the resultant.

그러나, 전술한 종래의 방법은 기판의 상측으로 주입된 EMC가 기판의 하측으로 유입될 수 있으며, 이렇게 유입된 EMC는 본딩와이어를 손상시킬 수 있다. However, in the conventional method described above, the EMC injected into the upper side of the substrate may flow into the lower side of the substrate, and the introduced EMC may damage the bonding wire.

자세하게, 도 2에 도시된 바와 같이, 기판(21)에 부착된 반도체 칩(22)은 윈도우(23)의 일측과 타측 부분(A, B)을 노출시키고, 이렇게 노출된 윈도우 부분(A, B)을 통해 기판(21)의 상측으로 주입된 EMC가 기판(21)의 하측으로 유입될 수 있으며, 유입된 EMC는 본딩와이어를 손상시킨다. In detail, as shown in FIG. 2, the semiconductor chip 22 attached to the substrate 21 exposes one side and the other side portions A and B of the window 23, and thus exposes the exposed window portions A and B. EMC injected into the upper side of the substrate 21 may be introduced into the lower side of the substrate 21, and the introduced EMC damages the bonding wire.

이에, 도 3에 도시된 바와 같이, 반도체 칩(22)이 기판(31)에 구비된 윈도우 (33)의 일측 부분(C)만을 노출시키도록 하여 몰딩하는 방법이 대한민국 특허출원번호 2004-29570로 출원되었다. Accordingly, as shown in FIG. 3, the method of molding the semiconductor chip 22 to expose only one side C of the window 33 provided on the substrate 31 is disclosed in Korean Patent Application No. 2004-29570. Filed.

그러나, 이러한 몰딩방법 또한, 노출된 윈도우의 일측 부분(C)에서 여전히 기판(31)의 상측으로 주입된 EMC가 기판(31)의 하측으로 유입되어 전자의 몰딩방법과 마찬가지로 본딩와이어를 손상시킨다. However, such a molding method also, EMC is injected into the upper side of the substrate 31 in one side portion (C) of the exposed window flows into the lower side of the substrate 31 to damage the bonding wires as in the former molding method.

따라서, 본 발명은 전술한 종래의 문제를 해결하기 위해 제안된 것으로서, 기판의 상측으로 주입된 EMC가 기판의 윈도우를 통해 기판의 하측으로 유입되는 것을 방지할 수 있는 FBGA 패키지의 몰딩방법을 제공함에 그 목적이 있다. Accordingly, the present invention has been proposed to solve the above-mentioned conventional problem, and provides a molding method of an FBGA package which can prevent the EMC injected into the upper side of the substrate from flowing into the lower side of the substrate through the window of the substrate. The purpose is.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 본딩패드를 구비한 반도체 칩이 회로패턴과 중앙에 윈도우를 구비한 기판 상에 페이스-다운 형태로 부착되고, 상기 기판에 구비된 윈도우를 관통하여 상기 반도체 칩의 본딩 패드와 상기 기판의 회로패턴 간을 와이어 본딩한 결과물을 하부 몰드 캡 형성을 위한 홈을 구비한 하부금형에 로딩시키는 단계와; 상기 기판 상측에 EMC(Epoxy Molding Compound) 충진 공간이 만들어지도록 하부금형 상에 상부금형을 배치시킨 상태로 금형의 일측에서 기판의 상측과 하측으로 EMC를 주입하는 단계를 포함하며, 상기 기판의 윈도우는 기판의 상측으로 주입된 EMC가 기판의 윈도우를 통해 기판의 하측으로 유입되는 것을 방지하기 위해, 상기 반도체 칩에 의해 가려지도록 반도체 칩보다 작은 크기로 구비되는 것을 특징으로 하는 FBGA 패키지의 몰딩방법을 제공한다. In order to achieve the above object, the present invention, a semiconductor chip having a bonding pad is attached in a face-down form on a circuit pattern and a substrate having a window in the center, and penetrates the window provided in the substrate Loading the result of wire bonding between the bonding pad of the semiconductor chip and the circuit pattern of the substrate to a lower mold having a groove for forming a lower mold cap; And injecting EMC from one side of the mold to the upper side and the lower side of the mold while the upper mold is disposed on the lower mold such that an epoxy molding compound (EMC) filling space is formed on the upper side of the substrate. In order to prevent the EMC injected into the upper side of the substrate from flowing into the lower side of the substrate through the window of the substrate, to provide a molding method of the FBGA package, characterized in that it is provided with a smaller size than the semiconductor chip to be covered by the semiconductor chip. do.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 4 및 도 5는 본 발명의 실시예에 따른 FBGA 패키지의 몰딩방법을 설명하기 위한 도면들이다. 4 and 5 are views for explaining a molding method of the FBGA package according to an embodiment of the present invention.                     

도시된 바와 같이, 본딩패드가 구비된 센터패드형의 반도체 칩(42)이 접착제(44)를 매개로 하여 회로패턴과 중앙에 윈도우(43)가 구비된 기판(41) 상에 페이스-다운 타입으로 부착한다. 여기서, 기판(41)에 구비된 윈도우(43)는 기판 (41) 상에 부착한 반도체 칩(42)의 크기와 동일하거나 작은 크기로 구비되도록 하고, 기판(41) 상에 부착한 반도체 칩(42)에 의해 윈도우(43)의 전 영역이 가려지도록 한다. As shown, a center pad-type semiconductor chip 42 with bonding pads is face-down on a substrate 41 with a circuit pattern and a window 43 in the center via the adhesive 44. Attach it. Here, the window 43 provided on the substrate 41 may be provided with a size equal to or smaller than that of the semiconductor chip 42 attached to the substrate 41, and the semiconductor chip attached to the substrate 41 may be provided. 42, the entire area of the window 43 is covered.

그런 다음, 기판(41)에 구비된 윈도우(43)를 관통하여 반도체 칩(42)의 본딩패드와 기판(41)의 회로패턴을 와이어 본딩하고, 이러한 와이어 본딩된 결과물을 하부 몰드 캡 형성을 위한 홈을 구비한 하부금형(46)에 로딩시킨다. Then, the wire pad is bonded to the bonding pad of the semiconductor chip 42 and the circuit pattern of the substrate 41 by penetrating through the window 43 provided on the substrate 41, and the wire bonded result is formed to form a lower mold cap. The lower mold 46 is provided with a groove.

그리고 나서, 기판(41) 상측에 EMC 충진 공간이 만들어지도록 하부금형(46) 상에 상부금형(45)을 배치시킨 상태로 금형의 일측에서 기판(41)의 상측과 하측으로 EMC를 주입한다. 주입된 EMC는 기판(41)의 상측과 하측을 동시에 충진하며, 또한, 기판(41)의 상측과 하측에 존재하는 공기는 금형의 타측에 구비된 에어벤트 (air vent)로 빠져나가게 한다. Then, EMC is injected into the upper side and the lower side of the substrate 41 from one side of the mold in a state where the upper mold 45 is disposed on the lower mold 46 so as to form an EMC filling space above the substrate 41. The injected EMC simultaneously fills the upper side and the lower side of the substrate 41, and also allows the air present at the upper side and the lower side of the substrate 41 to escape to the air vent provided at the other side of the mold.

이때, 기판(41)의 하측에 주입된 EMC는 윈도우(43)를 포함한 기판(41)의 하부면만을 밀봉하고, 기판(41)의 상측에 주입된 EMC는 반도체 칩(42)을 포함한 기판 (41)의 상부면을 밀봉하여 FBGA 패키지의 몰딩을 진행한다. At this time, the EMC injected below the substrate 41 seals only the lower surface of the substrate 41 including the window 43, and the EMC injected above the substrate 41 includes a substrate (including the semiconductor chip 42). Seal the top surface of 41) to proceed with the molding of the FBGA package.

이와 같은 방식으로 진행하는 본 발명의 FBGA 패키지의 몰딩방법은 기판(41)에 구비된 윈도우(43)가 반도체 칩(42)에 의해 전 영역이 가려지므로 기판(41)의 상측으로 주입된 EMC가 기판(41)의 하측으로 유입되지 않는다. According to the molding method of the FBGA package according to the present invention, since the entire area is covered by the semiconductor chip 42 of the window 43 provided on the substrate 41, the EMC injected into the upper side of the substrate 41 is increased. It does not flow into the lower side of the substrate 41.

이상에서 알 수 있는 바와 같이, 본 발명은 기판에 구비된 윈도우의 크기를 반도체 칩 크기 이하로 감소시킴으로써 기판의 상측으로 주입된 EMC가 기판의 윈도우를 통해 기판의 하측으로 유입되는 것을 방지할 수 있으며, 그 결과, 본 발명은 본딩와이어의 손상을 방지할 수 있다.  As can be seen from the above, the present invention can reduce the size of the window provided on the substrate to less than the size of the semiconductor chip to prevent the EMC injected into the upper side of the substrate to enter the lower side of the substrate through the window of the substrate As a result, the present invention can prevent damage to the bonding wires.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 사상과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다. As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope and spirit of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

Claims (1)

본딩패드를 구비한 반도체 칩이 회로패턴과 중앙에 윈도우를 구비한 기판 상에 페이스-다운 형태로 부착되고, 상기 기판에 구비된 윈도우를 관통하여 상기 반도체 칩의 본딩 패드와 상기 기판의 회로패턴 간을 와이어 본딩한 결과물을 하부 몰드 캡 형성을 위한 홈을 구비한 하부금형에 로딩시키는 단계와; 상기 기판 상측에 EMC(Epoxy Molding Compound) 충진 공간이 만들어지도록 하부금형 상에 상부금형을 배치시킨 상태로 금형의 일측에서 기판의 상측과 하측으로 EMC를 주입하는 단계를 포함하는 FBGA 패키지의 몰딩방법에 있어서, A semiconductor chip having a bonding pad is attached in a face-down manner on a circuit pattern and a substrate having a window in the center, and penetrates through a window provided in the substrate to between the bonding pad of the semiconductor chip and the circuit pattern of the substrate. Loading the result of wire bonding the lower mold with a groove for forming the lower mold cap; In the molding method of the FBGA package comprising the step of injecting EMC from one side of the mold to the upper side and the lower side of the mold while the upper mold is disposed on the lower mold to create an EMC (Epoxy Molding Compound) filling space on the upper side of the substrate. In 상기 기판의 윈도우는 기판의 상측으로 주입된 EMC가 기판의 윈도우를 통해 기판의 하측으로 유입되는 것을 방지하기 위해, 상기 반도체 칩에 의해 가려지도록 반도체 칩보다 작은 크기로 구비되는 것을 특징으로 하는 FBGA 패키지의 몰딩방법. The window of the substrate is a FBGA package characterized in that the size is smaller than the semiconductor chip to be covered by the semiconductor chip, in order to prevent the EMC injected into the upper side of the substrate to enter the lower side of the substrate through the window of the substrate Molding method.
KR1020040059179A 2004-07-28 2004-07-28 Method for molding in fbga package KR20060010464A (en)

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